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printed in japan document no. u15195ej5v0ud00 (5th edition) date published august 2005 n cp(k) v850e/ia2 32-bit single-chip microcontrollers hardware user?s manual pd703114 pd703114(a) pd70f3114 pd70f3114(a) 2001
2 user?s manual u15195ej5v0ud [memo]
3 user?s manual u15195ej5v0ud 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
4 user?s manual u15195ej5v0ud these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of march, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
5 user?s manual u15195ej5v0ud regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j05.6 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-265 40 10 ? tyskland filial taeby, sweden tel: 08-63 87 200 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
6 user?s manual u15195ej5v0ud preface readers this manual is intended for users who wish to understand the functions of the v850e/ia2 and design application systems using it. the target products are as follows. ? standard products: pd703114, 70f3114 ? special grade products: pd703114(a), 70f3114(a) purpose this manual is intended to give users an understanding of the hardware functions of the v850e/ia2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture (v850e1 architecture user?s manual). hardware architecture ? pin functions ? data type ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this ma nual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. cautions 1. the application examples in this manual a pply to ?standard? quality grade products for genera l electronic systems. when using an example in this manual fo r an application that requires a ?special? quality grade produc t, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. when using this manual as a manual for a special grade product, read the part numbers as follows. pd703114 703114(a) pd70f3114 70f3114(a) ? to find the details of a register where the name is known refer to appendix b register index . ? to understand the details of an instruction function refer to the v850e1 architecture user?s manual . ? to know details of the electric al specifications of the v850e/ia2 refer to chapter 16 electrical specifications .
7 user?s manual u15195ej5v0ud ? to understand the overall functions of the v850e/ia2 read this manual according to the contents . how to read register formats the name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file. when the register format of each regist er describes 0 or 1, other values are prohibited to be specified. the mark shows major revised points. conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (over score over pin or signal name) memory map address: top: higher, bottom: lower note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits
8 user?s manual u15195ej5v0ud related documents the related documents indicated in this publ ication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/ia2 document name document no. v850e1 architecture user?s manual u14559e v850e/ia2 hardware user?s manual this manual v850e/ia1, v850e/ia2 ac motor inverter control using vector operation application note u14868e inverter control by v850 series 120 excitation method control by zero- cross detection application note u17209e inverter control by v850 series vector control by encoder application note u17324e inverter control by v850 series vector control by hole sensor application note u17338e documents related to developm ent tools (user?s manuals) document name document no. ie-v850e-mc, ie-v850e-mc-a (in-circuit emulator) u14487e ie-703114-mc-em1 (in-circuit em ulator option board) u16533e operation u17293e c language u17291e assembly language u17292e ca850 (ver. 3.00) (c compiler package) link directives u17294e pm+ (ver. 6.00) (project manager) u17178e id850 (ver. 3.00) (integrated debugger) operation u17358e tw850 (ver. 2.00) (performance analysis tuning tool) u17241e sm850 (ver. 2.50) (system si mulator) operation u16218e sm850 (ver. 2.00 or later) (system simulator) external part user open interface specification u14873e operation u17246e sm+ (system simulator) user open interface u17247e basics u13430e installation u13410e rx850 (ver. 3.13 or later) (real-time os) technical u13431e basics u13773e installation u13774e rx850 pro (ver. 3.15) (real-time os) technical u13772e rd850 (ver. 3.01) (task debugger) u13737e rd850 pro (ver. 3.01) (task debugger) u13916e az850 (ver. 3.10) (system performance analyzer) u14410e pg-fp4 flash memory programmer u15260e
9 user?s manual u15195ej5v0ud contents chapter 1 introduction ...................................................................................................... ...........17 1.1 outline........................................................................................................................ ................ 17 1.2 features ....................................................................................................................... .............. 19 1.3 applications................................................................................................................... ............ 21 1.4 ordering information ........................................................................................................... ..... 21 1.5 pin configuration (top view)........................................ ........................................................... 22 1.6 configuration of function block................................... .......................................................... 25 1.6.1 internal bl ock di agram ......................................................................................................... .........25 1.6.2 internal units................................................................................................................. ................26 chapter 2 pin functions .................................................................................................... ............28 2.1 list of pin functions .......................................................................................................... ...... 28 2.2 pin status..................................................................................................................... .............. 33 2.3 description of pin functions ......................................... .......................................................... 34 2.4 types of pin i/o circuits and connection of unused pins................................................... 43 2.5 pin i/o circuits ............................................................................................................... ........... 45 chapter 3 cpu function..................................................................................................... ............46 3.1 features ....................................................................................................................... .............. 46 3.2 cpu register set ............................................................................................................... ....... 47 3.2.1 program regi ster set........................................................................................................... ..........48 3.2.2 system regi ster set............................................................................................................ ...........49 3.3 operation modes................................................................................................................ ....... 55 3.3.1 operation modes................................................................................................................ ..........55 3.3.2 operation mode specific ation ................................................................................................... ....56 3.4 address space .................................................................................................................. ........ 57 3.4.1 cpu addre ss space .............................................................................................................. .......57 3.4.2 image .......................................................................................................................... .................58 3.4.3 wrap-around of cpu address s pace............................................................................................59 3.4.4 memory map ..................................................................................................................... ...........60 3.4.5 area........................................................................................................................... ...................61 3.4.6 external memo ry expans ion ...................................................................................................... ...65 3.4.7 recommended use of address s pace ..........................................................................................66 3.4.8 on-chip periphera l i/o registers ............................................................................................... ....68 3.4.9 specific re gisters ............................................................................................................. .............78 3.4.10 system wait control register (vswc) ...........................................................................................7 8 3.4.11 cautio ns ....................................................................................................................... ................78 chapter 4 bus control function............................................................................................ .80 4.1 features ....................................................................................................................... .............. 80 4.2 bus control pins............................................................................................................... ........ 80 4.2.1 pin status during internal rom, internal ram, and on-chip per ipheral i/o access .......................80 4.3 memory block function .......................................................................................................... .81
10 user?s manual u15195ej5v0ud 4.3.1 chip select co ntrol f unction................................................................................................... ....... 82 4.4 bus cycle type control function .................................... ....................................................... 85 4.5 bus access ..................................................................................................................... ........... 86 4.5.1 number of ac cess cl ocks........................................................................................................ ..... 86 4.5.2 bus sizing functi on............................................................................................................ ........... 87 4.5.3 bus wid th ...................................................................................................................... ............... 88 4.6 wait function.................................................................................................................. ........... 94 4.6.1 programmable wa it func tion ..................................................................................................... ... 94 4.6.2 external wait function ......................................................................................................... ......... 96 4.6.3 relationship between programmable wait a nd external wait ....................................................... 96 4.7 idle state insertion function............................................. ..................................................... .. 97 4.8 bus priority order ............................................................................................................. ........ 98 4.9 boundary operation conditions........................................ ...................................................... 99 4.9.1 program space .................................................................................................................. .......... 99 4.9.2 data s pace ..................................................................................................................... ............. 99 chapter 5 memory access control function ................................................................ 100 5.1 sram, external rom, external i/o interface........................................................................ 100 5.1.1 featur es ....................................................................................................................... ............. 100 5.1.2 sram, external rom, external i/o access ............................................................................... 101 chapter 6 dma functions (dma controller) ................................................................... 105 6.1 features ....................................................................................................................... ............ 105 6.2 configuration.................................................................................................................. ......... 106 6.3 control registers .............................................................................................................. ...... 107 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 ) ............................................................. 107 6.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3)....................................................... 109 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3 )................................................................ 111 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc 3) ................................................... 112 6.3.5 dma channel control register s 0 to 3 (dchc 0 to dchc3 )........................................................ 114 6.3.6 dma disable status register (ddis)........................................................................................... 11 6 6.3.7 dma restart regi ster (drst) .................................................................................................... . 116 6.3.8 dma trigger factor regi sters 0 to 3 (dtfr 0 to d tfr3) ............................................................. 117 6.4 transfer modes................................................................................................................. ....... 120 6.4.1 single trans fer m ode ........................................................................................................... ...... 120 6.4.2 single-step tran sfer mode...................................................................................................... .... 122 6.4.3 block trans fer m ode............................................................................................................ ....... 123 6.5 transfer types................................................................................................................. ........ 123 6.5.1 two-cycle tr ansfer ............................................................................................................. ........ 123 6.6 transfer target ................................................................................................................ ........ 124 6.6.1 transfer type and transfer target .............................................................................................. . 124 6.6.2 external bus cycles during dma transfer (two-cycl e transfe r) ................................................... 125 6.7 dma channel priorities ......................................................................................................... . 125 6.8 next address setting function......................................... ..................................................... 125 6.9 dma transfer start factors ................................................................................................... 12 7 6.10 forcible suspension ............................................................................................................ ... 128 6.11 dma transfer end ............................................................................................................... .... 128
11 user?s manual u15195ej5v0ud 6.12 forcible termination ........................................................................................................... ... 129 6.12.1 restrictions on forcible te rmination of dm a transfe r ..................................................................130 6.13 time required for dma transfer .......................................................................................... 131 6.14 cautions....................................................................................................................... ............ 132 chapter 7 interrupt/exception processing function..................................................134 7.1 features ....................................................................................................................... ............ 134 7.2 non-maskable interrupt......................................................................................................... . 138 7.2.1 operation ...................................................................................................................... .............139 7.2.2 restore........................................................................................................................ ...............141 7.2.3 non-maskable interrupt status fl ag (np) ....................................................................................142 7.2.4 edge detecti on func tion........................................................................................................ ......142 7.3 maskable interrupts ............................................................................................................ .... 143 7.3.1 oper ation ................................................................................................................ ...................143 7.3.2 restore........................................................................................................................ ...............145 7.3.3 priorities of ma skable inte rrupts .............................................................................................. ...146 7.3.4 interrupt control r egister ( xxicn)............................................................................................. ....150 7.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) ..........................................................................153 7.3.6 in-service priority register (ispr) ............................................................................................ ...154 7.3.7 maskable interrupt st atus flag (id)............................................................................................ ..155 7.3.8 interrupt trigger mode sele ction............................................................................................... ...155 7.4 software exception............................................................................................................. .... 163 7.4.1 operation ...................................................................................................................... .............163 7.4.2 restore........................................................................................................................ ...............164 7.4.3 exception stat us flag (ep) ..................................................................................................... .....165 7.5 exception trap ................................................................................................................. ....... 166 7.5.1 illegal opcode definit ion...................................................................................................... ........166 7.5.2 debug trap ..................................................................................................................... ............168 7.6 multiple interrupt servicing contro l ..................................................................................... 170 7.7 interrupt response time........................................................................................................ 172 7.8 periods in which cpu does not acknowledge interr upts ................................................. 173 chapter 8 clock generation function ...............................................................................174 8.1 features ................................................................................................................... ................ 174 8.2 configuration .............................................................................................................. ............ 174 8.3 input clock selection ...................................................................................................... ....... 175 8.3.1 direc t mode .............................................................................................................. ..................175 8.3.2 p ll mode................................................................................................................. ..................175 8.3.3 peripheral co mmand register (phcmd)..................................................................................... 176 8.3.4 clock control register (ckc)............................................................................................ ...........177 8.3.5 peripheral st atus regist er (phs)....................................................................................... ..........179 8.4 pll lockup................................................................................................................. ............. 180 8.5 power save control ......................................................................................................... ....... 181 8.5.1 overvi ew ............................................................................................................... .....................181 8.5.2 contro l regist ers ...................................................................................................... ...................184 8.5.3 ha lt m ode .............................................................................................................. ..................187 8.5.4 id le m ode .............................................................................................................. ...................189
12 user?s manual u15195ej5v0ud 8.5.5 softwar e stop mode ..................................................................................................... ........... 191 8.6 securing oscillation stabilization time........................ ........................................................ 193 8.6.1 oscillation stabilization time secu rity specif ication.................................................................. ... 193 8.6.2 time bas e counter (tbc) ................................................................................................ .......... 194 chapter 9 timer/counter function ....................................................................................... 195 9.1 timer 0.................................................................................................................... .................. 195 9.1.1 featur es (tim er 0) ..................................................................................................... ................. 195 9.1.2 function ov erview (t imer 0) ............................................................................................ ........... 196 9.1.3 functions ad ded to v8 50e/ia2 ........................................................................................... ....... 197 9.1.4 basic configuration .................................................................................................... ................ 198 9.1.5 contro l regist ers ...................................................................................................... .................. 205 9.1.6 o peratio n.............................................................................................................. ..................... 229 9.1.7 oper ation ti ming ....................................................................................................... ................. 285 9.2 timer 1.................................................................................................................... .................. 294 9.2.1 featur es (tim er 1) ..................................................................................................... ................. 294 9.2.2 function ov erview (t imer 1) ............................................................................................ ........... 294 9.2.3 basic configuration .................................................................................................... ................ 296 9.2.4 contro l regist ers ...................................................................................................... .................. 299 9.2.5 o peratio n.............................................................................................................. ..................... 310 9.2.6 supplementary descrip tion of intern al operat ion........................................................................ 319 9.3 timer 2.................................................................................................................... .................. 322 9.3.1 featur es (tim er 2) ..................................................................................................... ................. 322 9.3.2 function ov erview (t imer 2) ............................................................................................ ........... 322 9.3.3 basic configuration .................................................................................................... ................ 324 9.3.4 contro l regist ers ...................................................................................................... .................. 330 9.3.5 o peratio n.............................................................................................................. ..................... 347 9.3.6 pwm output operation in timer 2 co mpare m ode ...................................................................... 365 9.4 timer 3.................................................................................................................... .................. 368 9.4.1 features (timer 3) ....................................................................................................... ............... 368 9.4.2 function over view (tim er 3) .............................................................................................. ......... 368 9.4.3 function adde d to v 850e/ia2.............................................................................................. ...... 369 9.4.4 basic c onfigurat ion ...................................................................................................... .............. 369 9.4.5 contro l regist ers ...................................................................................................... .................. 373 9.4.6 o peratio n.............................................................................................................. ..................... 380 9.4.7 applic ation ex amples................................................................................................... .............. 388 9.4.8 cautio ns ............................................................................................................... ..................... 394 9.5 timer 4.................................................................................................................... .................. 395 9.5.1 featur es (tim er 4) ..................................................................................................... ................. 395 9.5.2 function ov erview (t imer 4) ............................................................................................ ........... 395 9.5.3 basic c onfigurat ion ..................................................................................................... ............... 396 9.5.4 cont rol regi ster ....................................................................................................... ................... 400 9.5.5 o peratio n.............................................................................................................. ..................... 401 9.5.6 applic ation ex ample .................................................................................................... .............. 403 9.5.7 cautio ns ............................................................................................................... ..................... 403 9.6 timer connection function ................................................................................................. .. 404 9.6.1 overview............................................................................................................... ..................... 404 9.6.2 control re gister ............................................................................................................... ........... 405
13 user?s manual u15195ej5v0ud chapter 10 serial interface function ................................................................................406 10.1 features .................................................................................................................. ................. 406 10.1.1 selecting ua rt1 or cs i1 mode.......................................................................................... .......407 10.2 asynchronous serial interfa ce 0 (uart0) ........................................................................... 408 10.2.1 featur es .............................................................................................................. .......................408 10.2.2 conf iguration ......................................................................................................... .....................409 10.2.3 contro l regist ers ..................................................................................................... ....................411 10.2.4 interr upt requests .................................................................................................... ...................418 10.2.5 o peratio n ............................................................................................................. ......................419 10.2.6 dedicated baud rate generator 0 (b rg0)................................................................................ ...431 10.2.7 cautio ns .............................................................................................................. .......................438 10.3 asynchronous serial interfa ce 1 (uart1) ........................................................................... 439 10.3.1 featur es .............................................................................................................. .......................439 10.3.2 conf iguration ......................................................................................................... .....................440 10.3.3 contro l regist ers ..................................................................................................... ....................442 10.3.4 interr upt requests .................................................................................................... ...................451 10.3.5 o peratio n ............................................................................................................. ......................452 10.3.6 sync hronous mode ...................................................................................................... ..............462 10.3.7 dedicated baud rate generator 1 (b rg1)................................................................................ ...467 10.4 clocked serial interfaces 0, 1 (csi0, csi1)........................................................................... 47 4 10.4.1 featur es .............................................................................................................. .......................474 10.4.2 conf iguration ......................................................................................................... .....................475 10.4.3 contro l regist ers ..................................................................................................... ....................478 10.4.4 o peratio n ............................................................................................................. ......................492 10.4.5 ou tput pins ........................................................................................................... ......................507 10.4.6 dedicated baud rate generator 3 (b rg3)................................................................................ ...508 chapter 11 a/d converter ................................................................................................... .......512 11.1 features ................................................................................................................ ................... 512 11.2 configuration ........................................................................................................... ............... 512 11.3 functions added to v850e/ia2................................ ............................................................ .. 516 11.4 control registers....................................................................................................... ............. 517 11.5 interrupt requests ...................................................................................................... ............ 528 11.6 a/d converter operation................................................................................................. ....... 529 11.6.1 a/d converte r basic o peration ......................................................................................... ...........529 11.6.2 operation mo des and trig ger m odes ..................................................................................... .....530 11.7 operation in a/d trigger mode........................................................................................... ... 533 11.7.1 operation in select mode .............................................................................................. .............533 11.7.2 operatio n in sc an mode ................................................................................................ .............534 11.8 operation in a/d trigger polling mode.................. ............................................................... 53 5 11.8.1 operation in select mode .............................................................................................. .............535 11.8.2 operatio n in sc an mode ................................................................................................ .............536 11.9 operation in timer trigger mode ......................................................................................... . 537 11.9.1 operation in select mode .............................................................................................. .............537 11.9.2 operatio n in sc an mode ................................................................................................ .............538 11.10 operation in external trigger mode........................ .............................................................. 5 39 11.10.1 operation in select mode ............................................................................................. ..............539
14 user?s manual u15195ej5v0ud 11.10.2 operatio n in sc an mode ............................................................................................... ............. 540 11.11 operation cautions ....................................................................................................... .......... 541 11.11.1 stopping a/d c onversion o peratio n .................................................................................... ....... 541 11.11.2 trigger input duri ng a/d conversi on operat ion ........................................................................ .. 541 11.11.3 external or timer trigger interval................................................................................... .............. 541 11.11.4 operation in standby modes............................................................................................ .......... 541 11.11.5 compare match interru pt in timer trigger mode ........................................................................ . 541 11.11.6 timing that makes the a/ d conversion resu lt undef ined............................................................ 542 11.12 how to read a/d converter ch aracteristics table.............................................................. 543 chapter 12 port functions .................................................................................................. ..... 547 12.1 features .................................................................................................................. ................. 547 12.2 basic configuration of ports ............................................................................................ ..... 547 12.3 pin functions of each port .............................................................................................. ...... 563 12.3.1 port 0................................................................................................................ ......................... 563 12.3.2 port 1................................................................................................................ ......................... 564 12.3.3 port 2................................................................................................................ ......................... 566 12.3.4 port 3................................................................................................................ ......................... 568 12.3.5 port 4................................................................................................................ ......................... 570 12.3.6 port dh............................................................................................................... ....................... 572 12.3.7 port dl ............................................................................................................... ....................... 574 12.3.8 port ct ............................................................................................................... ....................... 576 12.3.9 port cm ............................................................................................................... ...................... 578 12.4 operation of port function .................................................................................................... 5 80 12.4.1 writing to i/o port ............................................................................................................ .......... 580 12.4.2 reading from i/o port .......................................................................................................... ...... 580 12.4.3 output status of alternate function in co ntrol m ode ................................................................... 580 12.5 noise eliminator ........................................................................................................ .............. 581 12.5.1 inte rrupt pins ........................................................................................................ ...................... 581 12.5.2 timer 10, timer 3 i nput pi ns .......................................................................................... ............. 581 12.5.3 timer 2 input pins .................................................................................................... .................. 585 12.6 cautions................................................................................................................. .................... 588 12.6.1 hysteresis characte ristics ............................................................................................ .............. 588 chapter 13 reset function.................................................................................................. ...... 589 13.1 features ................................................................................................................ ................... 589 13.2 pin functions........................................................................................................... ................ 589 13.3 initialization.......................................................................................................... .................... 594 chapter 14 regulator ........................................................................................................ ......... 599 14.1 features ................................................................................................................ ................... 599 14.2 functional outline...................................................................................................... ............. 599 14.3 connection example...................................................................................................... ......... 600 14.4 control register ......................................................................................................... ............. 602
15 user?s manual u15195ej5v0ud chapter 15 flash memory ( pd70f3114).................................................................................603 15.1 features ....................................................................................................................... ............ 603 15.2 writing using flash programmer.................................. ........................................................ 603 15.3 programming environment.................................................................................................... 606 15.4 communication mode ............................................................................................................ 6 06 15.5 pin connection................................................................................................................. ....... 608 15.5.1 mode1/v pp pin ..........................................................................................................................6 08 15.5.2 serial in terface pin.................................................................................................... ..................608 15.5.3 reset pin ............................................................................................................... ..................610 15.5.4 nm i pin................................................................................................................. ......................610 15.5.5 mode0, mode1 pins ..................................................................................................... ...........610 15.5.6 po rt pi ns ............................................................................................................. ........................610 15.5.7 other signal pins ..................................................................................................... ...................610 15.5.8 po wer su pply.......................................................................................................... ....................610 15.6 programming method............................................................................................................. 611 15.6.1 flash me mory c ontrol.................................................................................................. ...............611 15.6.2 flash memo ry program ming m ode......................................................................................... ....612 15.6.3 selection of communica tion mode....................................................................................... .......612 15.6.4 communica tion co mmands ................................................................................................ ........613 15.7 flash memory programming by self-programming.... ........................................................ 614 15.7.1 outline of self-pr ogrammi ng ........................................................................................... ............614 15.7.2 self-pro gramming f unction ............................................................................................. ............615 15.7.3 outline of self -programming interface ................................................................................. .......615 15.7.4 hardware environment .................................................................................................. .............616 15.7.5 softwar e environment .................................................................................................. ..............618 15.7.6 self-progr amming func tion number ...................................................................................... ......619 15.7.7 calli ng parameters .................................................................................................... .................620 15.7.8 contents of ram par ameters ............................................................................................ .........621 15.7.9 errors durin g self-pr ogramming........................................................................................ ..........622 15.7.10 flash info rmation.............................................................................................................. ..........622 15.7.11 area num ber .................................................................................................................... ..........623 15.7.12 flash programming mode cont rol register (flpmc ) ..................................................................624 15.7.13 calling device inte rnal proc essing ............................................................................................. .626 15.7.14 erasing flash memory flow ...................................................................................................... ...629 15.7.15 continuous wr iting flow ........................................................................................................ ......630 15.7.16 internal ve rify flow ........................................................................................................... ...........631 15.7.17 acquiring flash in formation flow............................................................................................... ...632 15.7.18 self-programmi ng libr ary ....................................................................................................... .....633 15.8 how to distinguish flash memory and mask rom versions............... .............................. 635 chapter 16 electrical specifications..................................................................................636 16.1 normal operation mode ......................................................................................................... 6 36 16.2 flash memory programming mode............................... ........................................................ 658 chapter 17 package drawings................................................................................................ .660
16 user?s manual u15195ej5v0ud chapter 18 recommended soldering conditions........................................................... 662 appendix a notes on target system design ................................................................... 664 appendix b register index .................................................................................................. ....... 666 appendix c instruction set list ........................................................................................... .. 675 c.1 conventions................................................................................................................ ............. 675 c.2 instruction set (alphabetical order) ..................................................................................... 67 8 appendix d revision history ................................................................................................ ..... 684 d.1 major revisions in this edition............................................................................................ . 684 d.2 revision history up to previous edition .............................................................................. 686
17 user?s manual u15195ej5v0ud chapter 1 introduction the v850e/ia2 is a product in nec electronics? v850 series of single-chip microcontrollers. this chapter provides an overview of the v850e/ia2. 1.1 outline the v850e/ia2 is a 32-bit single-chip microcontroller that uses high-speed operations to realize high-precision inverter control of motors. it uses the v850e1 cpu of t he v850 series and has on-chip peripheral functions such as rom, ram, a bus interface, a dma cont roller, timers including a 3-phase si ne-wave pwm timer fo r motors, serial interfaces, and a/d converters. (1) v850e1 cpu the v850e1 cpu supports a risc instruction set in which the instruction exec ution speed is increased greatly through the use of basic instru ctions that execute one instruction per clock, and an optimized pipeline. moreover, it supports multiply instru ctions using a 32-bit hardware multip lier, saturated product-sum operation instructions, and bit manipulation inst ructions as optimum instructions for digital servo control applications. object code efficiency is increased in the c compiler by using 2-byte-length basic instructions and instructions corresponding to high-level la nguages, which promote a compact program. furthermore, since the interrupt response time, including pr ocessing by the on-chip interrupt controller, is also fast, this cpu is ideal for advanced real-time control. (2) external bus interface function a bus configuration consisting of a multiplexed addr ess bus (22 bits) and data bus (8 bits or 16 bits selectable) suitable for compact system design is used as the external bus interface. sram and rom memories can be connected. in the dma controller, transfer is started using softw are and transfers between external memories can be made concurrent with internal cpu operations or data tr ansfers. real-time control such as motor control or communication control can also be realized simulta neously due to high-speed, high-performance cpu instruction execution. (3) on-chip flash memory ( pd70f3114) the on-chip flash memory version ( pd70f3114), which has a quickly accessible flash memory on-chip, can shorten system development time since it is possible to rewrite a program with t he v850e/ia2 mounted in an application system. moreover, it can greatly im prove maintainability after a system is shipped. (4) complete middleware, development environment the v850e/ia2 can execute jpeg, jbig, mh/mr/mmr and ot her middleware at high speeds. moreover, since middleware for realizing speech recognition, voic e synthesis, and other processing also is provided, multimedia systems can be realized easily. a development environment that integrates an optimized c compiler, debugger, in-circuit emulator, simulator, and system performance analyzer is also provided.
chapter 1 introduction 18 user?s manual u15195ej5v0ud table 1-1 lists the differences between the v850e/ia 1 and v850e/ia2. table 1-2 lists the differences between the v850e/ia1 and v850e/ia2 register setting values. table 1-1. differences between v850e/ia1 and v850e/ia2 item v850e/ia1 v850e/ia2 maximum operating frequency 50 mhz note 40 mhz mask rom pd703116: 256 kb pd703114: 128 kb internal rom flash memory pd70f3116: 256 kb pd70f3114: 128 kb internal ram 10 kb 6 kb timer 00, 01 provided buffer register, compare register, and compare match interrupt added timer 10, 11 provided timer 10: provided, timer 11: not provided timer 20, 21 provided provided timer 3 provided to3 output buffer off function added by intp4 input timer timer 4 provided provided uart0 provided provided uart1 provided provided (pins multiplexed with csi1) uart2 provided not provided csi0 provided provided csi1 provided provided (pins multiplexed with uart1) serial interface fcan provided not provided debug support function nbd provided not provided analog input total of two circuits: 16 ch a/d converter 0: 8 ch a/d converter 1: 8 ch total of two circuits: 14 ch a/d converter 0: 6 ch a/d converter 1: 8 ch a/d converter av dd , av ref pins independent pins alternate-function pins supply voltage v dd3 = 3.3 v 0.3 v v dd5 = 5.0 v 0.5 v v dd = rv dd = 5.0 v 0.5 v internal regulator package 144-pin plastic lqfp 100-pin plastic lqfp 100-pin plastic qfp note the maximum operating frequency of the in-circuit emulator is 40 mhz. a frequency of 50 mhz can be supported by upgrading the in-circuit emulator, so contact an nec el ectronics sales representative or distributor. remark for details, refer to the user?s manual of each product.
chapter 1 introduction 19 user?s manual u15195ej5v0ud table 1-2. differences between v850e /ia1 and v850e/ia2 register setting values register name v850e/ia1 v850e/ia2 system wait control register (vswc) 12h 02h timer 1/timer 2 clock selection register (prm02) 00h or 01h 01h (initial value 00h) remark for details, refer to the user?s manual of each product. 1.2 features number of instructions 80 minimum instruction execution time 25 ns (@ internal 40 mhz operation) general-purpose registers 32 bits 32 registers instruction set v850e1 (nb85e) cpu signed multiplication (32 bits 32 bits 64 bits): 1 or 2 clocks saturated operation instructions (wit h overflow/underflow detection function) 32-bit shift instruction: 1 clock bit manipulation instructions long/short format load/store instructions signed load instructions memory space 4 mb linear address space (shared by program and data) memory block division function: 2 mb/block programmable wait function idle state insertion function external bus interface 16-bit data bus (address/data multiplexed) 16-/8-bit bus sizing function external wait function internal memory part number internal rom internal ram pd703114 128 kb (mask rom) 6 kb pd70f3114 128 kb (flash memory) 6 kb interrupts/exceptions external interrupts: 16 (including nmi) internal interrupts: 42 sources exceptions: 1 source 8 levels of priority can be specified
chapter 1 introduction 20 user?s manual u15195ej5v0ud dma controller 4-channel configuration transfer unit: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: 2-cycle transfer transfer modes: single transfer, single-step transfer, block transfer transfer subjects: memory ? memory, memory ? i/o, i/o ? i/o transfer requests: on-c hip peripheral i/o, software next address setting function i/o lines input ports: 6 i/o ports: 47 timer/counter function 16-bit timer for 3-phase sine wave pwm inverter control: 2 channels 16-bit up/down counter/timer for 2-phase encoder input: 1 channel general-purpose 16-bit timer/counter: 2 channels general-purpose 16-bit timer/event counter: 1 channel 16-bit interval timer: 1 channel serial interface asynchronous serial interface (uart): 2 channels clocked serial interface (csi): 2 channels of the four channels, two channels are used for both csi and uart and therefore one or the other function must be selected. a/d converter 10-bit resolution a/d converter: 6 channels + 8 channels (2 units) regulator two power supplies, one for the internal cpu and one for the peripheral interface, are not necessary. a 5 v single-power-supply system can be configured by connecting an n-ch transistor (2sd1950 (vl standard product, surface mount type) or 2sd1581 (independent type) is recommended). if a 3.3 v power supply is available, it can be directly connected to the regin pin. clock generator multiplication function ( 1, 2.5, 5, 10) using pll clock synthesizer divide-by-2 function using external clock input power-saving function halt, idle, and software stop modes package 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) cmos technology fully static circuits
chapter 1 introduction 21 user?s manual u15195ej5v0ud 1.3 applications ? pd703114, 70f3114: consumer equipment (inverter air conditioners) industrial equipment (motor cont rol, general-purpose inverters) ? pd703114(a), 70f3114(a): automobile applications (electrical power steering) 1.4 ordering information part number package quality grade pd703114gc- -8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd703114gc- -8eu-a 100-pin plastic lqfp (fine pitch) (14 14) standard pd703114gc(a)- -8eu 100-pin plastic lqfp (fine pitch) (14 14) special pd703114gc(a)- -8eu-a 100-pin plastic lqfp (fine pitch) (14 14) special pd703114gf- -3ba 100-pin plastic qfp (14 20) standard pd703114gf- -3ba-a 100-pin plastic qfp (14 20) standard pd70f3114gc-8eu 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3114gc-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) standard pd70f3114gc(a)-8eu 100-pin plastic lqfp (fine pitch) (14 14) special pd70f3114gc(a)-8eu-a 100-pin plastic lqfp (fine pitch) (14 14) special pd70f3114gf-3ba 100-pin plastic qfp (14 20) standard pd70f3114gf-3ba-a 100-pin plastic qfp (14 20) standard remarks 1. indicates rom code suffix. 2. products with -a at the end of the part number are lead-free products. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec electronics corporation to know the specification of the quality grade on the device and its recommended applications.
chapter 1 introduction 22 user?s manual u15195ej5v0ud 1.5 pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14) pd703114gc- -8eu pd70f3114gc-8eu pd703114gc- -8eu-a pd70f3114gc-8eu-a pd703114gc(a)- -8eu pd70f3114gc(a)-8eu pd703114gc(a)- -8eu-a pd70f3114gc(a)-8eu-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 txd0/p31 si1/rxd1/p32 so1/txd1/p33 sck1/asck1/p34 ti2/intp20/p20 to21/intp21/p21 to22/intp22/p22 to23/intp23/p23 to24/intp24/p24 tclr2/intp25/p25 ti3/intp30/tclr3/p26 to3/intp31/p27 v ss v dd pdl0/ad0 pdl1/ad1 pdl2/ad2 pdl3/ad3 pdl4/ad4 pdl5/ad5 pdl6/ad6 pdl7/ad7 pdl8/ad8 pdl9/ad9 pdl10/ad10 ani04 ani03 ani02 ani01 ani00 av ss0 av dd0 to015 to014 to013 to012 to011 to010 v ss v dd to005 to004 to003 to002 to001 to000 intp4/to3off/p05 adtrg1/intp3/p04 adtrg0/intp2/p03 eso1/intp1/p02 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ani05 av dd1 av ss1 ani10 ani11 ani12 ani13 ani14 ani15 ani16 ani17 mode0 v ss3 rv dd regout regin x1 x2 reset cv ss cksel si0/p40 so0/p41 sck0/p42 rxd0/p30 eso0/intp0/p01 nmi/p00 note 2 tclr10/intp101/p12 tcud10/intp100/p11 tiud10/to10/p10 pcm1/clkout pcm0/wait pct6/astb pct4/rd pct1/uwr pct0/lwr v dd v ss3 mode1/v pp note 1 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 notes 1. pd70f3114 only 2. the nmi/p00 pin always functions as the nmi pin. the level of the nmi pin can be read by reading the p0.p00 bit.
chapter 1 introduction 23 user?s manual u15195ej5v0ud ? 100-pin plastic qfp (14 20) pd703114gf- -3ba pd70f3114gf-3ba pd703114gf- -3ba-a pd70f3114gf-3ba-a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 sck1/asck1/p34 ti2/intp20/p20 to21/intp21/p21 to22/intp22/p22 to23/intp23/p23 to24/intp24/p24 tclr2/intp25/p25 ti3/intp30/tclr3/p26 to3/intp31/p27 v ss v dd pdl0/ad0 pdl1/ad1 pdl2/ad2 pdl3/ad3 pdl4/ad4 pdl5/ad5 pdl6/ad6 pdl7/ad7 pdl8/ad8 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 adtrg1/intp3/p04 adtrg0/intp2/p03 eso1/intp1/p02 eso0/intp0/p01 nmi/p00 note 2 tclr10/intp101/p12 tcud10/intp100/p11 tiud10/to10/p10 pcm1/clkout pcm0/wait pct6/astb pct4/rd pct1/uwr pct0/lwr v dd v ss3 mode1/v pp note 1 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ani03 ani04 ani05 av dd1 av ss1 ani10 ani11 ani12 ani13 ani14 ani15 ani16 ani17 mode0 v ss3 rv dd regout regin x1 x2 reset cv ss cksel si0/p40 so0/p41 sck0/p42 rxd0/p30 txd0/p31 si1/rxd1/p32 so1/txd1/p33 ani02 ani01 ani00 av ss0 av dd0 to015 to014 to013 to012 to011 to010 v ss v dd to005 to004 to003 to002 to001 to000 intp4/to3off/p05 notes 1. pd70f3114 only 2. the nmi/p00 pin always functions as the nmi pin. the level of the nmi pin can be read by reading the p0.p00 bit.
chapter 1 introduction 24 user?s manual u15195ej5v0ud pin identification a16 to a21: ad0 to ad15: adtrg0, adtrg1: ani00 to ani05, ani10 to ani17: asck1: astb: av dd0 , av dd1 : av ss0 , av ss1 : cksel: clkout: cv ss : eso0, eso1: intp0 to intp4, intp100, intp101, intp20 to intp25, intp30, intp31: lwr: mode0, mode1: nmi: p00 to p05: p10 to p12: p20 to p27: p30 to p34: p40 to p42: pcm0, pcm1: pct0, pct1, pct4, pct6: address bus address/data bus a/d trigger input analog input asynchronous serial clock address strobe analog power supply analog ground clock generator operating mode select clock output clock generator ground emergency shut off external interrupt input lower write strobe mode non-maskable interrupt request port 0 port 1 port 2 port 3 port 4 port cm port ct pdh0 to pdh5: pdl0 to pld15: rd: reset: regin: regout: rv dd : rxd0, rxd1: sck0, sck1: si0, si1: so0, so1: tclr10, tclr2, tclr3: tcud10: ti2, ti3: tiud10: to000 to to005, to010 to to015, to10, to21 to to24, to3: to3off: txd0, txd1: uwr: v dd : v pp : v ss , v ss3 : wait: x1, x2: port dh port dl read strobe reset regulator input regulator output regulator power supply receive data serial clock serial input serial output timer clear timer control pulse input timer input timer count pulse input timer output timer output 3 off transmit data upper write strobe power supply programming power supply ground wait crystal
chapter 1 introduction 25 user?s manual u15195ej5v0ud 1.6 configuration of function block 1.6.1 internal block diagram timer 0: tm00, tm01 timer 1: tm10 timer 2: tm20, tm21 timer 3: tm3 timer 4: tm4 intc nmi intp2, intp3 intp0/eso0, intp1/eso1, intp4/to3off, intp20/ti2, intp21/to21 to intp24/to24, intp25/tclr2, intp30/ti3/tclr3, intp31/to3, intp100/tcud10, intp101/tclr10 to000 to to005, to010 to to015 tiud10/to10 note 1 instruction queue pc 32-bit barrel shifter multiplier 32 32 64 cpu rom ram bcu alu cksel clkout x1 x2 cv ss mode0, mode1 /v pp note 2 reset v dd v ss v ss3 pdl0 to pdl15 pdh0 to pdh5 pct0, pct1, pct4, pct6 pcm0, pcm1 p40 to p42 p30 to p34 p20 to p27 p10 to p12 p00 to p05 adtrg0 ani00 to ani05 av ss0 av dd0 adtrg1 ani10 to ani17 av ss1 av dd1 system registers general- purpose registers 32 bits 32 ports adc0 adc1 cg regin regout rv dd v ss3 regulator system controller 6 kb rd uwr lwr astb wait ad0 to ad15 a16 to a21 uart0 uart1 csi1 csi0 txd0 rxd0 so1/txd1 si1/rxd1 sck1/asck1 so0 si0 sck0 sramc romc dmac memc notes 1. pd703114: 128 kb (mask rom) pd70f3114: 128 kb (flash memory) 2. pd70f3114 only
chapter 1 introduction 26 user?s manual u15195ej5v0ud 1.6.2 internal units (1) cpu the cpu uses 5-stage pipeline control to execute address calculation, ar ithmetic and logica l operation, data transfer, and most other instruction processing in one clock. a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accele rate complex instruction processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on a physical addr ess obtained from the cpu. if there is no bus cycle start request from the cp u when fetching an instruction from an external memory area, the bcu generates a prefetch addres s and prefetches the instruction code. t he prefetched instruction code is fetched into the internal instruction queue of the cpu. (3) memory controller (memc) the memc controls sram, rom, and various i/o for external memory expansion. (4) dma controller (dmac) the dmac transfers data between memo ry and i/o in place of the cpu. the address mode is two-cycle transfer. the three bus modes are single transfer, single-step transfer, and block transfer. (5) rom the pd703114 includes mask rom (128 kb), and the pd70f3114 includes flash memory (128 kb). on an instruction fetch, the rom can be accessed by the cpu in one clock. when single-chip mode or flash memory programming mode is set, rom is mapped starting from address 00000000h. rom cannot be accessed if romless mode is set. (6) ram ram is mapped starting from address ffffc000h. it can be accessed by the cpu in one clo ck on an instruction fetch or data access. (7) interrupt controller (intc) the intc services hardware interrupt requests from on-chip peripheral i/o and external sources (nmi, intp0 to intp4, intp20 to intp25, intp30, intp31, intp10 0, intp101). for these interrupt requests, eight levels of interrupt priority can be defined and multip rocessing controls against the interrupt sources can be performed. (8) clock generator (cg) the cg provides a frequency t hat is 1, 2.5, 5, or 10 times (using the on-chip pll) or 0.5 times (not using the on-chip pll) the input clock (f x ) as the internal system clock (f xx ). as the input clock, connect an external resonator to pins x1 and x2 (only when using the on-chip pll synthesizer) or input an external clock from the x1 pin.
chapter 1 introduction 27 user?s manual u15195ej5v0ud (9) timer/counter function this unit incorporates a 2-channel 16-bit timer (tm0 ) for 3-phase sine wave pwm inverter control, a 1- channel 16-bit up/down counter (tm1) that can be us ed for 2-phase encoder input or as a general-purpose timer, a 2-channel 16-bit ge neral-purpose timer unit (tm2 ), a 1-channel 16-bit time r/event counter (tm3), and a 1-channel 16-bit interval timer (tm4) on-chip, and can measure the pulse interval or frequency and can output a programmable pulse. (10) serial interface a total of four channels of serial interfaces, including asynchronous serial interface (uart) and clocked serial interface (csi), are provided. of these channels, two are used for both uart and csi, and their function must be selected. of the other two channels, one is fixed to uart, and one is fixed to csi. the uart performs data transfer usi ng pins txdn and rxdn (n = 0, 1). the csi performs data transfer using pins son, sin, and sckn (n = 0, 1). (11) a/d converter (adc) two circuits of high-speed, high-resolution 10-bit a/d co nverters with a total of 14 pins (a/d converter 0: 6 pins, a/d converter 1: 8 pins) are available. the adc converts using a successive approximation method. (12) ports as shown in the table below, ports function as general-purpose ports and as control pins. port i/o control functions port 0 6-bit input nmi input timer/counter output stop signal input external interrupt input a/d converter external trigger input timer 3 output stop signal input port 1 3-bit i/o timer/counter i/o external interrupt input port 2 8-bit i/o timer/counter i/o external interrupt input port 3 5-bit i/o serial interface i/o (uart0, uart1/csi1) port 4 3-bit i/o serial interface i/o (csi0) port dh 6-bit i/o external address bus (a16 to a21) port dl 16-bit i/o external address/data bus (ad0 to ad15) port ct 4-bit i/o external bus interface control signal output port cm 2-bit i/o wait insertion signal input internal system clock output
28 user?s manual u15195ej5v0ud chapter 2 pin functions the names and functions of the v850e /ia2 pins are shown below. these pins can be divided by function into port pins and non-port pins. 2.1 list of pin functions (1) port pins (1/2) pin name i/o function alternate function p00 nmi p01 eso0/intp0 p02 eso1/intp1 p03 adtrg0/intp2 p04 adtrg1/intp3 p05 input port 0 6-bit input-only port p00 is the input port that indicates the status of the nmi pin. the level of the nmi pin can be read by reading the p0.p00 bit. when a valid edge is input, the port functions as an nmi input. intp4/to3off p10 tiud10/to10 p11 tcud10/intp100 p12 i/o port 1 3-bit i/o port input or output can be specified in 1-bit units tclr10/intp101 p20 ti2/intp20 p21 to21/intp21 p22 to22/intp22 p23 to23/intp23 p24 to24/intp24 p25 tclr2/intp25 p26 ti3/tclr3/intp30 p27 i/o port 2 8-bit i/o port input or output can be specified in 1-bit units to3/intp31 p30 rxd0 p31 txd0 p32 rxd1/si1 p33 txd1/so1 p34 i/o port 3 5-bit i/o port input or output can be specified in 1-bit units asck1/sck1 p40 si0 p41 so0 p42 i/o port 4 3-bit i/o port input or output can be specified in 1-bit units sck0 pcm0 wait pcm1 i/o port cm 2-bit i/o port input or output can be specified in 1-bit units clkout
chapter 2 pin functions 29 user?s manual u15195ej5v0ud (2/2) pin name i/o function alternate function pct0 lwr pct1 uwr pct4 rd pct6 i/o port ct 4-bit i/o port input or output can be specified in 1-bit units astb pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 i/o port dh 6-bit i/o port input or output can be specified in 1-bit units a21 pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5 pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o port dl 16-bit i/o port input or output can be specified in 1-bit units ad15
chapter 2 pin functions 30 user?s manual u15195ej5v0ud (2) non-port pins (1/3) pin name i/o function alternate function to000 ? to001 ? to002 ? to003 ? to004 ? to005 output timer 00 pulse signal output ? to010 ? to011 ? to012 ? to013 ? to014 ? to015 output timer 01 pulse signal output ? to10 output timer 10 pulse signal output p10/tiud10 to21 p21/intp21 to22 p22/intp22 to23 p23/intp23 to24 output timer 2 pulse signal output p24/intp24 to3 output timer 3 pulse signal output p27/intp31 eso0 p01/intp0 eso1 input timer 00 or 01 output stop signal input p02/intp1 tiud10 input external count clock input to up/down counter (timer 10) p10/to10 tcud10 input count operation switching signal to up/down counter (timer 10) p11/intp100 tclr10 input clear signal input to up/down counter (timer 10) p12/intp101 ti2 p20/intp20 ti3 input timer 2 or 3 external count clock input p26/intp30/tclr3 tclr2 p25/intp25 tclr3 input timer 2 or 3 clear signal input p26/intp30/ti3 intp0 p01/eso0 intp1 p02/eso1 intp2 p03/adtrg0 intp3 p04/adtrg1 intp4 input external maskable interrupt request input p05/to3off intp100 p11/tcud10 intp101 input external maskable interrupt reque st input and timer 10 external capture trigger input p12/tclr10
chapter 2 pin functions 31 user?s manual u15195ej5v0ud (2/3) pin name i/o function alternate function intp20 p20/ti2 intp21 p21/to21 intp22 p22/to22 intp23 p23/to23 intp24 p24/to24 intp25 input external maskable interrupt reque st input and timer 2 external capture trigger input p25/tclr2 intp30 p26/ti3/tclr3 intp31 input external maskable interrupt reque st input and timer 3 external capture trigger input p27/to3 to3off input timer 3 output stop signal input p05/intp4 so0 p41 so1 output serial transmit data output (3-wire) of csi0 and csi1 p33/txd1 si0 p40 si1 input serial receive data input (3-wire) of csi0 and csi1 p32/rxd1 sck0 p42 sck1 i/o serial clock i/o (3-w ire) of csi0 and csi1 p34/asck1 txd0 p31 txd1 output serial transmit data output of uart0 and uart1 p33/so1 rxd0 p30 rxd1 input serial receive data input of uart0 and uart1 p32/si1 asck1 i/o uart1 serial clock i/o p34/sck1 ani00 to ani05 ? ani10 to ani17 input analog input to a/d converter ? adtrg0 p03/intp2 adtrg1 input external trigger input to a/d converter p04/intp3 nmi input non-maskable interrupt request input p00 mode0 ? mode1 input specifies v850e/ia2 operation mode v pp note v pp note ? power application for flash memory write mode1 wait input control signal input to insert wait in bus cycle pcm0 lwr output external data lower byte write strobe signal output pct0 uwr output external data higher by te write strobe signal output pct1 rd output external data bus read strobe signal output pct4 astb output external data bus address strobe signal output pct6 ad0 to ad15 i/o 16-bit address/data bus for external memory pdl0 to pdl15 a16 to a21 output higher 6-bit address bus for external memory pdh0 to pdh5 reset input system reset input ? x1 input ? x2 ? crystal resonator connection pin for system clock oscillation. input to x1 pin when providing clocks from outside. ? note pd70f3114 only
chapter 2 pin functions 32 user?s manual u15195ej5v0ud (3/3) pin name i/o function alternate function clkout output system clock output pcm1 cksel input input specifying clock generator operation mode ? av dd0 , av dd1 ? positive power supply for a/d converter ? av ss0 , av ss1 ? ground potential for a/d converter ? cv ss ? ground potential for oscillator, pll and regulator ? v dd ? 5 v system positive power supply for peripheral interface ? v ss ? 5 v system ground potential for peripheral interface ? rv dd ? positive power supply pin for regula tor (5 v system power supply pin) ? v ss3 ? internal 3.3 v system ground pin ? regout output regulator output pin ? regin input regulator input pin (3.3 v system power supply pin) ?
chapter 2 pin functions 33 user?s manual u15195ej5v0ud 2.2 pin status the following table shows the status of each pin after a reset, in power-saving mode (software stop mode, idle, halt), and during a dma transfer. operating status pin reset (single-chip mode) reset (romless mode) idle mode/ software stop mode halt mode/ during dma transfer a16 to a21 (pdh0 to pdh5) hi-z hi-z hi-z operating ad0 to ad15 (pdl0 to pdl15) hi-z hi-z hi-z operating lwr, uwr (pct0, pct1) hi-z hi-z h operating rd (pct4) hi-z hi-z h operating astb (pct6) hi-z hi-z h operating wait (pcm0) hi-z hi-z ? operating clkout (pcm1) hi-z operating l operating caution when controlling the external bus using an as ic or the like in standby mode, provide a separate controller. remarks hi-z: high impedance h: high-level output l: low-level output ? : no input sampling
chapter 2 pin functions 34 user?s manual u15195ej5v0ud 2.3 description of pin functions (1) p00 to p05 (port 0) ? input p00 to p05 function as a 6-bit input-only port in which all pins are fixed to input. besides functioning as an input port, in control mode, p00 to p05 operate as nmi input, timer/counter output stop signal input, external interrupt request input, a/ d converter (adc) external trigger input, and timer 3 output stop signal input. normally, if port pins also ha ve alternate functions, the mode is selected using a port mode control register. however, there is no such regist er for p00 to p05. theref ore, the input port cannot be switched with the nmi input pin, timer/ counter output stop signal input pin, ex ternal interrupt request input pin, a/d converter (adc) external trigger input pin, and time r 3 output stop signal input pin. read the status of each pin by reading the port. (a) port mode p00 to p05 are input-only. (b) control mode p00 to p05 also serve as the nmi, eso0, eso1, adtrg0, adtrg1, intp 0 to intp4, and to3off pins, but they cannot be switched. (i) nmi (non-maskable inte rrupt request) ? input this is non-maskable interrupt request input. (ii) eso0, eso1 (emergency shut off) ? input these pins input timer 00 and timer 01 output stop signals. (iii) intp0 to intp4 (external interrupt input) ? input these are external interrupt request input pins. (iv) adtrg0, adtrg1 (a/d trigger input) ? input these are a/d converter external trigger input pins. (v) to3off (timer output 3 off) ? input this is a timer output stop signal input pin.
chapter 2 pin functions 35 user?s manual u15195ej5v0ud (2) p10 to p12 (port 1) ? i/o p10 to p12 function as a 3-bit i/o port in whic h input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p10 to p12 operat e as timer/counter i/o and external interrupt request input. port or control mode can be selected as the operation mode for each bit, s pecified by the port 1 mode control register (pmc1). (a) port mode p10 to p12 can be set to input or output in 1- bit units using the port 1 mode register (pm1). (b) control mode p10 to p12 can be set to port or control mode in 1-bit units using pmc1. (i) to10 (timer output) ? output this pin outputs the timer 10 pulse signal. (ii) tiud10 (timer count pulse input) ? input this is an external count clock input pin to the up/down counter (timer 10). (iii) tcud10 (timer cont rol pulse input) ? input this pin inputs count operation switching si gnals to the up/down counter (timer 10). (iv) tclr10 (timer clear) ? input this is a clear signal input pin to the up/down counter (timer 10). (v) intp100, intp101 (external interrupt input) ? input these are external interrupt request input pins and timer 10 external capture trigger input pins.
chapter 2 pin functions 36 user?s manual u15195ej5v0ud (3) p20 to p27 (port 2) ? i/o p20 to p27 function as an 8-bit i/o port in which input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p20 to p27 operat e as timer/counter i/o and external interrupt request input. port or control mode can be selected as the operation mode for each bit, s pecified by the port 2 mode control register (pmc2). (a) port mode p20 to p27 can be set to input or output in 1- bit units using the port 2 mode register (pm2). (b) control mode p20 to p27 can be set to port or control mode in 1-bit units using pmc2. (i) to21 to to24 (timer output) ? output these pins output a timer 2 pulse signal. (ii) to3 (timer output) ? output this pin outputs a timer 3 pulse signal. (iii) ti2, ti3 (timer input) ? input these are timer 2 and timer 3 external count clock input pins. (iv) tclr2, tclr3 (timer clear) ? input these are timer 2 and timer 3 clear signal input pins. (v) intp20 to intp25 (external interrupt input) ? input these are external interrupt request input pins and timer 2 external capture trigger input pins. (vi) intp30, inpt31 (external interrupt input) ? input these are external interrupt request input pins and timer 3 external capture trigger input pins.
chapter 2 pin functions 37 user?s manual u15195ej5v0ud (4) p30 to p34 (port 3) ? i/o p30 to p34 function as a 5-bit i/o port in whic h input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p30 to p34 operate as serial interface (uart0, uart1/csi1) i/o. port or control mode can be selected as the operation mode for each bit, s pecified by the port 3 mode control register (pmc3). the selection of uart/sci1 is specified by the port 3 function control register (pfc3). (a) port mode p30 to p34 can be set to input or output in 1- bit units using the port 3 mode register (pm3). (b) control mode p30 to p34 can be set to port or control mode in 1-bit units using pmc3. (i) txd0, txd1 (transmit data) ? output these pins output serial trans mit data of uart0 and uart1. (ii) rxd0, rxd1 (receive data) ? input these pins input serial receive data of uart0 and uart1. (iii) asck1 (asynchronous serial clock) ? i/o this is uart1 serial clock i/o pin. (iv) so1 (serial output) ? output this pin outputs serial transmit data of csi1. (v) si1 (serial input) ? input this pin inputs serial receive data of csi1. (vi) sck1 (serial clock) ? i/o this pin is csi1 serial clock i/o pin.
chapter 2 pin functions 38 user?s manual u15195ej5v0ud (5) p40 to p42 (port 4) ? i/o p40 to p42 function as a 3-bit i/o port in whic h input or output can be set in 1-bit units. besides functioning as an i/o port, in control mode, p 40 to p42 operate as serial interface (csi0) i/o. port or control mode can be selected as the operation mode for each bit, s pecified by the port 4 mode control register (pmc4). (a) port mode p40 to p42 can be set to input or output in 1- bit units using the port 4 mode register (pm4). (b) control mode p40 to p42 can be set to port or control mode in 1-bit units using pmc4. (i) so0 (serial output) ? output this pin outputs csi0 serial transmit data. (ii) si0 (serial input) ? input this pin inputs csi0 serial receive data. (iii) sck0 (serial clock) ? i/o this is csi0 serial clock i/o pin. (6) pcm0, pcm1 (port cm) ? i/o pcm0 and pcm1 function as a 2-bit i/o port in whic h input or output can be set in 1-bit units. besides functioning as a port, in control mode, pcm0 an d pcm1 operate as wait insertion signal input and internal system clock output. port or control mode can be select ed as the operati on mode for each bit, specified by the port cm mode control register (pmccm). (a) port mode pcm0 and pcm1 can be set to input or output in 1-bit units using the port cm mode register (pmcm). (b) control mode pcm0 and pcm1 can be set to port or control mode in 1-bit units using pmccm. (i) wait (wait) ? input this control signal input pin, which inserts a data wait in a bus cycle, can be input asynchronously to the clkout signal. sampling is pe rformed at the falling edge of t he clkout signal in the t2 or tw state of the bus cycle. if t he setup or hold time is not secu red within the sampling timing, wait insertion may not be performed. (ii) clkout (clock output) ? output this is an internal system clock output pin. in single-chip mode, output is not performed by the clkout pin because it is in port mode. to per form clkout output, set this pin to control mode using the port cm mode control register (pmccm). this pin performs clkout output, even during the reset period, in romless mode.
chapter 2 pin functions 39 user?s manual u15195ej5v0ud (7) pct0, pct1, pct4, pct6 (port ct) ? i/o pct0, pct1, pct4, and pct6 function as a 4-bit i/o port in which input or output can be set in 1-bit units. besides functioning as a port, in control mode, thes e pins operate as control signal output for when memory is expanded externally. port or control mode can be select ed as the operation mode for each bi t, specified by the port ct mode control register (pmcct). (a) port mode pct0, pct1, pct4, and pct6 can be set to input or output in 1-bit units using the port ct mode register (pmct). (b) control mode pct0, pct1, pct4, and pct6 can be set to port or control mode in 1-bit units using pmcct. (i) lwr (lower byte write strobe) ? output this is a strobe signal that shows that the bus cycl e being executed is a write cycle for sram, external rom, or an exte rnal peripheral i/o area. in the data bus, the lower byte is valid. if the bus cycl e is a lower memory write, it becomes active at the falling edge of the clkout signal in the t1 st ate and becomes inactive at the falling edge of the clkout signal in the t2 state. (ii) uwr (higher byte write strobe) ? output this is a strobe signal that shows that the bus cycl e being executed is a write cycle for sram, external rom, or an exte rnal peripheral i/o area. in the data bus, the higher byte is valid. if the bus cycle is a higher memory write, it becomes active at the falling edge of the clkout signal in the t1 state and becomes inactive at the falling edge of the clkout signal in the t2 state. (iii) rd (read strobe) ? output this is a strobe signal that shows that the bus cycl e being executed is a read cycle for sram, external rom, or external peripheral i/o. it is inactive in the idle state (ti). (iv) astb (address strobe) ? output this is the external address bus latch strobe signal output pin. output becomes low level in synchronization with the falling edge of the clock in the t1 state of the bus cycle, and high level in synchr onization with the fall ing edge of the clock in the t3 state.
chapter 2 pin functions 40 user?s manual u15195ej5v0ud (8) pdh0 to pdh5 (port dh) ? i/o pdh0 to pdh5 function as a 6-bit i/o port in wh ich input or output can be set in 1-bit units. besides functioning as a port, in control mode (external expansion mode), these pins operate as the address bus (a16 to a21) for when memory is expanded externally. port or control mode can be select ed as the operation mode for each bit, specified by the port dh mode control register (pmcdh). (a) port mode pdh0 to pdh5 can be set to input or output in 1-bit units using the port dh mode register (pmdh). (b) control mode pdh0 to pdh5 can be specified as a16 to a21 using pmcdh. (i) a16 to a21 (address) ? output these pins output the higher 6-bit address of t he 22-bit address in the address bus on an external access. (9) pdl0 to pdl15 (port dl) ? i/o pdl0 to pdl15 function as a 16-bit i/o port in wh ich input or output can be set in 1-bit units. besides functioning as a port, in control mode (e xternal expansion mode), these pins operate as the address/data bus (ad0 to ad15) for when memory is expanded externally. port or control mode can be selected as the operat ion mode for each bit, specified by the port dl mode control register (pmcdl). (a) port mode pdl0 to pdl15 can be set to input or output in 1-bi t units using the port dl mode register (pmdl). (b) control mode pdl0 to pdl15 can be specified as ad0 to ad15 using pmcdl. (i) ad0 to ad15 (address/data bus) ? i/o this is a multiplexed bus for addresses or data on an external access. when used for addresses (t1 state) these pins output a0 to a15 of the 22-bit address, and when used for data (t2, tw, t3) they are 16-bit data i/o bus pins. (10) to000 to to005 (timer output) ? output these pins output the pulse signal of timer 00. (11) to010 to to015 (timer output) ? output these pins output the pulse signal of timer 01. (12) ani00 to ani05, ani10 to ani17 (analog input) ? input these pins input analog signals to the a/d converter. (13) cksel (clock generator op erating mode select) ? input this is the input pin that specifies the operation mode of the clock generato r. fix this pin so that the input level does not change during operation.
chapter 2 pin functions 41 user?s manual u15195ej5v0ud (14) mode0, mode1 (mode) ? input these are the input pins that specif y the operation mode. operation mo des are broadly divided into normal operation modes and flash memory programming mode. the normal operation modes are single-chip mode and romless mode (see 3.3 operation modes for details). the operation mode is determined by sampling the status of each of the mode0 and mode1 pins on a reset. fix these pins so that the input le vel does not change during operation. (a) pd703114 mode1 mode0 operation mode l l romless mode l h normal operation mode single-chip mode other than above setting prohibited (b) pd70f3114 mode1/v pp mode0 operation mode l l romless mode l h normal operation mode single-chip mode 7.8 v h flash memory programming mode other than above setting prohibited remark l: low-level input h: high-level input (15) reset (reset) ? input reset input is asynchronous input. when a signal having a certain low level width is input in asynchronous with the operation clock, a system reset that takes precedence over all operations occurs. besides a normal initialize or start, this signal is also used to release a standby mode (halt, idle, software stop). (16) x1, x2 (crystal) these pins connect a resonato r for system clock generation. they can also input external clocks. in this case, connect the external clock to the x1 pin and leave the x2 pin open. (17) cv ss (ground for clock generator) this is the ground pin for the resonator, pll and regulator. (18) v dd (power supply) this is the 5 v system positive power s upply pin for the peripheral interface. (19) v ss (ground) this is the 5 v system ground pi n for the peripheral interface.
chapter 2 pin functions 42 user?s manual u15195ej5v0ud (20) rv dd (regulator power supply) this is the positive power supply pin for the regulator. supply 5 v system power to this pin. (21) v ss3 (ground) this is the internal 3.3 v system ground pin. (22) regout (regulator output) ? output this is the regulator output pin. (23) regin (regulator input) ? input this is the regulator input pin. supply 3.3 v system power to this pin. (24) av dd0 , av dd1 (analog power supply) these are the analog positive power su pply pins for the a/d converter. (25) av ss0 , av ss1 (analog ground) these are the ground pins for the a/d converter.
chapter 2 pin functions 43 user?s manual u15195ej5v0ud 2.4 types of pin i/o circuits and connection of unused pins connection of a 1 to 10 k ? resistor is recommended when connecting to v dd , v ss , or cv ss via a resistor. (1/2) pin i/o circuit type recommended connection p00/nmi p01/eso0/intp0 p02/eso1/intp1 p03/adtrg0/intp2 p04/adtrg1/intp3 p05/intp4/to3off 2 connect directly to v ss . p10/tiud10/to10 p11/tcud10/intp100 p12/tclr10/intp101 p20/ti2/intp20 p21/to21/intp21 to p24/to24/intp24 p25/tclr2/intp25 p26/ti3/tclr3/intp30 p27/to3/intp31 p30/rxd0 5-ac p31/txd0 5 p32/rxd1/si1 5-ac p33/txd1/so1 5 p34/asck1/sck1 p40/si0 5-ac p41/so0 5 p42/sck0 5-ac pcm0/wait pcm1/clkout pct0/lwr pct1/uwr pct4/rd pct6/astb pdh0/a16 to pdh5/a21 pdl0/ad0 to pdl15/ad15 5 input: independently connect to v dd or v ss via a resistor. output: leave open. ani00 to ani05 connect to av ss0 . ani10 to ani17 7 connect to av ss1 . to000 to to005, to010 to to015 4 leave open.
chapter 2 pin functions 44 user?s manual u15195ej5v0ud (2/2) pin i/o circuit type recommended connection mode0 v pp note /mode1 reset cksel 2 ? x2 ? leave open. av ss0 , av ss1 ? connect to v ss . av dd0 , av dd1 ? connect to v dd . regout ? leave open. note pd70f3114 only
chapter 2 pin functions 45 user?s manual u15195ej5v0ud 2.5 pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 4 push-pull output with possible high-impedance output (p-ch, n-ch both off) data output disable p-ch out v dd n-ch type 5 data output disable p-ch in/out v dd n-ch input enable type 5-ac type 7 in comparator + _ v ref (threshold voltage) p-ch n-ch p-ch n-ch v dd in/out data output disable input enable
46 user?s manual u15195ej5v0ud chapter 3 cpu function the cpu of the v850e/ia2 is based on ri sc architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 features minimum instruction execution time: 25 ns (@ internal 40 mhz operation) memory space program space: 64 mb linear data space: 4 gb linear thirty-two 32-bit general-purpose registers internal 32-bit architecture five-stage pipeline control multiplication/division instructions saturated operation instructions one-clock 32-bit shift instruction load/store instructions in long/short format four types of bit manipulation instructions set1 clr1 not1 tst1
chapter 3 cpu function 47 user?s manual u15195ej5v0ud 3.2 cpu register set the registers of the v850e/ia2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. the wid th of all the registers is 32 bits. for details, refer to v850e1 architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (status saving register during nmi) (status saving register during nmi) eipc eipsw (status saving register during interrupt) (status saving register during interrupt) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (status saving register during exception/debug trap) (status saving register during exception/debug trap) ctpc ctpsw (status saving register during callt execution) (status saving register during callt execution)
chapter 3 cpu function 48 user?s manual u15195ej5v0ud 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instruct ions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the as sembler and c compiler. ther efore, before using these registers, their contents mu st be saved so that they are not lost. the contents must be restored to these registers after they have been used. r2 is sometimes used by a real-time os. r2 can be used as a register for variables when it is not being used by the real-time os. table 3-1. program registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register work ing register for generating address r2 address/data variable register (wh en not being used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer for generating address when memory is accessed r31 link pointer used by compiler when calling function pc program counter holds instruction address during program execution remark for detailed descriptions of r1, r3 to r5, and r31, which are used by the assembler and c compiler, refer to ca850 (c compiler package) assembly language user?s manual (u10543e) . (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during execution 0 after reset 00000000h
chapter 3 cpu function 49 user?s manual u15195ej5v0ud 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) note 1 { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { note 2 19 status saving register during exception/debug trap (dbpsw) { note 2 { note 2 20 callt base pointer (ctbp) { { 21 to 31 reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to allow multip le interrupts, it is necessary to save this register by program. 2. access is only possible during the period from w hen the dbtrap instruction is executed to when the dbret instruction is executed. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 with the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, or ctpc, use an even value (bit 0 = 0). remark { : access allowed : access prohibited
chapter 3 cpu function 50 user?s manual u15195ej5v0ud (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), the contents are saved to the nm i status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed wh en a software exception or maskable interrupt occurs is saved to eipc, e xcept for some instructions (refer to 7.8 periods in which cpu does not acknowledge interrupts ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving r egisters, the contents of thes e registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function 51 user?s manual u15195ej5v0ud (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), t he contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. when the reti instruction has been ex ecuted, the values of fepc and fepsw are restored to the pc and psw, respectively. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the interrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code coded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
chapter 3 cpu function 52 user?s manual u15195ej5v0ud (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program st atus (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruction, the new contents become valid immediately following completion of ldsr instruction ex ecution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servic ing is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled (ei) 1: interrupt disabled (di) 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page.
chapter 3 cpu function 53 user?s manual u15195ej5v0ud (2/2) note during saturated operation, the saturated operation results are dete rmined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when t he ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are re served (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function 54 user?s manual u15195ej5v0ud (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, th e contents of the program co unter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. these registers can be read or written only in the period between dbtrap instruction execution and dbret instruction execution. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. when the dbret instruction has been executed, the values of dbpc and dbpsw are restored to the pc and psw, respectively. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify t able addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu function 55 user?s manual u15195ej5v0ud 3.3 operation modes 3.3.1 operation modes the v850e/ia2 has the following operation modes. mode specification is carried out by the mode0 and mode1 pins. (1) normal operation mode (a) single-chip mode access to the internal rom is enabled. in single-chip mode, after the system reset is cleared , each pin related to the bus interface enters the port mode, program execution branches to the reset entr y address of the internal rom, and instruction processing starts. by setting the pmcdh, pmcdl, pm cct, and pmccm registers to control mode by instruction, an external device can be co nnected to the external memory area. (b) romless mode after the system reset is cleared, each pin related to the bus interface enters the control mode, program execution branches to the external device?s (memo ry) reset entry address, and instruction processing starts. fetching of instructions and data access for internal rom becomes impossible. in romless mode, the data bus is a 16-bit data bus. (2) flash memory programming mode ( pd70f3114 only) if this mode is specified, it becomes possible for the fl ash programmer to run a program to the internal flash memory. the initial values of the regist ers differ depending on the mode. operation mode pmcdh pmcdl pmcct pmccm bsc romless mode ffh ffffh 53h 03h 5555h normal operation mode single-chip mode 00h 0000h 00h 00h 5555h
chapter 3 cpu function 56 user?s manual u15195ej5v0ud 3.3.2 operation mode specification the operation mode is specified accordin g to the status of the mode0 and mo de1 pins. in an application system, fix the specification of these pins and do not change them durin g operation. operation is not guaranteed if these pins are changed during operation. (a) pd703114 mode1 mode0 operation mode remark l l romless mode 16-bit data bus l h normal operation mode single-chip mode internal rom area is allocated from address 000000h. other than above setting prohibited (b) pd70f3114 mode1/v pp mode0 operation mode remark l l romless mode 16-bit data bus l h normal operation mode single-chip mode internal rom area is allocated from address 000000h. 7.8 v h flash memory programming mode ? other than above setting prohibited remarks l: low-level input h: high-level input
chapter 3 cpu function 57 user?s manual u15195ej5v0ud 3.4 address space 3.4.1 cpu address space the v850e1 cpu of the v850e/ia2 is of 32-bit architectu re and supports up to 4 gb of linear address space (data space) during operand addressing (data access). also, in in struction address addressing, a maximum of 64 mb of linear address space (program space) is supported. figure 3-1 shows the cpu address space. figure 3-1. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space
chapter 3 cpu function 58 user?s manual u15195ej5v0ud 3.4.2 image 16 images, each containing a 256 mb physical address spac e, are seen in the 4 gb cpu address space. in actuality, the same 256 mb physical a ddress space is accessed regardless of t he values of bits 31 to 28 of the cpu address. figure 3-2 shows the ima ge of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-2. image on address space ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram on-chip peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space
chapter 3 cpu function 59 user?s manual u15195ej5v0ud 3.4.3 wrap-around of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the upper- limit address of the program space, a ddress 03ffffffh, and the lower-limit address 00000000h become contiguous addresses. wrap-around re fers to a situation like this whereby the lower- limit address and upper-limit address become contiguous. caution the 4 kb area of 03fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. no instruction can be fetched from this area beca use this area is defined as on-chip peripheral i/o area. therefore, do not execute any branch a ddress calculation in which the result will reside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction ( ) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the uppe r-limit address of the program space, address ffffffffh, and the lower-limit address 00000000h are contiguous addresses, and the data spac e is wrapped around at the boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction ( ) direction
chapter 3 cpu function 60 user?s manual u15195ej5v0ud 3.4.4 memory map the v850e/ia2 reserves areas as shown in figure 3-3. each mode is specified by the mode0 and mode1 pins. figure 3-3. memory map xfffffffh on-chip peripheral i/o area internal ram area on-chip peripheral i/o area internal ram area access prohibited note internal rom area external memory area of v850e/ia2 single-chip mode romless mode 256 mb 1 mb 1 mb 4 kb xffff000h xfffefffh x0200000h x01fffffh x0100000h x00fffffh x0000000h xfffd800h xfffd7ffh xfffc000h xfffbfffh 6 kb 4 mb x0400000h x03fffffh note by setting the pmcdh, pmcdl, pmcct, and pmccm regi sters to control mode, this area can be used as external memory area.
chapter 3 cpu function 61 user?s manual u15195ej5v0ud 3.4.5 area (1) internal rom/internal flash memory area (a) memory map 1 mb of internal rom/internal flash memory area, addresses 00000h to fffffh, is reserved. actually, internal rom/internal flash memory of 128 kb is mapped to addre sses 000000h to 01ffffh. addresses 020000h to 0fffffh are undefined. figure 3-4. internal rom /internal flash memory area undefined internal rom/ internal flash memory area 0fffffh 020000h 01ffffh 000000h
chapter 3 cpu function 62 user?s manual u15195ej5v0ud (b) interrupt/exception table the v850e/ia2 increases the interrupt response s peed by assigning handler addresses corresponding to interrupts/exceptions. the collection of these handler addresses is called an interrupt/exception table, which is located in the internal rom area. when an interrupt/exception re quest is acknowledged, execution jumps to the handler address, and the program wri tten at that memory location is executed. table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. remark when in romless mode, in order to resume co rrect operation after reset, provide a handler address to the reset routine at address 0 of the external memory. table 3-3. interrupt/exception table start address of interrupt/exception table interrupt/exception source start address of interrupt/exception table interrupt/exception source 00000000h reset 00000230h intp24/intcc24 00000010h nmi0 00000240h intp25/intcc25 00000040h trap0n (n = 0 to f) 00000250h inttm3 00000050h trap1n (n = 0 to f) 00000260h intp30/intcc30 00000060h ilgop/dbg0 00000270h intp31/intcc31 00000080h intp0 00000280h intcm4 00000090h intp1 00000290h intdma0 000000a0h intp2 000002a0h intdma1 000000b0h intp3 000002b0h intdma2 000000c0h intp4 000002c0h intdma3 000000f0h intdet0 00000310h intcsi0 00000100h intdet1 00000320h intcsi1 00000110h inttm00 00000330h intsr0 00000120h intcm003 00000340h intst0 00000130h inttm01 00000350h intser0 00000140h intcm013 00000360h intsr1 00000150h intp100/intcc100 00000370h intst1 00000160h intp101/intcc101 000003a0h intad0 00000170h intcm100 000003b0h intad1 00000180h intcm101 000003f0h intcm010 000001d0h inttm20 00000400h intcm011 000001e0h inttm21 00000410h intcm012 000001f0h intp20/intcc20 00000420h intcm014 00000200h intp21/intcc21 00000430h intcm015 00000210h intp22/intcc22 00000440h intcm004 00000220h intp23/intcc23 00000450h intcm005
chapter 3 cpu function 63 user?s manual u15195ej5v0ud (2) internal ram area 12 kb of memory, addresses fffc000h to fffefffh, are reserved for the internal ram area. the 12 kb area of 3ffc000h to 3ffefffh can be seen as an image of fffc000h to fffefffh. in the v850e/ia2, 6 kb of memory, addresses fffc000h to fffd7ffh, are provided as physical internal ram. access to the area of addresses fffd 800h to fffefffh is prohibited. internal ram area (6 kb) fffefffh fffd800h fffd7ffh fffc000h access prohibited
chapter 3 cpu function 64 user?s manual u15195ej5v0ud (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, ar e provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen in the ar ea between addresse s 3fff000h and 3ffffffh note . note access to the area of addresses 3fff000h to 3 ffffffh is prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h on-chip peripheral i/o area (4 kb) on-chip peripheral i/o registers associ ated with the operation mode specif ication and the state monitoring for the on-chip peripheral i/o are all memory-mapped to the on-chip peripheral i/o area. program fetches cannot be executed from this area. cautions 1. the least significant bit of an address is not decoded. therefore, if byte access is executed in the register at an odd address (2n + 1), the register at the even address (2n) will be accessed because of th e hardware specification. 2. in the v850e/ia2, no registers exist that ar e capable of word access, but if a register is word accessed, halfword access is performed t wice in the order of lower address, then higher address of the word area, ignorin g the lower 2 bits of the address. 3. for registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 4. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. 5. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer. (4) external memory area 4 mb are available for external memory area. ? single-chip mode: x100000h to x3fffffh ? romless mode: x000000h to x3fffffh note that the internal rom, intern al ram, and on-chip peripheral i/o ar eas cannot be accessed as external memory areas.
chapter 3 cpu function 65 user?s manual u15195ej5v0ud 3.4.6 external memory expansion by setting the port n mode control register (pmcn) to control mode, an external device can be connected to the external memory space using each pin of ports dh, dl, ct, and cm. each register is set by selecting control mode for each pin of these ports using pmcn (n = dh, dl, ct, cm). note that the status after reset differs as shown below in accordance with the operating mode specification set by the mode0 and mode1 pins (refer to 3.3 operation modes for details of the operation modes). (a) in the case of romless mode because each pin of ports dh, dl, ct, and cm enters c ontrol mode following a reset, external memory can be used without making changes to the port n mo de control register (pmcn) (the external data bus width is 16 bits). (b) in the case of single-chip mode since the internal rom area is accessed after a re set, each pin of ports dh, dl, ct, and cm enters the port mode, and external devices cannot be used. to use external memory, set the por t n mode control register (pmcn). remark n = dh, dl, ct, cm
chapter 3 cpu function 66 user?s manual u15195ej5v0ud 3.4.7 recommended use of address space the architecture of the v850e/ia2 r equires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. operand data access from instruction can be directly executed at the address in this pointer register 32 kb. however, because there is a limit to which general-purpose registers are used as a pointer register, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-pur pose registers for handling variables is maximized, and the program size can be saved. to enhance the efficiency of using the pointer in con nection with of the memory ma p of the v850e/ia2, the following points are recommended. (1) program space of the 32 bits of the program counter (pc), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. therefore, a contiguous 64 mb space, starting from address 00000000h, corresponds to the memory map of the program space. (2) data space for the efficient use of resources that make use of the wrap-around feature of the da ta space, the continuous 16 mb address spaces 00000000h to 00ffffffh and ff000000h to ffffffffh of the 4 gb cpu are used as the data space. with the v850e/ia2, a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as address sign- extended to 32 bits. example application of wrap-around 00007fffh (r =) 00000000h ffffd800h ffff8000h internal rom area on-chip peripheral i/o area fffff000h ffffefffh ffffbfffh ffffd7ffh ffffc000h internal ram area 32 kb 4 kb 6 kb 16 kb 0001ffffh when r = r0 (zero register) is specified with the ld /st disp16 [r] instruction, an addressing range of 00000000h 32 kb can be referenced by the sign-extended disp 16. by mapping the external memory in the 16 kb area in the figure, all resources of inter nal hardware can be accessed with one pointer. the zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer.
chapter 3 cpu function 67 user?s manual u15195ej5v0ud figure 3-5. recommended memory map ffffffffh fffffa78h fffffa77h fffff000h ffffefffh ffffd800h ffffd7ffh ffffc000h ffffbfffh 03ffd800h 03ffc7ffh 03fff000h 03ffefffh 03ffc000h 03ffbfffh 00100000h 000fffffh 00020000h 0001ffffh 00000000h 03ffffffh 04000000h xfffffffh xffff000h xfffefffh xfffc000h xfffbfffh xfffd800h xfffd7ffh x0100000h x00fffffh x0020000h x001ffffh x0000000h xffffa78h xffffa77h data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory of v850e/ia2 external memory of v850e/ia2 internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom x0400000h x03fffffh 00400000h 003fffffh external memory of v850e/ia2 note access to this area is prohibited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map when the v850e/ia2 is set to single-chip mode, and used in external expansion mode.
chapter 3 cpu function 68 user?s manual u15195ej5v0ud 3.4.8 on-chip peripheral i/o registers (1/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff004h port dl pdl r/w undefined fffff004h port dll pdll r/w undefined fffff005h port dlh pdlh r/w undefined fffff006h port dh pdh r/w undefined fffff00ah port ct pct r/w undefined fffff00ch port cm pcm r/w undefined fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ffh fffff025h port dl mode register h pmdlh r/w ffh fffff026h port dh mode register pmdh r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff044h port dl mode control register pmcdl r/w 0000h/ffffh fffff044h port dl mode control register l pmcdll r/w 00h/ffh fffff045h port dl mode control register h pmcdlh r/w 00h/ffh fffff046h port dh mode control register pmcdh r/w 00h/ffh fffff04ah port ct mode control register pmcct r/w 00h/53h fffff04ch port cm mode control register pmccm r/w 00h/03h fffff060h chip area selection control register 0 csc0 r/w 2c11h fffff062h chip area selection control register 1 csc1 r/w 2c11h fffff066h bus size configuration register bsc r/w 5555h fffff06eh system wait control register vswc r/w 77h fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined
chapter 3 cpu function 69 user?s manual u15195ej5v0ud (2/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h fffff0f0h dma disable status register ddis r 00h fffff0f2h dma restart register drst r/w 00h fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff110h interrupt control register p0ic0 r/w 47h fffff112h interrupt control register p0ic1 r/w 47h fffff114h interrupt control register p0ic2 r/w 47h fffff116h interrupt control register p0ic3 r/w 47h fffff118h interrupt control register p0ic4 r/w 47h fffff11eh interrupt control register detic0 r/w 47h fffff120h interrupt control register detic1 r/w 47h fffff122h interrupt control register tm0ic0 r/w 47h fffff124h interrupt control register cm03ic0 r/w 47h fffff126h interrupt control register tm0ic1 r/w 47h fffff128h interrupt control register cm03ic1 r/w 47h
chapter 3 cpu function 70 user?s manual u15195ej5v0ud (3/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff12ah interrupt control register cc10ic0 r/w 47h fffff12ch interrupt control register cc10ic1 r/w 47h fffff12eh interrupt control register cm10ic0 r/w 47h fffff130h interrupt control register cm10ic1 r/w 47h fffff13ah interrupt control register tm2ic0 r/w 47h fffff13ch interrupt control register tm2ic1 r/w 47h fffff13eh interrupt control register cc2ic0 r/w 47h fffff140h interrupt control register cc2ic1 r/w 47h fffff142h interrupt control register cc2ic2 r/w 47h fffff144h interrupt control register cc2ic3 r/w 47h fffff146h interrupt control register cc2ic4 r/w 47h fffff148h interrupt control register cc2ic5 r/w 47h fffff14ah interrupt control register tm3ic0 r/w 47h fffff14ch interrupt control register cc3ic0 r/w 47h fffff14eh interrupt control register cc3ic1 r/w 47h fffff150h interrupt control register cm4ic0 r/w 47h fffff152h interrupt control register dmaic0 r/w 47h fffff154h interrupt control register dmaic1 r/w 47h fffff156h interrupt control register dmaic2 r/w 47h fffff158h interrupt control register dmaic3 r/w 47h fffff162h interrupt control register csiic0 r/w 47h fffff164h interrupt control register csiic1 r/w 47h fffff166h interrupt control register sric0 r/w 47h fffff168h interrupt control register stic0 r/w 47h fffff16ah interrupt control register seic0 r/w 47h fffff16ch interrupt control register sric1 r/w 47h fffff16eh interrupt control register stic1 r/w 47h fffff174h interrupt control register adic0 r/w 47h fffff176h interrupt control register adic1 r/w 47h fffff17eh interrupt control register cm00ic1 r/w 47h fffff180h interrupt control register cm01ic1 r/w 47h fffff182h interrupt control register cm02ic1 r/w 47h fffff184h interrupt control register cm04ic1 r/w 47h fffff186h interrupt control register cm05ic1 r/w 47h fffff188h interrupt control register cm04ic0 r/w 47h fffff18ah interrupt control register cm05ic0 r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined
chapter 3 cpu function 71 user?s manual u15195ej5v0ud (4/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff1feh power save control register psc r/w 00h fffff200h a/d scan mode register 00 adscm00 r/w 0000h fffff200h a/d scan mode register 00l adscm00l r/w 00h fffff201h a/d scan mode register 00h adscm00h r/w 00h fffff202h a/d scan mode register 01 adscm01 r/w 0000h fffff202h a/d scan mode register 01l adscm01l r 00h fffff203h a/d scan mode register 01h adscm01h r/w 00h fffff204h a/d voltage detection mode register 0 adetm0 r/w 0000h fffff204h a/d voltage detection mode register 0l adetm0l r/w 00h fffff205h a/d voltage detection mode register 0h adetm0h r/w 00h fffff210h a/d conversion result register 00 adcr00 r 0000h fffff212h a/d conversion result register 01 adcr01 r 0000h fffff214h a/d conversion result register 02 adcr02 r 0000h fffff216h a/d conversion result register 03 adcr03 r 0000h fffff218h a/d conversion result register 04 adcr04 r 0000h fffff21ah a/d conversion result register 05 adcr05 r 0000h fffff240h a/d scan mode register 10 adscm10 r/w 0000h fffff240h a/d scan mode register 10l adscm10l r/w 00h fffff241h a/d scan mode register 10h adscm10h r/w 00h fffff242h a/d scan mode register 11 adscm11 r/w 0000h fffff242h a/d scan mode register 11l adscm11l r 00h fffff243h a/d scan mode register 11h adscm11h r/w 00h fffff244h a/d voltage detection mode register 1 adetm1 r/w 0000h fffff244h a/d voltage detection mode register 1l adetm1l r/w 00h fffff245h a/d voltage detection mode register 1h adetm1h r/w 00h fffff250h a/d conversion result register 10 adcr10 r 0000h fffff252h a/d conversion result register 11 adcr11 r 0000h fffff254h a/d conversion result register 12 adcr12 r 0000h fffff256h a/d conversion result register 13 adcr13 r 0000h fffff258h a/d conversion result register 14 adcr14 r 0000h fffff25ah a/d conversion result register 15 adcr15 r 0000h fffff25ch a/d conversion result register 16 adcr16 r 0000h fffff25eh a/d conversion result register 17 adcr17 r 0000h fffff280h a/d internal trigger select register 0 itrg0 r/w 00h fffff288h a/d internal trigger select register 1 itrg1 r/w 00h fffff300h regulator control register regc r/w 00h fffff400h port 0 p0 r undefined fffff402h port 1 p1 r/w undefined
chapter 3 cpu function 72 user?s manual u15195ej5v0ud (5/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff404h port 2 p2 r/w undefined fffff406h port 3 p3 r/w undefined fffff408h port 4 p4 r/w undefined fffff422h port 1 mode register pm1 r/w ffh fffff424h port 2 mode register pm2 r/w ffh fffff426h port 3 mode register pm3 r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff442h port 1 mode control register pmc1 r/w 00h fffff444h port 2 mode control register pmc2 r/w 00h fffff446h port 3 mode control register pmc3 r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff462h port 1 function control register pfc1 r/w 00h fffff464h port 2 function control register pfc2 r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff480h bus cycle type configuration register 0 bct0 r/w cccch fffff482h bus cycle type configuration register 1 bct1 r/w cccch fffff484h data wait control register 0 dwc0 r/w 3333h fffff486h data wait control register 1 dwc1 r/w 3333h fffff488h address wait control register awc r/w 0000h fffff48ah bus cycle control register bcc r/w aaaah fffff540h timer 4 tm4 r 0000h fffff542h compare register 4 cm4 r/w 0000h fffff544h timer control register 4 tmc4 r/w 00h fffff570h dead time timer reload register 0 dtrr0 r/w 0fffh fffff572h buffer register cm00 bfcm00 r/w ffffh fffff574h buffer register cm01 bfcm01 r/w ffffh fffff576h buffer register cm02 bfcm02 r/w ffffh fffff578h buffer register cm03 bfcm03 r/w ffffh fffff57ah timer control register 00 tmc00 r/w 0508h fffff57ah timer control register 00l tmc00l r/w 08h fffff57bh timer control register 00h tmc00h r/w 05h fffff57ch timer unit control register 00 tuc00 r/w 01h fffff57dh timer output mode register 0 tomr0 r/w 00h fffff57eh pwm software timing output register 0 psto0 r/w 00h fffff57fh pwm output enable register 0 poer0 r/w 00h fffff580h tomr write enable register 0 spec0 r/w 0000h fffff59ch buffer register cm04 bfcm04 r/w ffffh
chapter 3 cpu function 73 user?s manual u15195ej5v0ud (6/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff59eh buffer register cm05 bfcm05 r/w ffffh fffff5b0h dead time timer reload register 1 dtrr1 r/w 0fffh fffff5b2h buffer register cm10 bfcm10 r/w ffffh fffff5b4h buffer register cm11 bfcm11 r/w ffffh fffff5b6h buffer register cm12 bfcm12 r/w ffffh fffff5b8h buffer register cm13 bfcm13 r/w ffffh fffff5bah timer control register 01 tmc01 r/w 0508h fffff5bah timer control register 01l tmc01l r/w 08h fffff5bbh timer control register 01h tmc01h r/w 05h fffff5bch timer unit control register 01 tuc01 r/w 01h fffff5bdh timer output mode register 1 tomr1 r/w 00h fffff5beh pwm software timing output register 1 psto1 r/w 00h fffff5bfh pwm output enable register 1 poer1 r/w 00h fffff5c0h tomr write enable register 1 spec1 r/w 0000h fffff5d0h timer 0 clock sele ct register prm01 r/w 00h fffff5d8h timer 1/timer 2 clock selection register prm02 r/w 00h fffff5dch buffer register cm14 bfcm14 r/w ffffh fffff5deh buffer register cm15 bfcm15 r/w ffffh fffff5e0h timer 10 tm10 r/w 0000h fffff5e2h compare register 100 cm100 r/w 0000h fffff5e4h compare register 101 cm101 r/w 0000h fffff5e6h capture/compare register 100 cc100 r/w 0000h fffff5e8h capture/compare register 101 cc101 r/w 0000h fffff5eah capture/compare control register 0 ccr0 r/w 00h fffff5ebh timer unit mode register 0 tum0 r/w 00h fffff5ech timer control register 10 tmc10 r/w 00h fffff5edh signal edge selection register 10 sesa10 r/w 00h fffff5eeh prescaler mode register 10 prm10 r/w 07h fffff5efh status register 0 status0 r 00h fffff5f6h cc101 capture input selection register csl10 r/w 00h fffff5f8h timer 10 noise eliminati on time select register nrc10 r/w 00h fffff620h timer connection sele ction register 0 tmic0 r/w 00h fffff630h timer 2 input filter mode register 0 fem0 r/w 00h fffff631h timer 2 input filter mode register 1 fem1 r/w 00h fffff632h timer 2 input filter mode register 2 fem2 r/w 00h fffff633h timer 2 input filter mode register 3 fem3 r/w 00h fffff634h timer 2 input filter mode register 4 fem4 r/w 00h
chapter 3 cpu function 74 user?s manual u15195ej5v0ud (7/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff635h timer 2 input filter mode register 5 fem5 r/w 00h fffff640h timer 2 clock stop register 0 stopte0 r/w 0000h fffff640h timer 2 clock stop register 0l stopte0l r 00h fffff641h timer 2 clock stop register 0h stopte0h r/w 00h fffff642h timer 2 count clock/control edge selection register 0 cse0 r/w 0000h fffff642h timer 2 c ount clock/control edge selection register 0l cse0l r/w 00h fffff643h timer 2 c ount clock/control edge selection register 0h cse0h r/w 00h fffff644h timer 2 subchannel input event edge selection register 0 sese0 r/w 0000h fffff644h timer 2 subchannel i nput event edge selection register 0l sese0l r/w 00h fffff645h timer 2 subchannel i nput event edge selection register 0h sese0h r/w 00h fffff646h timer 2 time base control register 0 tcre0 r/w 0000h fffff646h timer 2 time base control register 0l tcre0l r/w 00h fffff647h timer 2 time base control register 0h tcre0h r/w 00h fffff648h timer 2 output control register 0 octle0 r/w 0000h fffff648h timer 2 output control register 0l octle0l r/w 00h fffff649h timer 2 output control register 0h octle0h r/w 00h fffff64ah timer 2 subchannel 0, 5 capture/compare control register cmse050 r/w 0000h fffff64ch timer 2 subchannel 1, 2 capture/compare control register cmse120 r/w 0000h fffff64eh timer 2 subchannel 3, 4 capture/compare control register cmse340 r/w 0000h fffff650h timer 2 subchannel 1 sub capture/compare register cvse10 r/w 0000h fffff652h timer 2 subchannel 1 main capture/compare register cvpe10 r 0000h fffff654h timer 2 subchannel 2 sub capture/compare register cvse20 r/w 0000h fffff656h timer 2 subchannel 2 main capture/compare register cvpe20 r 0000h fffff658h timer 2 subchannel 3 sub capture/compare register cvse30 r/w 0000h fffff65ah timer 2 subchannel 3 main capture/compare register cvpe30 r 0000h fffff65ch timer 2 subchannel 4 sub capture/compare register cvse40 r/w 0000h
chapter 3 cpu function 75 user?s manual u15195ej5v0ud (8/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff65eh timer 2 subchannel 4 main capture/compare register cvpe40 r 0000h fffff660h timer 2 subchannel 0 capture/compare register cvse00 r/w 0000h fffff662h timer 2 subchannel 5 capture/compare register cvse50 r/w 0000h fffff664h timer 2 time base status register 0 tbstate0 r/w 0101h fffff664h timer 2 time base status register 0l tbstate0l r/w 01h fffff665h timer 2 time base status register 0h tbstate0h r/w 01h fffff666h timer 2 capture/compare 1 to 4 status register 0 ccstate0 r/w 0000h fffff666h timer 2 capture/compare 1 to 4 status register 0l ccstate0l r/w 00h fffff667h timer 2 capture/compare 1 to 4 status register 0h ccstate0h r/w 00h fffff668h timer 2 output delay register 0 odele0 r/w 0000h fffff668h timer 2 output delay register 0l odele0l r/w 00h fffff669h timer 2 output delay register 0h odele0h r/w 00h fffff66ah timer 2 software event capture register csce0 r/w 0000h fffff680h timer 3 tm3 r 0000h fffff682h capture/compare register 30 cc30 r/w 0000h fffff684h capture/compare register 31 cc31 r/w 0000h fffff686h timer control register 30 tmc30 r/w 00h fffff688h timer control register 31 tmc31 r/w 20h fffff689h valid edge selection register sesc r/w 00h fffff690h timer 3 clock selection register prm03 r/w 00h fffff698h timer 3 noise elimination time selection register nrc3 r/w 00h fffff6a0h timer 3 output control register to3c r/w 00h fffff800h peripheral command register phcmd w undefined fffff802h peripheral status register phs r/w 00h fffff810h dma trigger factor register 0 dtfr0 r/w 00h fffff812h dma trigger factor register 1 dtfr1 r/w 00h fffff814h dma trigger factor register 2 dtfr2 r/w 00h fffff816h dma trigger factor register 3 dtfr3 r/w 00h fffff820h power save mode register psmr r/w 00h fffff822h clock control register ckc r/w 00h fffff824h lock register lockr r 0000000xb fffff880h external interrupt mode register 0 intm0 r/w 00h
chapter 3 cpu function 76 user?s manual u15195ej5v0ud (9/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff882h external interrupt mode register 1 intm1 r/w 00h fffff884h external interrupt mode register 2 intm2 r/w 00h fffff8d4h flash programming mode control register flpmc r/w 08h/0ch/00h note fffff900h clocked serial interf ace mode register 0 csim0 r/w 00h fffff901h clocked serial in terface clock selection register 0 csic0 r/w 00h fffff902h clocked serial interface receive buffer register 0 sirb0 r 0000h fffff902h clocked serial interface receive buffer register l0 sirbl0 r 00h fffff904h clocked serial interface transmit buffer register 0 sotb0 r/w 0000h fffff904h clocked serial interface transmit buffer register l0 sotbl0 r/w 00h fffff906h clocked serial in terface read-only receive buffer register 0 sirbe0 r 0000h fffff906h clocked serial interface read-only receive buffer register l0 sirbel0 r 00h fffff908h clocked serial interface initial transmit buffer register 0 sotbf0 r/w 0000h fffff908h clocked serial interface initial transmit buffer register l0 sotbfl0 r/w 00h fffff90ah serial i/o shift register 0 sio0 r 0000h fffff90ah serial i/o shift register l0 siol0 r 0000h fffff910h clocked serial interf ace mode register 1 csim1 r/w 00h fffff911h clocked serial in terface clock selection register 1 csic1 r/w 00h fffff912h clocked serial interface receive buffer register 1 sirb1 r 0000h fffff912h clocked serial interface receive buffer register l1 sirbl1 r 0000h fffff914h clocked serial interface transmit buffer register 1 sotb1 r/w 0000h fffff914h clocked serial interface transmit buffer register l1 sotbl1 r/w 00h fffff916h clocked serial in terface read-only receive buffer register 1 sirbe1 r 0000h fffff916h clocked serial in terface read-only receive buffer register l1 sirbel1 r 00h fffff918h clocked serial interface initial transmit buffer register 1 sotbf1 r/w 0000h fffff918h clocked serial interface initial transmit buffer register l1 sotbfl1 r/w 00h fffff91ah serial i/o shift register 1 sio1 r 0000h fffff91ah serial i/o shift register l1 siol1 r 00h note pd703114: 00h pd70f3114: 08h or 0ch (for details, refer to 15.7.12 flash programming mode control register (flpmc) .)
chapter 3 cpu function 77 user?s manual u15195ej5v0ud (10/10) bit units for manipulation address function register name symbol r/w 1 bit 8 bits 16 bits after reset fffff920h prescaler mode register 3 prsm3 r/w 00h fffff922h prescaler compare register 3 prscm3 r/w 00h fffffa00h asynchronous serial interface mode register 0 asim0 r/w 01h fffffa02h receive buffer register 0 rxb0 r ffh fffffa03h asynchronous serial interface status register 0 asis0 r 00h fffffa04h transmit buffer register 0 txb0 r/w ffh fffffa05h asynchronous serial interface transmit status register 0 asif0 r 00h fffffa06h clock select register 0 cksr0 r/w 00h fffffa07h baud rate generator control register 0 brgc0 r/w ffh fffffa20h 2-frame continuous reception buffer register 1 rxb1 r undefined fffffa22h receive buffer register l1 rxbl1 r undefined fffffa24h 2-frame continuous transmission shift register 1 txs1 w undefined fffffa26h transmit shift register l1 txsl1 w undefined fffffa28h asynchronous serial interface mode register 10 asim10 r/w 81h fffffa2ah asynchronous serial interface mode register 11 asim11 r/w 00h fffffa2ch asynchronous serial interface status register 1 asis1 r 00h fffffa2eh prescaler mode register 1 prsm1 r/w 00h fffffa30h prescaler compare register 1 prscm1 r/w 00h
chapter 3 cpu function 78 user?s manual u15195ej5v0ud 3.4.9 specific registers specific registers are registers that are protected from being written with ill egal data due to inadvertent program loop (runaway), etc. the v850e/ia2 has three specific re gisters, the power save control register (psc) (refer to 8.5.2 (3) power save control register (psc) ), clock control register (ckc) (refer to 8.3.4 clock control register (ckc) ), and flash programming mode control register (flpmc) (refer to 15.7.12 flash programming mode control register (flpmc) ). 3.4.10 system wait control register (vswc) the system wait control register (vsw c) controls the wait cycles of a bus access to the on-chip peripheral i/o registers. set the following values to this register. set value of vswc: 02h (when two wait clocks are set, with operating frequency (f xx ) = 40 mhz) this register can be read/written in 8-bit units (address: fffff06eh, after reset: 77h). remark if the timing at which the flag or count value changes overlaps the register access timing when a register that includes a status flag indicating the status of on-chip peripheral f unctions (asif0, etc.) or a register that indicates a timer count value (tm0n, etc.) are accessed, a regist er access retry operation occurs. therefore, it may take longer than normal to access an on-chip peripheral register. 3.4.11 cautions (1) register to be set first when using the v850e/ia2, the following regi sters must be set from the beginning. ? system wait control register (vswc) (see 3.4.10 system wait control register (vswc) ) ? clock control register (ckc) (see 8.3.4 clock control register (ckc) ) after setting vswc and ckc, set other registers as required.
chapter 3 cpu function 79 user?s manual u15195ej5v0ud (2) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mov instruction immediately before the sld instruction and an interrupt requ est conflict before execution of the ld instruction is complete, the execution result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> for assembler when executing the sld instruction immediately after instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instru ction destination register in the above instruction executed immediately bef ore the sld instruction. ? ? ?
80 user?s manual u15195ej5v0ud chapter 4 bus control function the v850e/ia2 is provided with an exte rnal bus interface function by whic h external i/o and memories, such as rom and ram, can be connected. 4.1 features 16-bit/8-bit data bus sizing function wait function programmable wait function: up to 7 wait states can be inserted external wait function via wait pin idle state insertion function external device connection enabled via bus control/port alternate function pins 4.2 bus control pins the following pins are used for connection to external devices. bus control pin (function when in control mode) func tion when in port mode register for port/control mode switching address/data bus (ad0 to ad15) pdl0 to pdl15 (port dl) pmcdl address bus (a16 to a21) pdh0 to pdh5 (port dh) pmcdh read/write control (lwr/uwr, rd, astb) pct0, pct1, pct4, pct6 (port ct) pmcct external wait control (wait) pcm0 (port cm) internal system clock (clkout) pcm1 (port cm) pmccm remark in the case of romless mode, when the system is reset, each bus control pin becomes valid unconditionally. 4.2.1 pin status during internal rom, in ternal ram, and on-chip peripheral i/o access when the internal rom and ram are accessed, both the address bus and address/data bus become undefined. the external bus control signal becomes inactive. when on-chip peripheral i/o are access ed, both the address bus and address/data bus out put the address of the on-chip peripheral i/o currently being acce ssed. no data is output. the external bus control signal becomes inactive.
chapter 4 bus control function 81 user?s manual u15195ej5v0ud 4.3 memory block function in the v850e/ia1, the 256 mb memory space is divided into memory blo cks of 2 mb and 64 mb units. the programmable wait function and bus cycle operat ion mode can be inde pendently controll ed for each block. the area that can be used as progr am area is the 64 mb space of addresses 0000000h to 3ffffffh. in the v850e/ia2, memory space is t he 4 mb space of addresses 000000h to 3fffffh (n = 1 to 7) because the csn pin has been deleted and the a0 to a21 pins have been specified as address pins. fffffffh fffffffh on-chip peripheral i/o area (4 kb) internal ram area (12 kb note 1 ) external memory area external memory area fffc000h fe00000h fdfffffh ffff000h fffefffh fc00000h fbfffffh fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 1 (2 mb) block 0 (2 mb) block 2 (2 mb) block 3 (2 mb) 64 mb 64 mb block 5 (2 mb) block 6 (2 mb) block 4 (2 mb) block 7 (2 mb) 3ffffffh on-chip peripheral i/o area (4 kb) note 2 internal ram area (12 kb note 1 ) 3ffc000h 3fff000h 3ffefffh 00fffffh internal rom area (1 mb) note 3 0000000h cs7, cs6, cs5 area 3 area 2 area 1 area 0 cs6 cs4 cs1 cs3 cs2, cs1, cs0 note 4 notes 1. internal physical ram: 6 kb 2. access to this area is prohibited. to a ccess the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 3. when in romless mode, this becomes an external memory area. 4. memory space of the v850e/ia2
chapter 4 bus control function 82 user?s manual u15195ej5v0ud 4.3.1 chip select control function of the 256 mb memory area, the lower 8 mb (00000 00h to 07fffffh) and the hi gher 8 mb (f800000h to fffffffh) can be divided into 2 mb memory blocks by chip area selection control regi sters 0 and 1 (csc0, csc1) to control the chip select signal. the memory area can be effectively used by dividing it into memory blocks using the chip select control function. the priority order is described below. (1) chip area selection control registers 0, 1 (csc0, csc1) these registers can be read/written in 16-bit units and become valid by setting each bit to 1. only the cs01 and cs00 bits of the csc0 register are valid in the v850e/ia2. these registers are not affected by other bit settings. in the v850e/ia2, set the cs01 and cs00 bits to 11b so that cs0 is output to both block 0 and 1. if different chip select signal outputs are set to the sa me block, the priority order is controlled as follows. csc0: cs0 > cs2 > cs1 csc1: cs7 > cs5 > cs6 if both the cs0m and cs2m bits of the csc0 register ar e set to 0, cs1 is output to the corresponding block (m = 0 to 3). similarly, if both the cs5m and cs 7m bits of the csc1 register are set to 0, cs6 is output to the corresponding block (m = 0 to 3). caution write to the csc0 and csc1 registers afte r reset, and then do not change the set values.
chapter 4 bus control function 83 user?s manual u15195ej5v0ud 15 cs33 csc0 address fffff060h after reset 2c11h 14 cs32 13 cs31 12 cs30 11 cs23 10 cs22 9 cs21 8 cs20 7 cs13 6 cs12 5 cs11 4 cs10 3 cs03 2 cs02 1 cs01 0 cs00 15 cs43 csc1 address fffff062h after reset 2c11h 14 cs42 13 cs41 12 cs40 11 cs53 10 cs52 9 cs51 8 cs50 7 cs63 6 cs62 5 cs61 4 cs60 3 cs73 2 cs72 1 cs71 0 cs70 bit position bit name function chip select enabled by setting csnm bit to 1. csnm cs operation cs00 cs0 output during block 0 access cs01 cs0 output during block 1 access. cs02 cs0 output during block 2 access. cs03 cs0 output during block 3 access. cs10 to cs13 note 1 cs20 cs2 output during block 0 access. cs21 cs2 output during block 1 access. cs22 cs2 output during block 2 access. cs23 cs2 output during block 3 access. cs30 to cs33 note 2 cs40 to cs43 note 3 cs50 cs5 output during block 7 access. cs51 cs5 output during block 6 access. cs52 cs5 output during block 5 access. cs53 cs5 output during block 4 access. cs60 to cs63 note 4 cs70 cs7 output during block 7 access. cs71 cs7 output during block 6 access. cs72 cs7 output during block 5 access. cs73 cs7 output during block 4 access. 15 to 0 csnm (n = 0 to 7) (m = 0 to 3) notes 1. if both the cs0m and cs2m bits have been set to 0, if area 0 is acce ssed, cs1 will be output regardless of the setting of the cs1m bit. 2. when area 1 is accessed, cs3 will be output regardless of the setting of the cs3m bit. 3. when area 2 is accessed, cs4 will be output regardless of the setting of the cs4m bit. 4. if both the cs5m and cs7m bits have been set to 0, if area 3 is acce ssed, cs6 will be output regardless of the setting of the cs6m bit. caution in the v850e/ia2, set the cs01 and cs00 bits to 11b so that cs0 is output to both block 0 and 1.
chapter 4 bus control function 84 user?s manual u15195ej5v0ud the following diagram shows the cs signal that is enabled for area 0 w hen the csc0 register is set to 0703h. when the csc0 register is set to 0703h, cs0 and cs2 ar e output to block 0 and block 1, but since cs0 has priority over cs2, cs0 is output if the addr esses of block 0 and block 1 are accessed. if the address of block 3 is accessed, both the cs03 an d cs23 bits of the csc0 register are 0, and cs1 is output. figure 4-1. example when cs c0 register is set to 0703h 3ffffffh 0600000h 05fffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h block 2 (2 mb) block 3 (2 mb) block 1 (2 mb) block 0 (2 mb) cs1 is output. cs2 is output. cs0 is output. 58 mb 2 mb 4 mb
chapter 4 bus control function 85 user?s manual u15195ej5v0ud 4.4 bus cycle type control function in the v850e/ia2, the following external devices c an be connected directly to each memory block. ? sram, external rom, external i/o connected external devices are spec ified by bus cycle type configuration registers 0 and 1 (bct0 and bct1). (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read/written in 16-bit units. only the me0 bit is valid in the v850e/ia2. thes e registers are not affected by other bit settings. caution write to the bct0 and bct1 registers after reset, and then do not ch ange the set values. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bct0 and bct1 registers is complete. however, it is possible to access external memory areas whose initial settings are complete. 15 me3 bct0 csn signal address fffff480h after reset cccch 14 11 00 13 12 11 me2 10 9 00 00 87 me1 6 1 543 me0 2 1 1 00 0 cs3 cs2 cs1 cs0 15 me7 bct1 csn signal address fffff482h after reset cccch 14 1 13 00 00 12 11 me6 10 1 987 me5 6 1 5 00 00 43 me4 2 1 10 cs6 cs5 cs4 cs7 bit position bit name function sets memory controller operation enable for each chip select. men memory controller operation enable 0 operation disabled 1 operation enabled 15, 11, 7, 3 (bct0), 15, 11, 7, 3 (bct1) men (n = 0 to 7)
chapter 4 bus control function 86 user?s manual u15195ej5v0ud 4.5 bus access 4.5.1 number of access clocks the number of basic clocks required to access each resource is shown below. bus cycle status resource (bus width) instruction fetch operand data access internal rom (32 bits) 1 note 1 5 internal ram (32 bits) 1 note 2 1 on-chip peripheral i/o (16 bits) ? 5 note 3 external memory (16 bits) 3 note 3 3 note 3 notes 1. this value is 2 in the case of instruction branch. 2. this value is 2 if there is conflict with data access. 3. min. value remark unit: clock/access
chapter 4 bus control function 87 user?s manual u15195ej5v0ud 4.5.2 bus sizing function the bus sizing function controls the dat a bus width for each cs space. the data bus width is specified by using the bus size configuration register (bsc). (1) bus size configuration register (bsc) this register can be read/written in 16-bit units. only the bs00 bit is valid in the v850e/ia2. this register is not affected by other bit settings. cautions 1. write to the bsc register after reset, and then do not change th e set values. also, do not access an external memory area other than the one for this initialization routine until the initial setting of the bsc register is complete. however, it is possible to access external memory areas who se initial settings are complete. 2. when the data bus width is specified as 8 bits, only the signals shown below become active. lwr: when accessing sram, external rom, or external i/o (write cycle) 15 0 bsc csn signal address fffff066h after reset 5555h 14 bs70 13 0 12 bs60 11 0 10 bs50 9 0 8 bs40 7 0 6 bs30 5 0 4 bs20 3 0 2 bs10 1 0 0 bs00 cs3 cs2 cs1 cs0 cs4 cs5 cs6 cs7 bit position bit name function sets the data bus width of csn space. bsn0 data bus width of csn space 0 8 bits 1 16 bits 14, 12, 10, 8, 6, 4, 2, 0 bsn0 (n = 0 to 7)
chapter 4 bus control function 88 user?s manual u15195ej5v0ud 4.5.3 bus width the v850e/ia2 accesses on-chip peripheral i/o and external memory in 8-bit, 16-bi t, or 32-bit units. the following shows the operation for each type of access. access all data in order starting from the lower side. (1) byte access (8 bits) (a) when the data bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 byte data 15 8 external data bus 2n + 1 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data external data bus 2n address 7 0 7 0 byte data external data bus 2n + 1 address
chapter 4 bus control function 89 user?s manual u15195ej5v0ud (2) halfword access (16 bits) (a) when the bus width is 16 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus 2n address 15 8 2n + 1 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 1 address 7 0 7 0 halfword data 15 8 15 8 external data bus 2n + 2 address (b) when the data bus width is 8 bits (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 1st access 2nd access 1st access 2nd access 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 1 address 2n 7 0 7 0 halfword data 15 8 external data bus address 7 0 7 0 halfword data 15 8 external data bus 2n + 2 address 2n + 1
chapter 4 bus control function 90 user?s manual u15195ej5v0ud (3) word access (32 bits) (a) when the bus width is 16 bits (little endian) (1/2) <1> access to address 4n 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 23 16 31 24
chapter 4 bus control function 91 user?s manual u15195ej5v0ud (a) when the bus width is 16 bits (little endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 7 0 7 0 word data 15 8 external data bus 4n + 2 address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 7 0 7 0 word data 15 8 external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 4 address 15 8 4n + 5 23 16 31 24 7 0 7 0 word data 15 8 external data bus 4n + 6 address 15 8 23 16 31 24
chapter 4 bus control function 92 user?s manual u15195ej5v0ud (b) when the data bus width is 8 bits (little endian) (1/2) <1> access to address 4n 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n 23 16 31 24 7 0 7 0 word data external data bus 4n + 1 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 <2> access to address 4n + 1 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 1 23 16 31 24 7 0 7 0 word data external data bus 4n + 2 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24
chapter 4 bus control function 93 user?s manual u15195ej5v0ud (b) when the data bus width is 8 bits (little endian) (2/2) <3> access to address 4n + 2 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 2 23 16 31 24 7 0 7 0 word data external data bus 4n + 3 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 <4> access to address 4n + 3 1st access 2nd access 3rd access 4th access 7 0 7 0 word data external data bus address 15 8 4n + 3 23 16 31 24 7 0 7 0 word data external data bus 4n + 4 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 5 address 15 8 23 16 31 24 7 0 7 0 word data external data bus 4n + 6 address 15 8 23 16 31 24
chapter 4 bus control function 94 user?s manual u15195ej5v0ud 4.6 wait function 4.6.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to facilitate interfacing with low-speed memory or with i/os , it is possible to insert up to 7 data wait states in the bus cycle activated for each cs space. the number of wait states can be spec ified by program using data wait control registers 0 and 1 (dwc0 and dwc1). just after system reset, all blo cks have 3 data wait states inserted. these registers can be read/written in 16-bit units. only the dw02, dw01, and dw00 bits are valid in the v850e/ia2. these registers are not affected by other bit settings. cautions 1. the internal rom area and intern al ram area are not subject to programmable waits and ordinarily no wait access is carried out. the on-chip pe ripheral i/o area is also not subject to programmable wait states, with wait control performe d by each peripheral function only. 2. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memo ry area other than the one for this initialization routine until the initial se tting of the dwc0 and dwc1 registers is complete. however, it is possible to acc ess external memory areas whose initial settings are complete. 15 dwc0 csn signal address fffff484h after reset 3333h 14131211109876543210 0 dw32 dw31 dw30 0 dw22 dw21 dw20 0 dw12 dw11 dw10 0 dw02 dw01 dw00 0 dw72 dw71 dw70 0 dw62 dw61 dw60 0 dw52 dw51 dw50 0 dw42 dw41 dw40 cs3 cs2 cs1 cs0 cs7 cs6 cs5 cs4 15 dwc1 csn signal address fffff486h after reset 3333h 14131211109876543210 bit position bit name function specifies the number of wait states inserted in the csn space. dwn2 dwn1 dwn0 number of wait states inserted in csn space 0 0 0 not inserted 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 14 to 12, 10 to 8, 6 to 4, 2 to 0 dwn2 to dwn0 (n = 0 to 7)
chapter 4 bus control function 95 user?s manual u15195ej5v0ud (2) address wait cont rol register (awc) in the v850e/ia2, address setup wait and address hold wa it states can be inserted before and after the t1 cycle, respectively. these wait states can be set for eac h cs space via the awc register. this register can be read/written in 16-bit units. only the ahw0 and asw0 bits are valid in the v850e/ia2. this register is not affected by other bit settings. caution write to the awc register after reset , and then do not change the set values. cs4 cs0 awc csn signal 15 ahw7 14 asw7 13 ahw6 12 asw6 11 ahw5 10 asw5 9 ahw4 8 asw4 7 ahw3 6 asw3 5 ahw2 4 asw2 3 ahw1 2 asw1 1 ahw0 0 asw0 address fffff488h after reset 0000h cs7 cs6 cs5 cs3 cs2 cs1 bit position bit name function 15, 13, 11, 9, 7, 5, 3, 1 ahwn (n = 0 to 7) sets the insertion of an address hold wait state in each csn space after the t1 cycle. 0: address hold wait state not inserted 1: address hold wait state inserted 14, 12, 10, 8, 6, 4, 2, 0 aswn (n = 0 to 7) sets the insertion of an address setup wait state in each csn space before the t1 cycle. 0: address setup wait state not inserted 1: address setup wait state inserted
chapter 4 bus control function 96 user?s manual u15195ej5v0ud 4.6.2 external wait function when an extremely slow device, an i/o, or an asynchronou s system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (wait) for synch ronization with the external device. just as with programmable waits, acce ssing internal rom, internal ram, and on-chip peripheral i/o areas cannot be controlled by external waits. the external wait signal can be input asynchronously to clkout and is sampled at the falling edge of the clkout signal in the t2 and tw states of the bus cycle. if the setup/hold ti me is not satisfi ed within the sampling timing, a wait state may or may not be inserted in the next state. 4.6.3 relationship between programm able wait and external wait a wait cycle is inserted as the result of an or operation between the wait cycl es specified by the set value of the programmable wait and t he wait cycles controlled by the wait pin. wait control programmable wait wait by wait pin for example, if the timings of the pr ogrammable wait and the wait pin signal are as illustrated below, three wait states will be inserted in the bus cycle. figure 4-2. example of wait insertion clkout wait pin wait from wait pin programmable wait wait control t2 tw tw tw t3 remark the circles indicate the sampling timing.
chapter 4 bus control function 97 user?s manual u15195ej5v0ud 4.7 idle state insertion function to facilitate interfacing with low-speed memory devices, a set number of idle states (t1) can be inserted into the bus cycle to be activated after the t3 state to secure the data output float delay time (t df ) of the memory when each cs space is read-accessed. the bus cycle following the t3 st ate starts after the in serted idle state(s). idle states are inserted at the following timing. ? after the read cycle for sram, external i/o, or external rom. the idle state insertion setting can be specified using the bus cycle control register (bcc). idle state insertion is automatically programmed for all memory blocks immediately after a system reset. (1) bus cycle control register (bcc) this register can be read/written in 16-bit units. only the bc01 bit is valid in the v850e/ia2. this register is not affected by other bit settings. cautions 1. idle states cannot be inserted in inte rnal rom, internal ram, or on-chip peripheral i/o areas. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area other than th e one for this initialization routine until the initial setting for this regi ster is complete. however, it is possible to access external memory areas whose initia l settings are complete. cs4 cs0 bcc csn signal 15 bc71 14 0 0 00 0000 13 bc61 12 11 bc51 10 9 bc41 87 bc31 65 bc21 43 bc11 2 1 bc01 0 address fffff48ah after reset aaaah cs7 cs6 cs5 cs3 cs2 cs1 bit position bit name function 15, 13, 11, 9, 7, 5, 3, 1 bcn1 (n = 0 to 7) specifies the insertion of idle states after the t3 state in each csn space. 0: idle state not inserted 1: idle state inserted
chapter 4 bus control function 98 user?s manual u15195ej5v0ud 4.8 bus priority order there are three external bus cycles: dma cycle, operand data access, and instruction fetch. in order of priority, dma cycle is the highest, followed by operand data access and instruction fetch, in that order. an instruction fetch may be inserted between a read acce ss and write access during a read modify write access. also, an instruction fetch may be inserted between bus accesses when the cpu bus is locked. table 4-1. bus priority order priority order external bus cycle bus master dma cycle dma controller operand data access cpu high low instruction fetch cpu
chapter 4 bus control function 99 user?s manual u15195ej5v0ud 4.9 boundary operation conditions 4.9.1 program space (1) branching to the on-chip peripheral i/o area or successive fetches from the internal ram area to the on-chip peripheral i/o area are pr ohibited. if the above is performed (branc hing or successive fetch), the data to be fetched is undefined and the o peration is not guaranteed. (2) if a branch instruction exists at the upper limit of the internal ram area, a prefetch operation (invalid fetch) that straddles over the on-chip peripheral i/o area does not occur. 4.9.2 data space the v850e/ia2 is provided with an address misalign function. through this function, regardless of the data format (word data, halfword data, or byte data), data can be allocated to all addresses. however, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) in the case of halfword-length data access when the address?s lsb is 1, the byte-len gth bus cycle will be generated 2 times. (2) in the case of word-length data access (a) when the address?s lsb is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, an d byte-length bus cycle. (b) when the address?s lowest 2 bits are 10, the halfword-length bus cycle will be generated 2 times.
100 user?s manual u15195ej5v0ud chapter 5 memory ac cess control function 5.1 sram, external rom, external i/o interface 5.1.1 features sram is accessed in a minimum of 3 states. a maximum of 7 programmable data wait states can be inserted according to dwc0 and dwc1 register settings. data waits can be controlled by wait pin input. an idle state (1 state) can be inserted afte r a read/write cycle by setting the bcc register. an address hold wait state or address setup wait state can be inserted by setting the awc register.
chapter 5 memory access control function 101 user?s manual u15195ej5v0ud 5.1.2 sram, external rom, external i/o access figure 5-1. sram, external rom, external i/o access timing (1/4) (a) when reading (1 wait inserted) t1 t2 tw t3 address data h clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) wait (input) address remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance.
chapter 5 memory access control function 102 user?s manual u15195ej5v0ud figure 5-1. sram, external rom, external i/o access timing (2/4) (b) when reading (0 waits, address set up waits, address hold wait states inserted) tasw t1 tahw address address t2 t3 data h clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) wait (input) remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance.
chapter 5 memory access control function 103 user?s manual u15195ej5v0ud figure 5-1. sram, external rom, external i/o access timing (3/4) (c) when writing (1 wait inserted) t1 t2 tw t3 address data note h clkout (output) a16 to a21 (output) ad0 to ad15 (i/o) astb (output) rd (output) uwr, lwr (output) wait (input) address note ad0 to ad7 output invalid data when odd-numbered address byte data is accessed. ad8 to ad15 output invalid data when even-numbered address byte data is accessed. remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance.
chapter 5 memory access control function 104 user?s manual u15195ej5v0ud figure 5-1. sram, external rom, external i/o access timing (4/4) (d) when writing (0 waits inserted, for 8-bit data bus) t1 t2 t3 address address address h clkout (output) a16 to a21 (output) ad8 to ad15 (i/o) ad0 to ad7 (i/o) astb (output) rd (output) uwr, lwr (output) wait (input) data note note ad0 to ad7 output invalid data when odd-numbered address byte data is accessed. remarks 1. the circles indicate the sampling timing. 2. broken lines indicate high impedance.
105 user?s manual u15195ej5v0ud chapter 6 dma functions (dma controller) the v850e/ia2 includes a direct memory access (dma) c ontroller (dmac) that ex ecutes and controls dma transfer. the dmac controls data tr ansfer between memory and peripheral i/o, between memories or between peripheral i/os, based on dma requests issued by the on-chip peripheral i/o (serial interface, timer/ counter, and a/d converter), or software triggers (memory refers to internal ram or external memory). 6.1 features four independent dma channels transfer unit: 8/16 bits maximum transfer count: 65,536 (2 16 ) two-cycle transfer three transfer modes single transfer mode single-step transfer mode block transfer mode transfer requests request by interrupts from on-c hip peripheral i/o (serial interfac e, timer/counter, a/d converter) requests by software trigger transfer targets memory ? peripheral i/o memory ? memory peripheral i/o ? peripheral i/o next address setting function
chapter 6 dma functions (dma controller) 106 user?s manual u15195ej5v0ud 6.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850e/ia2 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma destination address register (ddanh/ddanl) dma addressing control register (dadcn) dma disable status register (ddis) dma trigger factor register (dtfrn) dma restart register (drst) remark n = 0 to 3
chapter 6 dma functions (dma controller) 107 user?s manual u15195ej5v0ud 6.3 control registers 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) these registers are used to set the dma source addresses (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, dsanh and dsanl. since these registers are configured as 2-stage fifo buffe r registers, a new source address for dma transfer can be specified during dma transfer. (refer to 6.8 next address setting function .) in this case, if a new dsan register is set, the value set will be transferred to the sl ave register and enabled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). (1) dma source address registers 0h to 3h (dsa0h to dsa3h) these registers can be read/written in 16-bit units. be sure to set bits 14 to 12 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. when setting an addr ess of an on-chip peripheral i/o regi ster for the source address, be sure to specify an addr ess between ffff000h and fffffffh . an address of the on- chip peripheral i/o register image (3fff 000h to 3ffffffh) must not be specified. 2. do not set the dsanh regi ster while dma is suspended. 15 ir dsa0h address fffff082h after reset undefined 14 0 13 0 12 0 11 sa27 10 sa26 9 sa25 8 sa24 7 sa23 6 sa22 5 sa21 4 sa20 3 sa19 2 sa18 1 sa17 0 1514131211109876543210 1514131211109876543210 1514131211109876543210 sa16 ir dsa1h address fffff08ah after reset undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa2h address fffff092h after reset undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir dsa3h address fffff09ah after reset undefined 000 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 bit position bit name function 15 ir specifies the dma source address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 sa27 to sa16 sets the dma source addresses (a27 to a16). during dma transfer, it stores the next dma transfer source address.
chapter 6 dma functions (dma controller) 108 user?s manual u15195ej5v0ud (2) dma source address registers 0l to 3l (dsa0l to dsa3l) these registers can be read/written in 16-bit units. 15 sa15 dsa0l address fffff080h after reset undefined 14 sa14 13 sa13 12 sa12 11 sa11 10 sa10 9 sa9 8 sa8 7 sa7 6 sa6 5 sa5 4 sa4 3 sa3 2 sa2 1 sa1 0 1514131211109876543210 1514131211109876543210 1514131211109876543210 sa0 sa15 dsa1l address fffff088h after reset undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa2l address fffff090h after reset undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 dsa3l address fffff098h after reset undefined sa14 sa13 sa12 sa11 sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 bit position bit name function 15 to 0 sa15 to sa0 sets the dma source address (a15 to a0). during dma transfer, it stores the next dma transfer source address.
chapter 6 dma functions (dma controller) 109 user?s manual u15195ej5v0ud 6.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) these registers are used to set the dma destination address (28 bits each) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are configured as 2-stage fifo buffer registers, a ne w destination address for dma transfer can be specified during dma transfer. (refer to 6.8 next address setting function .) in this case, if a new ddan register is set, the value set will be transferred to the sl ave register and enabled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). (1) dma destination address register s 0h to 3h (dda0h to dda3h) these registers can be read/written in 16-bit units. be sure to set bits 14 to 12 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. when setting an address of an on- chip peripheral i/o regist er for the destination address, be sure to specify an addres s between ffff000h and fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. 2. do not set the ddanh regist er while dma is suspended. 15 ir dda0h address fffff086h after reset undefined 14 0 13 0 12 0 11 da27 10 da26 9 da25 8 da24 7 da23 6 da22 5 da21 4 da20 3 da19 2 da18 1 da17 0 1514131211109876543210 1514131211109876543210 1514131211109876543210 da16 ir dda1h address fffff08eh after reset undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda2h address fffff096h after reset undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 ir dda3h address fffff09eh after reset undefined 000 da27 da26 da25 da24 da23 da22 da21 da20 da19 da18 da17 da16 bit position bit name function 15 ir specifies the dma destination address. 0: external memory, on-chip peripheral i/o 1: internal ram 11 to 0 da27 to da16 sets the dma destination addresses (a27 to a16). during dma transfer, it stores the next dma transfer destination address.
chapter 6 dma functions (dma controller) 110 user?s manual u15195ej5v0ud (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) these registers can be read/written in 16-bit units. 15 da15 dda0l address fffff084h after reset undefined 14 da14 13 da13 12 da12 11 da11 10 da10 9 da9 8 da8 7 da7 6 da6 5 da5 4 da4 3 da3 2 da2 1 da1 0 1514131211109876543210 1514131211109876543210 1514131211109876543210 da0 da15 dda1l address fffff08ch after reset undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda2l address fffff094h after reset undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 da15 dda3l address fffff09ch after reset undefined da14 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 da0 bit position bit name function 15 to 0 da15 to da0 sets the dma destination address (a15 to a0). during dma transfer, it stores the next dma transfer destination address.
chapter 6 dma functions (dma controller) 111 user?s manual u15195ej5v0ud 6.3.3 dma transfer count regi sters 0 to 3 (dbc0 to dbc3) these 16-bit registers are used to set the byte transfer counts for dma channels n (n = 0 to 3). they store the remaining transfer counts during dma transfer. since these registers are configured as 2-stage fifo buffer registers, a new dma byte transfer count for dma transfer can be specified during dma transfer. (refer to 6.8 next address setting function .) in this case, if a new dbcn register is set, the value set will be transferred to the slave register and enabled only if dma transfer ends normally, and the tcn bit of dma channel control register n (dchcn) has been set to 1 or the initn bit of the dchcn register has been set to 1 (n = 0 to 3). these registers are decremented by 1 per transfer. transfer is terminated if a borrow occurs. these registers can be read/written in 16-bit units. cautions 1. during 2-cycle transfer wh en the transfer source is the inte rnal ram, do not set the transfer count to 2 (the set value of the dbcn register is 0001h). if dma transfer is required t wice, perform dma transfer with th e transfer count set to one (the set value of the dbcn register is 0000h) twice. 2. do not set the dbcn register while dma is suspended. remark if the dbcn register is read after a terminal c ount has occurred during dma transfer without the value of the dbcn register rewritten, the value set i mmediately before dma transfer is read (0000h is not read even after completion of transfer). 15 bc15 dbc0 address fffff0c0h after reset undefined 14 bc14 13 bc13 12 bc12 11 bc11 10 bc10 9 bc9 8 bc8 7 bc7 6 bc6 5 bc5 4 bc4 3 bc3 2 bc2 1 bc1 0 1514131211109876543210 1514131211109876543210 1514131211109876543210 bc0 bc15 dbc1 address fffff0c2h after reset undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc2 address fffff0c4h after reset undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 dbc3 address fffff0c6h after reset undefined bc14 bc13 bc12 bc11 bc10 bc9 bc8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bit position bit name function sets the byte transfer count. it stores t he remaining byte transfer count during dma transfer. dbcn (n = 0 to 3) states 0000h byte transfer count 1 or remaining byte transfer count 0001h byte transfer count 2 or remaining byte transfer count : : ffffh byte transfer count 65,536 (2 16 ) or remaining byte transfer count 15 to 0 bc15 to bc0
chapter 6 dma functions (dma controller) 112 user?s manual u15195ej5v0ud 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) these 16-bit registers are used to control the dma transfer modes for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. they can be read/written in 16-bit units. be sure to set bits 13 to 8, 1, and 0 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. the ds1 and ds0 bits are used to set how many bits of data are transferred. when 8-bit data (ds1, ds0 bits = 00) is set, the lower data bus (ad0 to ad7) is not necessarily used. when the transfer data size is set to 16 bits, the transfer mu st start from an address with bit 1 of the lower address aligned to ?0?. in this case, the transfer cannot start from an odd address. 2. set the dadcn register when the corresponding channel is in one of the following periods (the operation is not guaranteed if set at another timing). ? time from system reset to the ge neration of the first dma transfer ? time from dma transfer e nd (after terminal count) to th e generation of the next dma transfer request ? time from the forcible termination of dma transfer (after the ini tn bit of dma channel control register n (dchcn) has b een set to 1) to the generati on of the next dma transfer request (1/2) 15 ds1 dadc0 address fffff0d0h after reset 0000h 14 ds0 13 0 12 0 11 0 10 0 9 0 8 0 7 sad1 6 sad0 5 dad1 4 dad0 3 tm1 2 tm0 1 0 0 1514131211109876543210 1514131211109876543210 0 ds1 dadc1 address fffff0d2h after reset 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 1514131211109876543210 ds1 dadc2 address fffff0d4h after reset 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 ds1 dadc3 address fffff0d6h after reset 0000h ds0000000 sad1 sad0 dad1 dad0 tm1 tm0 00 bit position bit name function sets the transfer data size for dma transfer. ds1 ds0 transfer data size 0 0 8 bits 0 1 16 bits 1 0 setting prohibited 1 1 setting prohibited 15, 14 ds1, ds0 for the on-chip peripheral i/o registers, ensure the transfer size matches the access size.
chapter 6 dma functions (dma controller) 113 user?s manual u15195ej5v0ud (2/2) bit position bit name function sets the count direction of the source address for dma channel n (n = 0 to 3). sad1 sad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 7, 6 sad1, sad0 sets the count direction of the destinat ion address for dma channel n (n = 0 to 3). dad1 dad0 count direction 0 0 increment 0 1 decrement 1 0 fixed 1 1 setting prohibited 5, 4 dad1, dad0 sets the transfer mode during dma transfer. tm1 tm0 transfer mode 0 0 single transfer mode 0 1 single-step transfer mode 1 0 setting prohibited 1 1 block transfer mode 3, 2 tm1, tm0
chapter 6 dma functions (dma controller) 114 user?s manual u15195ej5v0ud 6.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) these 8-bit registers are used to c ontrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read/written in 8-bit or 1-bit units . (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) be sure to set bits 6 to 4 to 0. if they are set to 1, the operation is not guaranteed. cautions 1. if transfer is complete d with the mlen bit set to 1, and th e next transfer request is executed with the dma transfer (hardware dma) started by an interrupt from the on-chip peripheral i/o, the next transfer will be executed if the tcn bit is set to 1 (will not be automatically cleared to 0). 2. set the mlen bit when the corresponding ch annel is in one of the following periods (the operation is not guaranteed if set at another timing). ? time from system reset to the generati on of the first dma transfer request ? time from dma transfer e nd (after terminal count) to th e generation of the next dma transfer request ? time from the forcible termination of dma transf er (after the initn bit has been set to 1) to the generation of the next dma transfer request 3. if dma transfer is forcibly terminated in the last transfer cycl e with the mlen bit set to 1, the same operations as transfer completion (setting of the tcn bit to 1) are performed (the enn bit will be cleared to 0 in forcible terminati on regardless of the value of the mlen bit). in this case, at the next dm a transfer request, the enn bit mu st be set to 1 and the tcn bit must be read (cleared to 0). 4. during dma transfer completion (terminal coun t), each bit is updated in the order of clearing the enn bit to 0 and setting the tcn bit to 1. fo r this reason, if the tcn bit and enn bit are in the polling mode, the value indicating ?transfer not completed, and transfer prohibited? (tcn bit = 0, and enn bit = 0) may be read in some cases if the dchcn register is read while each of the above bits is being upda ted (this is not an error). 5. do not set the enn and stgn bits while dma is suspended. the opera tion is not guaranteed if set while dma is suspended.
chapter 6 dma functions (dma controller) 115 user?s manual u15195ej5v0ud address fffff0e0h <7> tc0 dchc0 6 0 5 0 4 0 <3> mle0 <2> init0 <1> stg0 <0> e00 after reset 00h address fffff0e2h tc1 dchc1 0 0 0 mle1 init1 stg1 e11 after reset 00h address fffff0e4h tc2 dchc2 0 0 0 mle2 init2 stg2 e22 after reset 00h address fffff0e6h tc3 dchc3 0 0 0 mle3 init3 stg3 e33 after reset 00h <7> 6 5 4 <3> <2> <1> <0> <7> 6 5 4 <3> <2> <1> <0> <7> 6 5 4 <3> <2> <1> <0> bit position bit name function 7 tcn this status bit indicates whether dma transfer through dma channel n has completed or not. this bit is read-only. it is se t to 1 during the last dma transfer and cleared (to 0) when it is read. 0: dma transfer had not completed. 1: dma transfer had completed. 3 mlen when this bit is set to 1 when dma transfer is complete (at terminal count output), the enn bit is not cleared to 0 and the dma tr ansfer enable state is retained. when the next dma transfer start factor is an interrupt from the on-chip peripheral i/o (hardware dma), the dma transfer request can be acknowledged even when the tcn bit is not read. when the next dma transfer start factor is the setting of the stgn bit to 1 (software dma), the dma transfer start factor can be acknowledged by reading and clearing the tcn bit to 0. when this bit is cleared to 0 when dma transfer is complete (at terminal count output), the enn bit is cleared to 0 and the dma transfer di sable state is entered. at the next dma transfer request, the setting of the enn bit to 1 and the reading of the tcn bit are required. 2 initn when this bit is set to 1 during dma trans fer or while dma is suspended, dma transfer is forcibly terminated (refer to 6.12.1 restrictions on forcible termination of dma transfer ). 1 stgn if this bit is set to 1 in the dma tran sfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. 0 enn specifies whether dma transfer through dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer ends. it is also cleared to 0 when dma transfer is forcibly suspended or terminated by means of setting the initn bit to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled caution once the enn bit is set to 1, do not set the bit again until the number of dma transfers set in the dbcn register is complete or dma transfer has been forcibly terminated by setting the initn bit. remark n = 0 to 3
chapter 6 dma functions (dma controller) 116 user?s manual u15195ej5v0ud 6.3.6 dma disable status register (ddis) this register holds the contents of the enn bit of the dchcn register when dma is forcibly suspended (during nmi input) (n = 0 to 3). this register is read-only, in 8-bit units. be sure to set bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f0h 7 0 ddis 6 0 5 0 4 0 3 ch3 2 ch2 1 ch1 0 ch0 after reset 00h bit position bit name function 3 to 0 ch3 to ch0 reflects the value of the enn bit of the dchcn register when dma is forcibly suspended (during nmi input). the contents of this register are held until the next forcible suspension (nmi input) or until the system is reset. 6.3.7 dma restart register (drst) the enn bit of the drst register and the enn bit of the dchcn register are linked to each other, the enn bit can also be used to set the enabling or disabling of dma trans fer independently for four channels, and the drst register can be used to set the enabling or disabling of dma transfer for four channels at the same time (n = 0 to 3). this register can be read/written in 8-bit units. be sure to set bits 7 to 4 to 0. if they are set to 1, the operation is not guaranteed. address fffff0f2h 7 0 drst 6 0 5 0 4 0 3 en3 2 en2 1 en1 0 en0 after reset 00h bit position bit name function 3 to 0 en3 to en0 specifies whether dma transfer vi a dma channel n is to be enabled or disabled. this bit is cleared to 0 when dma transfer is comple ted in accordance with the terminal count output (n = 0 to 3). it is also cleared to 0 when dma transfer is fo rcibly terminated by setting the initn bit of the dchcn register to 1 or by nmi input. 0: dma transfer disabled 1: dma transfer enabled
chapter 6 dma functions (dma controller) 117 user?s manual u15195ej5v0ud 6.3.8 dma trigger factor regi sters 0 to 3 (dtfr0 to dtfr3) these 8-bit registers are used to control the dma transf er start trigger via interrupt requests from on-chip peripheral i/o. the interrupt requests set with these regist ers serve as dma transfer start factors. these registers can be read/written in 8-bit units. only bit 7 (dfn) can be read/written in 1-bit units, and bits 5 to 0 (ifcn5 to ifcn0) can be read/written in 8-bit units. (n = 0 to 3). be sure to set bit 6 to 0. if it is set to 1, the operation is not guaranteed. cautions 1. be sure to stop the dma operation before making changes to dtfrn register settings. 2. except intp0 to inpt4 and intp20 to intp25 (when noise elimination by an analog filter is selected), an interrupt request input in sta ndby mode (idle or soft ware stop mode) does not trigger dma transfer. 3. intcm004 and intcm005 cannot be used as dma trigger sources. 4. if the start factor for dma transfer is change d using the ifcn5 to ifcn0 bits, be sure to clear (0) the dfn bit with the instructi on immediately after the change. (1/3) <7> dtfr0 6543210 df0 0 ifc05 ifc04 ifc03 ifc02 ifc01 ifc00 address fffff810h after reset 00h <7> dtfr1 6543210 df1 0 ifc15 ifc14 ifc13 ifc12 ifc11 ifc10 address fffff812h after reset 00h <7> dtfr2 6543210 df2 0 ifc25 ifc24 ifc23 ifc22 ifc21 ifc20 address fffff814h after reset 00h <7> dtfr3 6543210 df3 0 ifc35 ifc34 ifc33 ifc32 ifc31 ifc30 address fffff816h after reset 00h bit position bit name function 7 dfn this is a dma transfer request flag. only 0 can be written to this bit. 0: no dma transfer request 1: dma transfer request if the interrupt specified as the dma transfer star t factor occurs and it is necessary to clear the dma transfer request while dma transfer is disabled (including when it is aborted by nmi or forcibly stopped by software), stop the operation that has caused the interrupt (e.g., if serial reception is in progress, by di sabling reception) and then clear the dfn bit. if it is clearly known that the interrupt will not occur until the next dma transfer is started, it is not necessary to stop the operation that has caused the interrupt. remark n = 0 to 3
chapter 6 dma functions (dma controller) 118 user?s manual u15195ej5v0ud (2/3) bit position bit name function sets the interrupt source that serves as the dma transfer start factor. ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intp0 0 0 0 0 1 0 intp1 0 0 0 0 1 1 intp2 0 0 0 1 0 0 intp3 0 0 0 1 0 1 intp4 0 0 1 0 0 0 intdet0 0 0 1 0 0 1 intdet1 0 0 1 0 1 0 inttm00 0 0 1 0 1 1 intcm003 0 0 1 1 0 0 inttm01 0 0 1 1 0 1 intcm013 0 0 1 1 1 0 intp100/intcc100 0 0 1 1 1 1 intp101/intcc101 0 1 0 0 0 0 intcm100 0 1 0 0 0 1 intcm101 0 1 0 1 1 0 inttm20 0 1 0 1 1 1 inttm21 0 1 1 0 0 0 intp20/intcc20 0 1 1 0 0 1 intp21/intcc21 0 1 1 0 1 0 intp22/intcc22 0 1 1 0 1 1 intp23/intcc23 0 1 1 1 0 0 intp24/intcc24 0 1 1 1 0 1 intp25/intcc25 0 1 1 1 1 0 inttm3 0 1 1 1 1 1 intp30/intcc30 1 0 0 0 0 0 intp31/intcc31 1 0 0 0 0 1 intcm4 1 0 0 0 1 0 intdma0 1 0 0 0 1 1 intdma1 1 0 0 1 0 0 intdma2 5 to 0 ifcn5 to ifcn0 remark n = 0 to 3
chapter 6 dma functions (dma controller) 119 user?s manual u15195ej5v0ud (3/3) bit position bit name function ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 0 1 0 1 intdma3 1 0 1 0 1 0 intcsi0 1 0 1 0 1 1 intcsi1 1 0 1 1 0 0 intsr0 1 0 1 1 0 1 intst0 1 0 1 1 1 0 intser0 1 0 1 1 1 1 intsr1 1 1 0 0 0 0 intst1 1 1 0 0 1 1 intad0 1 1 0 1 0 0 intad1 1 1 1 0 1 0 intcm010 1 1 1 0 1 1 intcm011 1 1 1 1 0 0 intcm012 1 1 1 1 0 1 intcm014 1 1 1 1 1 0 intcm015 other than above setting prohibited 5 to 0 ifcn5 to ifcn0 remark n = 0 to 3 the relationship between the interrupt source and the dma transfer trigger is as follows (n = 0 to 3). ifcn0 to ifcn5 internal dma request signal interrupt source selector caution an interrupt request will be generated when dma transfer starts . to prevent an interrupt from being generated, mask the interr upt by setting the interrupt request control register. dma transfer starts even if an interrupt is masked.
chapter 6 dma functions (dma controller) 120 user?s manual u15195ej5v0ud 6.4 transfer modes 6.4.1 single transfer mode in single transfer mode, the dmac rel eases the bus at each byte/halfword tr ansfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. however, if a lo wer priority dma transfer request is generated within one clock after the end of a single transfer, even if the previous higher priority dma transfer request signal stays active, this request is not prioritized, and the next dma transfer a fter the bus is released for the cpu is a transfer based on the newly generated, lower priority dma transfer request. figures 6-1 to 6-4 show examples of single transfer. figure 6-1. single transfer example 1 cpu dma3 cpu cpu dma3 cpu cpu cpu cpu cpu dma3 cpu dma3 dma3 cpu cpu cpu dmarq3 (internal signal) cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 6-2 shows a single transfer mode example in which a higher priority dma transfer request is generated. dma channels 0 to 2 are used for a block transfer, and channel 3 is used for a single transfer. figure 6-2. single transfer example 2 dma1 dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dmarq3 cpu dma3 dmarq2 dmarq1 dmarq0 note note note note dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dma channel 1 terminal count (internal signal) (internal signal) (internal signal) (internal signal) note the bus is always released.
chapter 6 dma functions (dma controller) 121 user?s manual u15195ej5v0ud figure 6-3 shows a single transfer mode example in which a lower priority dma transfer request is generated within one clock after the end of a single transfer. dma channels 0 and 3 are used for a single transfer. when two dma transfer request signals are activated at the same time, the two dma transfers are performed alternately. figure 6-3. single transfer example 3 cpu cpu dma3 dma0 cpu dma0 cpu cpu cpu cpu dma0 cpu dma0 dma3 cpu cpu dma0 dmarq3 cpu dma0 dma channel 0 terminal count note note note note dmarq0 dma channel 3 terminal count note note note (internal signal) (internal signal) note the bus is always released. figure 6-4 shows a single transfer mode example in which two or more lower priority dma transfer requests are generated within one clock after the end of a single transfer. dma channels 0, 2, and 3 are used for a single transfer. when three or more dma transfer request signals are activated at the same time, the two highest priority dma transfers are performed alternately. figure 6-4. single transfer example 4 dma2 cpu dma3 cpu cpu dma3 cpu cpu dma2 dma0 cpu dmarq3 dma0 note note note dmarq2 note note dmarq0 dma2 cpu dma channel 0 terminal count note dma3 cpu dma2 cpu cpu dma3 dma channel 3 terminal count note cpu cpu note dma channel 2 terminal count note (internal signal) (internal signal) (internal signal) note the bus is always released.
chapter 6 dma functions (dma controller) 122 user?s manual u15195ej5v0ud 6.4.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. once a dma transfer request signal has been received, transfer continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows examples of single-step transfer. figure 6-6 shows a single-step transfer mode example in which a higher priority dma transfer request is generat ed and dma channels 0 and 1 are set to the single-step transfer mode. figure 6-5. single-step transfer example 1 dma1 cpu cpu cpu cpu cpu cpu cpu cpu dma1 cpu cpu dma1 dma1 cpu dmarq1 cpu cpu dma channel 1 terminal count note note note (internal signal) note the bus is always released. figure 6-6. single-step transfer example 2 dma0 dma0 cpu cpu dma1 cpu cpu cpu cpu dma1 cpu cpu dma1 dma0 cpu dmarq1 dma1 cpu dmarq0 dma channel 0 terminal count dma channel 1 terminal count note note note note note note (internal signal) (internal signal) note the bus is always released.
chapter 6 dma functions (dma controller) 123 user?s manual u15195ej5v0ud 6.4.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma r equests are acknowledged during block transfer. after the block transfer ends and the dmac releases the bus, another dma transfer can be acknowledged. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 2 and 3 are in the block transfer mode. figure 6-7. block transfer example cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma3 dma3 cpu dma2 dma2 dma2 dma2 dma2 dma channel 3 terminal count the bus is always released. dmarq3 (internal signal) dmarq2 (internal signal) 6.5 transfer types 6.5.1 two-cycle transfer in two-cycle transfer, data transfer is performed in two cy cles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and reading is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. caution an idle cycle of 1 to 2 clocks is always inserted between th e read cycle and write cycle.
chapter 6 dma functions (dma controller) 124 user?s manual u15195ej5v0ud 6.6 transfer target 6.6.1 transfer type and transfer target table 6-1 lists the relationship between the transfer type and transfer target ( : transfer enabled, : transfer disabled). table 6-1. relationship between tr ansfer type and transfer target destination internal rom on-chip peripheral i/o note internal ram external memory, external i/o on-chip peripheral i/o note external i/o internal ram external memory source internal rom note if the transfer target is the on-chip peripheral i/o, only the single transfer mode can be used. cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with ? ? in table 6-1. 2. addresses between 3fff000h and 3ffffffh ca nnot be specified for the source and destination address of dma transfer. be sure to specify an address between ffff000h and fffffffh. remark if the target of the dma transfer is an on-chip peripheral i/o register (transfer source/transfer destination), be sure to specify the same transfer size as the register size. for example, in the case of dma transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. <16-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a writ e cycle (8 bits) is generated twice successively. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated. the data is written to the transfer target with the lower bits firs t then higher bits in little endian and the higher bits then the lower bits in big endian. <8-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (the higher 8 bits go into a high-imped ance state) is generated and then a write cycle (8 bits) is generated. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated and then a write cycle (the higher 8 bits go into a high-impedance state) is generated. the data is written to the transfer target with t he lower bits first then higher bits in little endian and the higher bits then the lower bits in big endian.
chapter 6 dma functions (dma controller) 125 user?s manual u15195ej5v0ud 6.6.2 external bus cycles during dma transfer (two-cycle transfer) the external bus cycles during dma transfe r (two-cycle transfe r) are shown below. table 6-2. external bus cycles duri ng dma transfer (two-cycle transfer) transfer target external bus cycle on-chip peripheral i/o, internal ram none ? external memory, external i/o yes sram, ex ternal rom, external i/o access cycle 6.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 in the block transfer mode, the channel used for transfer is never switched. in the single-step transfer mode, if a hi gher priority dma transfer request is issued while the bus is released, the higher priority dma transfer request is acknowledged. caution be sure not to activate mult iple dma channels using the same star t factor. if multiple channels are activated in this way, a lo wer priority dma channel may be acknowledged prior to a higher priority dma channel. 6.8 next address setting function the dma source address registers (dsanh, dsanl), dm a destination address registers (ddanh, ddanl), and dma transfer count register (dbcn) are 2-stage fifo buffe r registers configured with a master register and slave register (n = 0 to 3). when the terminal count is issued, these registers ar e automatically rewritten wit h the value that was set immediately before. if new dma transfer setting is made to these registers duri ng dma transfer, therefore, t he values of the registers are automatically updated to the new value after completion of transfer note . note before making another dma transfer setting, confirm that dma transfer has started. if new settings are made before dma transfer starts, the set values are overwritten to both the ma ster and slave registers, preventing the dma transfer based on the set value immediately before from being correctly performed.
chapter 6 dma functions (dma controller) 126 user?s manual u15195ej5v0ud figure 6-8 shows the configurat ion of the buffer register. figure 6-8. buffer register configuration the actual dma transfer is performed bas ed on the settings of the slave register. the settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made. (1) time from system reset to the genera tion of the first dma transfer request the settings made are incorporated in bot h the master and slave registers. (2) during dma transfer (time from the ge neration to end of dma transfer request) the settings made are incorporated in only the master register, and not in the slave register (the slave register maintains the value set for the next dma transfer). however, the contents of the master register are automatically overwritten in the slave register after dma transfer ends. if the value of each register is read during this per iod, the value of the sl ave register is read. to check that dma transfer has been started, confirm that the first tr ansfer has been executed by reading the dbcn register (n = 0 to 3). (3) time from dma transfer end to the start of the next dma transfer the settings made are incorporated in bot h the master and slave registers. remark ?dma transfer end? means one of the following. ? completion of dma transfer (terminal count) ? forcible termination of dma transfer (the in itn bit of the dchcn register is set to 1) data read data write master register slave register address/ count controller internal bus
chapter 6 dma functions (dma controller) 127 user?s manual u15195ej5v0ud 6.9 dma transfer start factors there are two types of dma transfe r start factors, as shown below. cautions 1. do not use both start factors ((1) and (2)) in combination for th e same channel (if these two start factors are generated at the same time, onl y one of them is valid, but the valid start factor cannot be identified). the operation is not guara nteed if two start factors are used in combination. 2. if dma transfer is started via software and if the software does not correctly detect whether the expected dma transfer opera tion has been completed through manipulation (setting to 1) of the stgn bit of the dchcn register, it cannot be guaranteed whether the next (second) manipulation of the stgn bit corresponds to the st art of ?the next dma transfer expected by software? (n = 0 to 3). for example, suppose single transfer is starte d by manipulating the stgn bit. even if the stgn bit is manipulated next (the second time) without checking by software whether the single transfer has actually b een executed, the next (second) dma transfer is not always executed. this is because the stgn bit may be manipulated th e second time before the first dma transfer is started or completed because , for example, dma transfer with a higher priority had already been started when the stgn bit was manipulated for the first time. it is therefore necessary to manipulate the stgn bit next time (the second time) after checking whether dma transfer started by the fi rst manipulation of th e stgn bit has been completed. completion of dma transfer can be checked by confirming the contents of the dbcn register. (1) request from software if the stgn, enn, and tcn bits of t he dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (2) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0
chapter 6 dma functions (dma controller) 128 user?s manual u15195ej5v0ud 6.10 forcible suspension dma transfer can be forcibly suspended by nmi input during dma transfer. at such a time, the dmac resets the enn bit of the dc hcn register of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be acknowledged after the dma transfer executed during nmi input is terminated (n = 0 to 3). initialize the dma transfer that has been forcibly suspended by setting the initn bit of the dchcn register to 1 to forcibly terminate dma transfer. 6.11 dma transfer end when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3).
chapter 6 dma functions (dma controller) 129 user?s manual u15195ej5v0ud 6.12 forcible termination in addition to the forcible interruption operation by m eans of nmi input, dma transfer can be forcibly terminated by the initn bit of the dchcn register (n = 0 to 3). an example of forcible termination by the initn bit of the dchcn register is illustrated below (n = 0 to 3). figure 6-9. example of forcible termination of dma transfer (a) block transfer via dma channel 3 is st arted during block transfer via dma channel 2 cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu dmarq2 (internal signal) dmarq3 (internal signal) dma channel 3 transfer start dma channel 3 terminal count forcible termination of dma channel 2 transfer, bus released dsa2, dda2, dbc2, dadc2, dchc2 register set dchc2 (init2 bit = 1) register set dsa3, dda3, dbc3, dadc3, dchc3 register set e22 bit = 1 tc2 bit = 0 e22 bit 0 tc2 bit = 0 e33 bit = 1 tc3 bit = 0 e33 bit 0 tc3 bit 1 (b) when transfer is suspended during dma channel 1 block transf er, and transfer under another condition is executed cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (internal signal) forcible termination of dma channel 1 transfer, bus released dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 0 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark the values of the dsan, ddan, and dbcn regi sters (n = 0 to 3) are retained even when dma transfer is forcibly terminated, because these regi sters are fifo-format buffer registers. the next transfer condition can be set to these registers even while dma transfer is in progress. on the other hand, the setting of the dadcn and dchcn re gisters is invalid during dma transfer because these registers are not buffer registers (see 6.8 next address setting function , 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) , and 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ).
chapter 6 dma functions (dma controller) 130 user?s manual u15195ej5v0ud 6.12.1 restrictions on forcible termination of dma transfer during the procedure to forcibly terminate dma transfer using the initn bit of the dchcn register, the transfer may not be terminated and suspended instead even if the init n bit has been set to 1. consequently, when the dma transfer of the channel that should have been forcibly termi nated is resumed, dma transfer may end after completion of an unexpected transfer count, generating a dma tr ansfer end interrupt (intdman) (n = 0 to 3). [preventive measures] the above can be prevented by softwar e using either of the following. (1) temporarily stopping transf ers of all dma channels these restrictions can be prevented if the program configuration is su ch that the tcn bit of the dchcn register is expected to be 1 only during the preven tive processing shown below. (the tcn bit of the dchcn register is cleared to 0 after a read. that is, the tcn bi t is cleared to 0 when preventive processing routine (ii) in step <5> of the preventiv e processing is executed.) <1> disable interrupts (di). <2> read the dma restart register (drst) and transfer t he value in the enn bit of each channel to general- purpose registers (value a). <3> write 00h to the drst register (write twice note ). writing twice ensures that dma transfer is stopped before the processing in step <4>. <4> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. <5> manipulate value a read in step <2> as follows (value b). (i) clear the bit corresponding to the channel to be forcibly terminated to 0. (ii) if both the tcn bit of the dchcn register and the enn bit of the drs t register of the channel that is not to be forcibly terminated are 1 (the anded value is 1), clear the bit corresponding to the channel to 0. <6> write value b manipulated in step <5> to the drst register. <7> enable interrupts (ei). note write three times if the transfer target (transfe r source or destination) is the internal ram. caution step <5> must be performed to prevent th e enn bit of the drst register of the channel for which transfer was succe ssfully complete during steps <2> and <3> from being illegally set to 1. remark n = 0 to 3
chapter 6 dma functions (dma controller) 131 user?s manual u15195ej5v0ud (2) repetitively setting the initn bit of the dchcn re gister until the transfer is forcibly terminated successfully the preventive processing steps are shown below. <1> copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2> set the initn bit of the dchcn register of the channel to be forcibly terminated to 1. <3> read the value of dma transfer count register n (dbcn) of the channel to be forcibly terminated and compare it with the value copied in step <1>. if the values do not match, repeat steps <2> and <3>. cautions 1. when the dbcn register was read in step <3>, if dma stops due to this restriction, the remaining number of the transfer count is read. if the forcible termination is successful, the initial transfer count is read. 2. note that this preventive method takes longer until the forcible termination in applications in which dma tr ansfers of dma channels ot her than those subject to forcible termination are frequently performed. remark n = 0 to 3 6.13 time required for dma transfer the overhead before and after dma transfer and minimum execution clock for dma transfer are shown below. table 6-3. minimum number of execution clocks in dma cycle dma cycle minimum number of execution clocks <1> response time to dma request 4 clocks note 1 internal ram access 2 clocks note 2 <2> memory access on-chip peripheral i/o register access 4 cl ocks + number of waits by vswc register notes 1. if the external interrupt (intpn) is specified as a start factor of dma tr ansfer, the time for noise elimination is added to this value (n = 0 to 4, 100, 101, 20 to 25, 30, 31). 2. two clocks are required for the dma cycle. the following shows the minimum number of executi on clocks in a dma cycle in each transfer mode. single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) block transfer: dma response time (<1>) + (transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>)) number of transfers note one clock is inserted between the r ead and write cycles of any dma transfer.
chapter 6 dma functions (dma controller) 132 user?s manual u15195ej5v0ud 6.14 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma targets (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not supported. if the source or the destination address is set to an odd address, the lsb of the address is forcibly handled as ?0?. (3) bus arbitration for cpu the cpu can access external memory, on-chip per ipheral i/o, and internal ram not undergoing dma transfer. while data transfer between external memories or to and from i/o is bei ng performed, the cpu can access internal ram. while data transfer is being executed between internal rams, the cpu can access external memory and on- chip peripheral i/o. (4) dma start factors do not start two or more dma channels with the same factor. if two or more dma channels are started with the same factor, the dma channel with a lower priori ty may be acknowledged before the dma channel with a higher priority. operation is not guaranteed in this case. (5) program execution and dma transfer with internal ram do not execute dma transfer to/from the internal ram a nd an instruction in the internal ram simultaneously. (6) restrictions related to automatic clearing of tcn bit of dchcn register the tcn bit of the dchcn register is automatically cleared to 0 when it is read. when dma transfer is executed to transfer data to or from the internal ram when two or more dma transfer channels are simultaneously used, the tcn bit may not be cleared even if it is read after completion of dma transfer (n = 0 to 3). caution this restriction does not apply if one of the following conditions is satisfied. ? only one channel of dma transfer is used. ? dma is not executed to transfer da ta to or from the internal ram. [preventive measures] to read the tcn bit of the dchcn regi ster of the dma channel that is us ed to transfer data to or from the internal ram, be sure to read the tcn bit three times in a row. this can accurately clear the tcn bit to 0.
chapter 6 dma functions (dma controller) 133 user?s manual u15195ej5v0ud (7) read values of dsan and ddan registers if the values of the dsan and ddan registers are read during dma transfer, the values in the middle of being updated may be read (n = 0 to 3). for example, if the dsanh register and the dsanl regist er are read in that order when the value of the dma transfer source address (dsa n register) is ?0000ffffh? an d the counting direction is incremental (when the sadn1 and sadn0 bits of the dadcn register = 00), t he value of the dsanl register differs as follows depending on whether dma transfer is executed immedi ately after the dsanh register has been read. (a) if dma transfer does not occur while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> reading dsanl register: dsanl = ffffh (b) if dma transfer occurs while the dsan register is being read <1> reading dsanh register: dsanh = 0000h <2> occurrence of dma transfer <3> incrementing dsan register : dsan = 00010000h <4> reading dsanl register: dsanl = 0000h
134 user?s manual u15195ej5v0ud chapter 7 interrupt/exception processing function the v850e/ia2 is provided with an interr upt controller (intc) that can proc ess a total of 48 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on pr ogram execution. the v850e/ia2 can process interrupt requests from the on-chip peripheral hardware and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). eight levels of software-programmable priorities can be specified for each in terrupt request. interrupt servicing starts after at least 4 system clocks (100 ns (@ 40 mhz)) following the generation of an interrupt request. 7.1 features { interrupts non-maskable interrupts: 1 source caution p00 alternately functions as nmi, and is fixed to input. p00 and nmi cannot be switched. if the p00 bit of the p0 register is read , the level of the p00/nmi pin is read. set the valid edge of the nmi pin using the esn0 bit of the intm0 register (default value: falling edge detection). maskable interrupts: 47 sources 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for each maskable interrupt request. noise elimination note , edge detection, and valid edge specification for external interrupt request signals. note for details of the noise eliminator, refer to 12.4 noise eliminator. { exceptions software exceptions: 32 sources exception traps: 2 sources ( illegal opcode exception and debug trap) interrupt/exception sources ar e listed in table 7-1.
chapter 7 interrupt/exception processing function 135 user?s manual u15195ej5v0ud table 7-1. interrupt/exception source list (1/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc reset interrupt reset ? reset input pin ? 0000h 00000000h undefined non-maskable interrupt nmi0 ? nmi input pin ? 0010h 00000010h nextpc exception trap0n note 1 ? trap instruction ? ? 004nh note 1 00000040h nextpc software exception exception trap1n note 1 ? trap instruction ? ? 005nh note 1 00000050h nextpc exception trap exception ilgop/dbg0 ? illegal opcode/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intp0 p0ic0 intp0 pin pin 0 0080h 00000080h nextpc interrupt intp1 p0ic1 intp1 pin pin 1 0090h 00000090h nextpc interrupt intp2 p0ic2 intp2 pin pin 2 00a0h 000000a0h nextpc interrupt intp3 p0ic3 intp3 pin pin 3 00b0h 000000b0h nextpc interrupt intp4 p0ic4 intp4 pin pin 4 00c0h 000000c0h nextpc interrupt ? ? not used note 2 ? ? ? 000000d0h ? interrupt ? ? not used note 2 ? ? ? 000000e0h ? interrupt intdet0 detic0 ad0 voltage det ection adc0 5 00f0h 000000f0h nextpc interrupt intdet1 detic1 ad1 voltage detection adc1 6 0100h 00000100h nextpc interrupt inttm00 tm0ic0 tm00 underfl ow tm00 7 0110h 00000110h nextpc interrupt intcm003 cm03ic0 cm003 ma tch tm00 8 0120h 00000120h nextpc interrupt inttm01 tm0ic1 tm01 underfl ow tm01 9 0130h 00000130h nextpc interrupt intcm013 cm03ic1 cm013 ma tch tm01 10 0140h 00000140h nextpc interrupt intp100/ intcc100 cc10ic0 intp100 pin/ cc100 match pin/tm10 11 0150h 00000150h nextpc interrupt intp101/ intcc101 cc10ic1 intp101/intp100 pin note 3 / cc101 match pin/tm10 12 0160h 00000160h nextpc interrupt intcm100 cm10ic0 cm100 ma tch tm10 13 0170h 00000170h nextpc interrupt intcm101 cm10ic1 cm101 ma tch tm10 14 0180h 00000180h nextpc interrupt ? ? not used note 2 ? ? ? 00000190h ? interrupt ? ? not used note 2 ? ? ? 000001a0h ? interrupt ? ? not used note 2 ? ? ? 000001b0h ? interrupt ? ? not used note 2 ? ? ? 000001c0h ? interrupt inttm20 tm2ic0 tm20 over flow tm20 15 01d0h 000001d0h nextpc interrupt inttm21 tm2ic1 tm20 over flow tm21 16 01e0h 000001e0h nextpc interrupt intp20/intcc20 cc2i c0 intp20 pin/cc20 match pin/ tm20 17 01f0h 000001f0h nextpc interrupt intp21/intcc 21 cc2ic1 intp21 pin/ cc21 match pin/ tm20/tm21 18 0200h 00000200h nextpc interrupt intp22/intcc 22 cc2ic2 intp22 pin/ cc22 match pin/ tm20/tm21 19 0210h 00000210h nextpc interrupt intp23/intcc 23 cc2ic3 intp23 pin/ cc23 match pin/ tm20/tm21 20 0220h 00000220h nextpc interrupt intp24/intcc 24 cc2ic4 intp24 pin/ cc24 match pin/ tm20/tm21 21 0230h 00000230h nextpc interrupt intp25/intcc 25 cc2ic5 intp25 pin/ cc25 match pin/tm21 22 0240h 00000240h nextpc maskable interrupt inttm3 tm3ic0 tm3 over flow tm3 23 0250h 00000250h nextpc notes 1. n = 0 to fh 2. reserved for expansion to the v850e/ia1. 3. select using the csl10 register.
chapter 7 interrupt/exception processing function 136 user?s manual u15195ej5v0ud table 7-1. interrupt/exception source list (2/2) interrupt/exception source type classification name controlling register generating source generating unit default priority exception code handler address restored pc interrupt intp30/intcc 30 cc3ic0 intp30 pin/ cc30 match pin/tm3 24 0260h 00000260h nextpc interrupt intp31/intcc 31 cc3ic1 intp31 pin/ cc31 match pin/tm3 25 0270h 00000270h nextpc interrupt intcm4 cm4ic0 cm4 match signal tm4 26 0280h 00000280h nextpc interrupt intdma0 dmaic0 end of dma0 transfer dma 27 0290h 00000290h nextpc interrupt intdma1 dmaic1 end of dma1 transfer dma 28 02a0h 000002a0h nextpc interrupt intdma2 dmaic2 end of dma2 transfer dma 29 02b0h 000002b0h nextpc interrupt intdma3 dmaic3 end of dma3 transfer dma 30 02c0h 000002c0h nextpc interrupt ? ? not used note ? ? ? 000002d0h ? interrupt ? ? not used note ? ? ? 000002e0h ? interrupt ? ? not used note ? ? ? 000002f0h ? interrupt ? ? not used note ? ? ? 00000300h ? interrupt intcsi0 csiic0 csi0 transmission complete csi0 31 0310h 00000310h nextpc interrupt intcsi1 csiic1 csi1 reception complete csi1 32 0320h 00000320h nextpc interrupt intsr0 sric0 uart0 reception complete uart0 33 0330h 00000330h nextpc interrupt intst0 stic0 uart0 transmission complete uart0 34 0340h 00000340h nextpc interrupt intser0 seic0 uart0 receiver error uart0 35 0350h 00000350h nextpc interrupt intsr1 sric1 uart1 reception complete uart1 36 0360h 00000360h nextpc interrupt intst1 stic1 uart1 transmission complete uart1 37 0370h 00000370h nextpc interrupt ? ? not used note ? ? ? 00000380h ? interrupt ? ? not used note ? ? ? 00000390h ? interrupt intad0 adic0 e nd of ad0 conversion adc0 38 03a0h 000003a0h nextpc interrupt intad1 adic1 e nd of ad0 conversion adc1 39 03b0h 000003b0h nextpc interrupt ? ? not used note ? ? ? 000003c0h ? interrupt ? ? not used note ? ? ? 000003d0h ? interrupt ? ? not used note ? ? ? 000003e0h ? interrupt intcm010 cm00ic1 cm010 matc h tm01 40 03f0h 000003f0h nextpc interrupt intcm011 cm01ic1 cm011 ma tch tm01 41 0400h 00000400h nextpc interrupt intcm012 cm02ic1 cm012 ma tch tm01 42 0410h 00000410h nextpc interrupt intcm014 cm04ic1 cm014 ma tch tm01 43 0420h 00000420h nextpc interrupt intcm015 cm05ic1 cm015 ma tch tm01 44 0430h 00000430h nextpc interrupt intcm004 cm04ic0 cm004 ma tch tm00 45 0440h 00000440h nextpc maskable interrupt intcm005 cm05ic0 cm005 ma tch tm00 46 0450h 00000450h nextpc note reserved for expansion to the v850e/ia1.
chapter 7 interrupt/exception processing function 137 user?s manual u15195ej5v0ud remarks 1. default priority: the priority order when two or more maskable interrupt requests are generated at the same time. the highest priority is 0. restored pc: the value of t he program counter (pc) saved to eipc, fepc, or dbpc of cpu when interrupt servicing is started. no te, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being exec uted does not become the nextp c. (if an interrupt is acknowledged during instruction executi on, execution stops, and then resumes after the interrupt servicing has finished. in this case, the address of the aborted instruction is the restore pc.) ? load instructions (sld.b, sld. bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
chapter 7 interrupt/exception processing function 138 user?s manual u15195ej5v0ud 7.2 non-maskable interrupt a non-maskable interrupt request is acknowledged unconditi onally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupts. a non-maskable interrupt request is input from the nmi pin. when the valid edge specifi ed by bit 0 (esn0) of the external interrupt mode register 0 (intm0) is detected on the nmi pin, the interrupt occurs. while the service program of the non-maskable interrupt is being execut ed, the acknowledgm ent of another non- maskable interrupt request is held pending. the pending nmi is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the reti instructi on). note that if two or more nmi requests are input during the exec ution of the service program for an nmi, the number of nmis that will be acknowledged after the reti instru ction has been executed is only one.
chapter 7 interrupt/exception processing function 139 user?s manual u15195ej5v0ud 7.2.1 operation if a non-maskable interrupt is generated, the cpu performs the following proce ssing, and transfers control to the handler routine. (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes exception code 0010h to the higher halfword (fecc) of ecr. (4) sets the np and id bits of the psw and clears the ep bit. (5) sets the handler address (00000010h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-mask able interrupt is shown in figure 7-1. figure 7-1. servicing configur ation of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
chapter 7 interrupt/exception processing function 140 user?s manual u15195ej5v0ud figure 7-2. acknowledging non -maskable interrupt request (a) if a new nmi request is generated while an nmi ser vice program is being executed main routine nmi request nmi request (psw.np = 1) nmi request held pending regardless of the value of the np bit of the psw pending nmi request processed (b) if a new nmi request is generated twice while an nmi service program is being executed main routine nmi request nmi request held pending because nmi service program is being processed only one nmi request is acknowledged even though two nmi requests are generated nmi request held pending because nmi service program is being processed
chapter 7 interrupt/exception processing function 141 user?s manual u15195ej5v0ud 7.2.2 restore execution is restored from the non-maskable inte rrupt servicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from fepc and fepsw, res pectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. (2) transfers control back to the address of the restored pc and psw. figure 7-3 illustrates how the reti instruction is processed. figure 7-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit ar e changed by the ldsr instruction during non- maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid lines show the cpu processing flow.
chapter 7 interrupt/exception processing function 142 user?s manual u15195ej5v0ud 7.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that i ndicates that non-maskable interrupt (nmi ) servicing is under execution. this flag is set when an nmi interrupt has been acknowl edged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 7 np indicates whether nmi interrupt servicing is in progress. 0: no nmi interrupt servicing 1: nmi interrupt currently being serviced 7.2.4 edge detection function (1) external interrupt m ode register 0 (intm0) external interrupt mode register 0 (intm0) is a register that spec ifies the valid edge of a non-maskable interrupt (nmi). the nmi valid edge can be specified to be either t he rising edge or the falling edge by the esn0 bit. this register can be read/written in 8-bit or 1-bit units. address fffff880h 7 0 intm0 6 0 5 0 4 0 3 0 2 0 1 0 <0> esn0 after reset 00h bit position bit name function 0 esn0 specifies the nmi pin?s valid edge. 0: falling edge 1: rising edge
chapter 7 interrupt/exception processing function 143 user?s manual u15195ej5v0ud 7.3 maskable interrupts maskable interrupt requests can be masked by interrupt control registers. t he v850e/ia2 has 47 maskable interrupt sources. if two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight le vels of priorities can be spec ified by using the interrupt control registers (programmable priority control). when an interrupt request has been ackno wledged, the acknowledgment of other maskable interrupt requests is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt servici ng routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a hi gher priority than the interrupt request in progress (specified by the interrupt control register). note that only in terrupts with a higher priority will have th is capability; interrupts with the same priority level cannot be nested. however, if multiple interrupts are exec uted, the following processing is necessary. <1> save eipc and eipsw in memory or a general-purpos e register before executi ng the ei instruction. <2> execute the di instruct ion before executing the reti instruction, then reset ei pc and eipsw with the values saved in <1>. 7.3.1 operation if a maskable interrupt occurs by int input, the cpu perfo rms the following processing, and transfers control to a handler routine. (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower halfword of ecr (eicc). (4) sets the id bit of the psw and clears the ep bit. (5) sets the handler address corresponding to each interrupt to the pc, and transfers control. the servicing configurati on of a maskable interrupt is shown in figure 7-4.
chapter 7 interrupt/exception processing function 144 user?s manual u15195ej5v0ud figure 7-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for details of the ispr register, see 7.3.6 in-service priori ty register (ispr) . the int input masked by the interrupt controllers and the int input that o ccurs while another interrupt is being serviced (when psw.np = 1 or psw.id = 1) are held pending internally by the interrupt controller. in such case, if the interrupts are unmasked, or when psw.np = 0 and psw.id = 0 as set by the reti and ldsr instructions, input of the pending int starts the new ma skable interrupt servicing.
chapter 7 interrupt/exception processing function 145 user?s manual u15195ej5v0ud 7.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. (1) restores the values of the pc and the psw from eipc and eipsw bec ause the ep bit of the psw is 0 and the np bit of the psw is 0. (2) transfers control to the address of the restored pc and psw. figure 7-5 illustrates the processi ng of the reti instruction. figure 7-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for details of the ispr register, see 7.3.6 in-service priori ty register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to rest ore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid lines show the cpu processing flow.
chapter 7 interrupt/exception processing function 146 user?s manual u15195ej5v0ud 7.3.3 priorities of maskable interrupts the v850e/ia2 provides multiple interr upt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts c an be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request type (default priority level) befor ehand. for more information, refer to table 7-1 interrupt/exception source list . the programmable priority control cu stomizes interrupt requests into eight levels by setting the priority level specification flag. note that when an interrupt request is a cknowledged, the id flag of psw is automat ically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing t he ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 )
chapter 7 interrupt/exception processing function 147 user?s manual u15195ej5v0ud figure 7-6. example of servicing in which a nother interrupt request is issued while an interrupt is bei ng serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple interrupt servici ng, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt requests.
chapter 7 interrupt/exception processing function 148 user?s manual u15195ej5v0ud figure 7-6. example of servicing in which a nother interrupt request is issued while an interrupt is bei ng serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple in terrupt servicing, restor e the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 7 interrupt/exception processing function 149 user?s manual u15195ej5v0ud figure 7-7. example of servicing interr upt requests generate d simultaneously default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. nmi request caution the values of the eipc and eipsw regi sters must be saved be fore executing multiple interrupts. when returning from multiple inte rrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remark a to c in the figure are pseudo names given to interrupt requests for the sake of explanation.
chapter 7 interrupt/exception processing function 150 user?s manual u15195ej5v0ud 7.3.4 interrupt control register (xxicn) an interrupt control register is assigned to each in terrupt request (maskable inte rrupt) and sets the control conditions for each maskable interrupt request. this register can be read/written in 8-bit or 1-bit units. caution read the xxifn bit of the xxicn register in the interrupt disable d (di) state. otherwise if the timing of interrupt acknowledgmen t and bit reading conflict, no rmal values may not be read. address fffff110h to ffff18ah <7> xxifn xxicn <6> xxmkn 5 0 4 0 3 0 <2> xxprn2 <1> xxprn1 <0> xxprn0 after reset 47h bit position bit name function 7 xxifn this is an interrupt request flag. 0: interrupt request not issued 1: interrupt request issued the flag xxlfn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxmkn this is an interrupt mask flag. 0: enables interrupt servicing 1: disables interr upt servicing (pending) 8 levels of priority order ar e specified for each interrupt. xxprn2 xxprn1 xxprn0 interrupt priority specification bit 0 0 0 specifies level 0 (highest). 0 0 1 specifies level 1. 0 1 0 specifies level 2. 0 1 1 specifies level 3. 1 0 0 specifies level 4. 1 0 1 specifies level 5. 1 1 0 specifies level 6. 1 1 1 specifies level 7 (lowest). 2 to 0 xxprn2 to xxprn0 remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 ). the address and bit of each interrupt control register are as follows.
chapter 7 interrupt/exception processing function 151 user?s manual u15195ej5v0ud table 7-2. addresses and bits of interrupt control registers (1/2) bit address register <7> <6> 5 4 3 <2> <1> <0> fffff110h p0ic0 p0if0 p0mk0 0 0 0 p0pr02 p0pr01 p0pr00 fffff112h p0ic1 p0if1 p0mk1 0 0 0 p0pr12 p0pr11 p0pr10 fffff114h p0ic2 p0if2 p0mk2 0 0 0 p0pr22 p0pr21 p0pr20 fffff116h p0ic3 p0if3 p0mk3 0 0 0 p0pr32 p0pr31 p0pr30 fffff118h p0ic4 p0if4 p0mk4 0 0 0 p0pr42 p0pr41 p0pr40 fffff11ah not used note ? ? ? ? ? ? ? ? fffff11ch not used note ? ? ? ? ? ? ? ? fffff11eh detic0 detif0 detmk0 0 0 0 detpr02 detpr01 detpr00 fffff120h detic1 detif1 detmk1 0 0 0 detpr12 detpr11 detpr10 fffff122h tm0ic0 tm0if0 tm0mk0 0 0 0 tm0pr02 tm0pr01 tm0pr00 fffff124h cm3ic0 cm03if0 cm03mk0 0 0 0 cm03pr02 cm03pr01 cm03prc0 fffff126h tm0ic1 tm0if1 tm0mk1 0 0 0 tm0pr12 tm0pr11 tm0pr10 fffff128h cm03ic1 cm03if1 cm03mk1 0 0 0 cm03pr12 cm03pr11 cm03pr10 fffff12ah cc10ic0 cc10if0 cc10mk0 0 0 0 cc10pr02 cc10pr01 cc10pr00 fffff12ch cc1cic1 cc10if1 cc10mk1 0 0 0 cc10pr12 cc10pr11 cc10pr10 fffff12eh cm10ic0 cm10if0 cm10mk0 0 0 0 cm10pr02 cm10pr01 cm10pr00 fffff130h cm10ic1 cm10if1 cm10mk1 0 0 0 cm10pr12 cm10pr11 cm10pr10 fffff132h not used note ? ? ? ? ? ? ? ? fffff134h not used note ? ? ? ? ? ? ? ? fffff136h not used note ? ? ? ? ? ? ? ? fffff138h not used note ? ? ? ? ? ? ? ? fffff13ah tm2ic0 tm2if0 tm2mk0 0 0 0 tm2pr02 tm2pr01 tm2pr00 fffff13ch tm2ic1 tm2if1 tm2mk1 0 0 0 tm2pr12 tm2pr11 tm2pr10 fffff13eh cc2ic0 cc2if0 cc2mk0 0 0 0 cc2pr02 cc2pr01 cc2pr00 fffff140h cc2ic1 cc2if1 cc2mk1 0 0 0 cc2pr12 cc2pr11 cc2pr10 fffff142h cc2ic2 cc2if2 cc2mk2 0 0 0 cc2pr22 cc2pr21 cc2pr20 fffff144h cc2ic3 cc2if3 cc2mk3 0 0 0 cc2pr32 cc2pr31 cc2pr30 fffff146h cc2ic4 cc2if4 cc2mk4 0 0 0 cc2pr42 cc2pr41 cc2pr40 fffff148h cc2ic5 cc2if5 cc2mk5 0 0 0 cc2pr52 cc2pr51 cc2pr50 fffff14ah tm3ic0 tm3if0 tm3mk0 0 0 0 tm3pr02 tm3pr01 tm3pr00 fffff14ch cc3ic0 cc3if0 cc3mk0 0 0 0 cc3pr02 cc3pr01 cc3pr00 fffff14eh cc3ic1 cc3if1 cc3mk1 0 0 0 cc3pr12 cc3pr11 cc3pr10 note reserved for expansion to v850e/ia1.
chapter 7 interrupt/exception processing function 152 user?s manual u15195ej5v0ud table 7-2. addresses and bits of interrupt control registers (2/2) bit address register <7> <6> 5 4 3 <2> <1> <0> fffff150h cm4ic0 cm4if0 cm4mk0 0 0 0 cm4pr02 cm4pr01 cm4pr00 fffff152h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff154h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff156h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff158h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff15ah not used note ? ? ? ? ? ? ? ? fffff15ch not used note ? ? ? ? ? ? ? ? fffff15eh not used note ? ? ? ? ? ? ? ? fffff160h not used note ? ? ? ? ? ? ? ? fffff162h csiic0 csiif0 csimk0 0 0 0 csipr02 csipr01 csipr00 fffff164h csiic1 csiif1 csimk1 0 0 0 csipr12 csipr11 csipr10 fffff166h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff168h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff16ah seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff16ch sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff16eh stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff170h not used note ? ? ? ? ? ? ? ? fffff172h not used note ? ? ? ? ? ? ? ? fffff174h adic0 adif0 admk0 0 0 0 adpr02 adpr01 adpr00 fffff176h adic1 adif1 admk1 0 0 0 adpr12 adpr11 adpr10 fffff178h not used note ? ? ? ? ? ? ? ? fffff17ah not used note ? ? ? ? ? ? ? ? fffff17ch not used note ? ? ? ? ? ? ? ? fffff17eh cm00ic1 cm00if1 cm00mk1 0 0 0 cm00pr12 cm00pr11 cm00pr10 fffff180h cm01ic1 cm01if1 cm01mk1 0 0 0 cm01pr12 cm01pr11 cm01pr10 fffff182h cm02ic1 cm02if1 cm02mk1 0 0 0 cm02pr12 cm02pr11 cm02pr10 fffff184h cm04ic1 cm04if1 cm04mk1 0 0 0 cm04pr12 cm04pr11 cm04pr10 fffff186h cm05ic1 cm05if1 cm05mk1 0 0 0 cm05pr12 cm05pr11 cm05pr10 fffff188h cm04ic0 cm04if0 cm04mk0 0 0 0 cm04pr02 cm04pr01 cm04pr00 fffff18ah cm05ic0 cm05if0 cm05mk0 0 0 0 cm05pr02 cm05pr01 cm05pr00 note reserved for expansion to v850e/ia1.
chapter 7 interrupt/exception processing function 153 user?s manual u15195ej5v0ud 7.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) these registers set the interrupt ma sk state for the maskable interrupts. the xxmkn bit of the imr0 to imr3 registers is equivalent to the xxmkn bit of the xxicn register. imrm can be read/written in 16-bit units (m = 0 to 3). when the imrm register is divided into two registers: higher 8 bits (imrmh register) and lower 8 bits (imrml register), these registers can be r ead/written in 8-bit or 1-bit units. caution the device file defines the xxmkn bit of th e xxicn register as a reser ved word. if a bit is manipulated with the name xxmkn, th erefore, the xxicn register, rath er than the imrm register, is rewritten (as a result, the imrm register is also rewritten). <15> cm10mk0 <7> detmk0 imr0 <14> cc10mk1 6 1 <13> cc10mk0 5 1 <12> cm03mk1 <4> p0mk4 <11> tm0mk1 <3> p0mk3 <10> cm03mk0 <2> p0mk2 <9> tm0mk0 <1> p0mk1 <8> detmk1 <0> p0mk0 address fffff100h after reset ffffh <15> cc3mk1 <7> cc2mk0 imr1 <14> cc3mk0 <6> tm2mk1 <13> tm3mk0 <5> tm2mk0 <12> cc2mk5 4 1 <11> cc2mk4 3 1 <10> cc2mk3 2 1 <9> cc2mk2 1 1 <8> cc2mk1 <0> cm10mk1 address fffff102h after reset ffffh <15> stmk1 7 1 imr2 <14> srmk1 6 1 <13> semk0 5 1 <12> stmk0 <4> dmamk3 <11> srmk0 <3> dmamk2 <10> csimk1 <2> dmamk1 <9> csimk0 <1> dmamk0 8 1 <0> cm4mk0 address fffff104h after reset ffffh 15 1 <7> cm00mk1 imr3 14 1 6 1 <13> cm05mk0 5 1 <12> cm04mk0 4 1 <11> cm05mk1 <3> admk1 <10> cm04mk1 <2> admk0 <9> cm02mk1 1 1 <8> cm01mk1 0 1 address fffff106h after reset ffffh bit position bit name function 15 to 7, 4 to 0 (imr0) 15 to 5, 0 (imr1) 15 to 9, 4 to 0 (imr2) 13 to 7, 3, 2 (imr3) xxmkn interrupt mask flag 0: interrupt servicing enabled 1: interrupt servicing disabled (pending) remark xx: identification name of each peripheral unit (refer to table 7-2 ). n: peripheral unit number (refer table 7-2 )
chapter 7 interrupt/exception processing function 154 user?s manual u15195ej5v0ud 7.3.6 in-service priori ty register (ispr) this register holds the priority leve l of the maskable interrupt currently a cknowledged. when an interrupt request is acknowledged, the bit of this register co rresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the inte rrupt request having the highest priority is automatically cleared to 0 by hardware. however, it is not cleared to 0 when execution is returned from non-maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. caution in the interrupt enabled (ei) state, if an interrupt is acknowle dged during the reading of the ispr register, the value of the ispr register may be read after the bit is set (1) by this interrupt acknowledgment. to read the value of the ispr register properly before interrupt acknowledgment, read it in the interrupt disabled (di) state. address fffff1fah <7> ispr7 ispr <6> ispr6 <5> ispr5 <4> ispr4 <3> ispr3 <2> ispr2 <1> ispr1 <0> ispr0 after reset 00h bit position bit name function 7 to 0 ispr7 to ispr0 indicates priority of interrupt currently acknowledged 0: interrupt request with priority n not acknowledged 1: interrupt request with priority n acknowledged remark n = 0 to 7 (priority level)
chapter 7 interrupt/exception processing function 155 user?s manual u15195ej5v0ud 7.3.7 maskable interrupt status flag (id) the id flag is bit 5 of the psw and th is controls the maskable interrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 5 id indicates whether maskable interr upt servicing is enabled or disabled. 0: maskable interrupt request acknowledgment enabled 1: maskable interrupt request acknowledgment disabled (pending) this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt requests and exc eptions are acknowledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request generated during t he acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn register is set to 1, and the id flag is reset to 0. 7.3.8 interrupt trigger mode selection the valid edge of the intpn, adtrg0, adtrg1, tiud 10, tcud10, tclr10, tclr 3, and ti3 pins can be selected by program. the edge t hat can be selected as the valid edge is one of the following (n = 0 to 4, 20 to 25, 30, 31, 100, 101). ? rising edge ? falling edge ? both the rising and falling edges when the intpn, adtrg0, adtrg1, tiud10, tcud10, tclr10, tclr3, and ti3 signals are edge-detected, they become an interrupt s ource or capture trigger. the valid edge is specified by exter nal interrupt mode registers 1 and 2 (i ntm1 and intm2), signal edge selection register 10 (sesa10), the valid edge select ion register (sesc), and tm2 input filt er mode registers 0 to 5 (fem0 to fem5).
chapter 7 interrupt/exception processing function 156 user?s manual u15195ej5v0ud (1) external interrupt mode re gisters 1, 2 (intm1, intm2) these registers specify the valid edge for external interrupt requests (intp0 to intp4), input via external pins. the correspondence between each r egister and the external interrupt requests that register controls is shown below. ? intm1: intp0, intp1, intp2/adtrg0, intp3/adtrg1 ? intm2: intp4 intp2 and intp3 function alternately as adtrg0 and ad trg1 (a/d converter external trigger input). therefore, if the external trigger mode has been set by the trg0 to trg2 bits of a/d converter mode register n0 (adscmn0), setting the es20 and es21, and es30 and es31 bits of intm1 also specifies the valid edge of the external trigger input (adtrg0 and adtrg1) (n = 0, 1). the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. 7 es31 intm1 6 es30 5 es21 4 es20 3 es11 2 es10 1 es01 0 es00 address fffff882h after reset 00h intp3/adtrg1 intp2/adtrg0 intp1 intp0 7 0 intm2 6 0 5 0 4 0 3 0 2 0 1 es41 0 es40 address fffff884h after reset 00h intp4 bit position bit name function specifies the valid edge of the intpn, adtrg0 and adtrg1 pins. esn1 esn0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7 to 0 (intm1), 1, 0 (intm2) esn1, esn2 (n = 0 to 4)
chapter 7 interrupt/exception processing function 157 user?s manual u15195ej5v0ud (2) signal edge selection register 10 (sesa10) these registers specify the valid edge of external interrupt requests (intp100, intp101, tiud10, tcud10, and tclr10), input via external pins. the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. cautions 1. the bits of the sesa10 register ca nnot be changed during tm 10 operation (tm1ce0 bit of timer control register 10 (tmc10) = 1). 2. tm1ce0 bit must be set (1) before using the tcud10/intp100 and tclr10/intp101 pins as intp100 and intp101, even if not using timer 1. 3. setting the trigger mode of the intp 100, intp101, tiud10, tcud10, or tclr10 pin should be performed after setting the pmc1 register. if the pmc1 register is set after setti ng the sesa10 register, an invalid interrupt may occur when the pmc1 register is set. (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies1011 2 ies1010 1 ies1001 0 ies1000 address fffff5edh after reset 00h tiud10, tcud10 tclr10 intp101 intp100 bit position bit name function specifies the valid edge of the tiud10 and tcud10 pins. tesud01 tesud00 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesud01, tesud00 cautions 1. the values set to the tesud01 and tesud00 bits are valid only in udc mode a note 1 and udc mode b note 1 . 2. if tm10 operation has been specified in mode 4 note 2 , the valid edge specification (tesud01 and tesud00 bits) for the tiud10 and tcud10 pins is invalid. notes 1. see 9.2.4 (2) timer unit mode register 0 (tum0) . 2. see 9.2.4 (6) prescaler mode register 10 (prm10) .
chapter 7 interrupt/exception processing function 158 user?s manual u15195ej5v0ud (2/2) bit position bit name function specifies the valid edge of the tlcr10 pin cesud01 cesud00 valid edge 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 5, 4 cesud01, cesud00 the setting values of the cesud01 and cesud00 bits and the operation of tm10 are as follows. 00: tm10 cleared after detection of tclr10 rising edge 01: tm10 cleared after detection of tclr10 falling edge 10: tm10 holds cleared status while tclr10 input is low level 11: tm10 holds cleared status while tclr10 input is high level caution the values set to the cesud01 and cesud00 bits are valid only in udc mode a note . specifies the valid edge of the pin selected using the csl0 bit of the csl10 register (intp101/intp100) ies1011 ies1010 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1011, ies1010 specifies the valid edge of the intp100 pin ies1001 ies1000 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies1001, ies1000 note see 9.2.4 (2) timer unit mode register 0 (tum0) .
chapter 7 interrupt/exception processing function 159 user?s manual u15195ej5v0ud (3) valid edge selection register (sesc) this register specifies the valid edge for external inte rrupt requests (intp30, intp 31, tclr3, ti3), input via external pins. the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). this register can be read/written in 8-bit or 1-bit units. cautions 1. the tm3cae and tm3ce bits of timer control register 30 (tmc30) must be set (1) before using the ti3/tclr3/intp30 and to3/intp31 pins as intp30 and intp31, even if not using timer 3. 2. setting the trigger mode of the intp30, in tp31, tclr3, or ti3 pin should be performed after setting the pmc2 register. if the pmc2 register is set after setting th e sesc register, an inva lid interrupt may occur when the pmc2 register is set. 7 tes31 sesc 6 tes30 5 ces31 4 ces30 3 ies311 2 ies310 1 ies301 0 ies300 address fffff689h after reset 00h ti3 tclr3 intp31 intp30 bit position bit name function 7, 6 tes31, tes30 specifies the valid edge of the intp30, intp31, tclr3, or ti3 pins. xesn1 xesn0 valid edge 0 0 falling edge 5, 4 ces31, ces30 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies311, ies310 1, 0 tes301, tes300 remark n = 3, 30, 31
chapter 7 interrupt/exception processing function 160 user?s manual u15195ej5v0ud (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) these registers specify the valid edge for external interrupts input to timer 2 (intp20 to intp25). the correspondence between each register and t he external interrupt request that register controls is shown below. ? fem0: intp20 ? fem1: intp21 ? fem2: intp22 ? fem3: intp23 ? fem4: intp24 ? fem5: intp25 the valid edge can be specified i ndependently for each pin (rising edge, fa lling edge, or both rising and falling edges). these registers can be read/wri tten in 8-bit or 1-bit units. cautions 1. be sure to clear (0) the stfte bit of timer 2 clock stop regist er 0 (stopte0) even when using the ti2/intp20, to21/intp21, to22 /intp22, to23/intp23, to24/intp24, and tclr2/intp25 pins as intp20, intp21, intp22, intp23, intp24, and intp25, respectively, even if not using timer 2. 2. setting the trigger mode of the intp2n pin should be performed after setting the pmc2 register. if the pmc2 register is set after setting th e femn register, an inva lid interrupt may occur when the pmc2 register is set (n = 0 to 5). 3. the noise elimination function starts ope rating by setting the ceen bit of the tcre0 register to 1 (enab ling count operations).
chapter 7 interrupt/exception processing function 161 user?s manual u15195ej5v0ud (1/2) 7 dfen00 fem0 6 0 5 0 4 0 3 edge010 2 edge000 1 tms010 0 tms000 address fffff630h after reset 00h intp20 7 dfen01 fem1 6 0 5 0 4 0 3 edge011 2 edge001 1 tms011 0 tms001 address fffff631h after reset 00h intp21 7 dfen02 fem2 6 0 5 0 4 0 3 edge012 2 edge002 1 tms012 0 tms002 address fffff632h after reset 00h intp22 7 dfen03 fem3 6 0 5 0 4 0 3 edge013 2 edge003 1 tms013 0 tms003 address fffff633h after reset 00h intp23 7 dfen04 fem4 6 0 5 0 4 0 3 edge014 2 edge004 1 tms014 0 tms004 address fffff634h after reset 00h intp24 7 dfen05 fem5 6 0 5 0 4 0 3 edge015 2 edge005 1 tms015 0 tms005 address fffff635h after reset 00h intp25 bit position bit name function 7 dfen0n specifies the filter of the intp2n pin. 0: analog filter 1: digital filter caution when the dfen0n bit = 1, the sam pling clock of the digital filter is f xtm2 (clock selected by the prm02 register). specifies the valid edge of the intp2n pin. edge01n edge00n operation 0 0 interrupt by intcc2n note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges 3, 2 edge01n, edge00n note set when intcc2n is selected by a match between tm20, tm21 and the subchannel compare register (specified by the tms01n, tms00n bits) (n = 0 to 5). remark n = 0 to 5
chapter 7 interrupt/exception processing function 162 user?s manual u15195ej5v0ud (2/2) bit position bit name function selects the capture input note . tms01n tms00n operation 0 0 used as a pin 0 1 digital filter (noise eliminator specification) 1 0 timer-based capture to subchannel 1 1 1 timer-based capture to subchannel 2 1, 0 tms01n, tms00n note selection of capture input based on intcm100 and intcm101 is valid only for the fem1 and fem2 registers. set the tms01m and tms00m bits of t he femm register to 00b or 01b. all other settings are prohibited (m = 1, 3 to 5). subchannels 1 and 2 of timer 2 can be captured by intp21, intp22, and intcm100, intcm101. an example is given below. (a) when subchannel 1 is captured by intcm101 fem1 register = xxxxxx10b tmic0 register = 00000010b (b) when subchannel 2 is captured by intcm101 fem2 register = xxxxxx11b tmic0 register = 00001000b remark n = 0 to 5
chapter 7 interrupt/exception processing function 163 user?s manual u15195ej5v0ud 7.4 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can be always acknowledged. 7.4.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine: (1) saves the restored pc to eipc. (2) saves the current psw to eipsw. (3) writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). (4) sets the ep and id bits of the psw. (5) sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. figure 7-8 illustrates the processi ng of a software exception. figure 7-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 7 interrupt/exception processing function 164 user?s manual u15195ej5v0ud 7.4.2 restore returning from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. (1) loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. (2) transfers control to the address of the restored pc and psw. figure 7-9 illustrates the processi ng of the reti instruction. figure 7-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is n ecessary to set psw.ep back to 1 using the ldsr instruction immediately befo re the reti instruction. remark the solid lines show the cpu processing flow.
chapter 7 interrupt/exception processing function 165 user?s manual u15195ej5v0ud 7.4.3 exception status flag (ep) the ep flag is bit 6 of psw, and is a status flag used to indica te that exception processing is in progress. it is set when an exception occurs. 31 0 psw after reset 00000020h 7 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit position bit name function 6 ep shows that exception processing is in progress. 0: exception processing not in progress. 1: exception processing in progress.
chapter 7 interrupt/exception processing function 166 user?s manual u15195ej5v0ud 7.5 exception trap an exception trap is an interrupt that is requested when an illegal ex ecution of an instruction takes place. in the v850e/ia2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 7.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, sub-opcodes of 0111b to 1111b (bits 26 to 23), and 0b (bit 16). an exception trap is generated when an instru ction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible that this instruction will be assigned to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep, and id bits of the psw. (4) sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 7-10 illustrates the proce ssing of the exception trap.
chapter 7 interrupt/exception processing function 167 user?s manual u15195ej5v0ud figure 7-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore returning from exception trap processing is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address indicated by the restored pc and psw. figure 7-11 illustrates the processing fo r restoring from an exception trap. figure 7-11. processing for restoring from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 7 interrupt/exception processing function 168 user?s manual u15195ej5v0ud 7.5.2 debug trap the debug trap is an exception that can be acknowledged every time and is generated by exec ution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation when the debug trap is generated, the cpu performs the following proce ssing, transfers control to the debug monitor routine, and shifts to debug mode. (1) saves the restored pc to dbpc. (2) saves the current psw to dbpsw. (3) sets the np, ep and id bits of the psw. (4) sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. figure 7-12 illustrates the pr ocessing of the debug trap. figure 7-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing
chapter 7 interrupt/exception processing function 169 user?s manual u15195ej5v0ud (2) restore returning from debug trap processing is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. (1) loads the restored pc and psw from dbpc and dbpsw. (2) transfers control to the address indicated by the restored pc and psw. caution dbpc and dbpsw can be accessed during the period between when the dbtrap is executed and when the dbret instruction is executed. figure 7-13 illustrates the processi ng for restoring from a debug trap. figure 7-13. processing for restoring from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 7 interrupt/exception processing function 170 user?s manual u15195ej5v0ud 7.6 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher prio rity level, and the higher priority interrupt request is received and processed first. if there is an interrupt request with a lower priority level than the interrupt request curr ently being processed, that interrupt request is held pending. maskable interrupt multiple processing control is executed when interrupts are enabled (id = 0). thus, if multiple interrupts are executed, it is necessary for interrupts to be enabled (id = 0) even during an in terrupt servicing routine. if a maskable interrupt or a software e xception is generated in a maskable inte rrupt or software exception service program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgment of maskable interrupts in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (inte rrupt acknowledgment enabled) ... ... maskable interrupt acknowledgment ... ... ? di instruction (interr upt acknowledgment disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
chapter 7 interrupt/exception processing function 171 user?s manual u15195ej5v0ud (2) generation of exception in service program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interr upt servicing control has 8 levels, fr om 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. setting of the priority order level is done using the xxprn0 to xxprn2 bits of the interrupt control request regist er (xxlcn), which is provided for each maskable interrupt request. after system reset, an interrupt request is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request is acknowledged after the cu rrent interrupt servici ng has been completed and the reti instruction has been executed. caution in a non-maskable interrupt servicing routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged.
chapter 7 interrupt/exception processing function 172 user?s manual u15195ej5v0ud 7.7 interrupt response time the following table describes the v850e/ia 2 interrupt response time (from interr upt generation to start of interrupt servicing). figure 7-14. pipeline operation at inte rrupt request acknowledgment (outline) if if id ex df wb ifx ifx idx if if id ex int1 int2 int3 int4 internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt service routine) interrupt request 4 system clocks interleave access note note for details of interleave access, refer to 8.1.2 2-clock branch in v850e1 architecture user?s manual (u14559e) . remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt response time (i nternal system clock (f xx )) external interrupt internal interrupt intp0 to intp4, intp20 to intp25 intp20 to intp25 intp100, intp30, intp101, intp31 condition mini- mum 4 4+ analog delay time 4+ digital noise filter 4 + note 1 + digital noise filter maxi- mum 7 note 2 7+ analog delay time 7+ digital noise filter 7 + note 1 + digital noise filter the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non- sampling instructions are executed in succession ? access to on-chip peripheral i/o register notes 1. the number of internal system clocks is as follows. ? for timer 10 (tm10) using intp100 and intp101 as external interrupt inputs (see 9.2.4 (1) timer 1/timer 2 clock selection register (prm02) ): f clk = f xx /2 (prm2 bit = 1): 2 f clk = f xx /4 (prm2 bit = 0): 4 ? for timer 3 (tm3) using intp30 and intp31 as external interrupt inputs (see 9.4.5 (1) timer 3 clock selection register (prm03) ): f clk = f xx (prm3 bit = 1): 2 f clk = f xx /2 (prm3 bit = 0): 4 2. when ld instruction is executed to internal rom (during align access)
chapter 7 interrupt/exception processing function 173 user?s manual u15195ej5v0ud 7.8 periods in which cpu does not acknowledge interrupts the cpu acknowledges an interrupt wh ile an instruction is being execut ed. however, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction (int errupt is held pending). the interrupt request non-sampling instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the store instructions or bit mani pulation instructions of set1, clr1, and not1 instructions for the following registers: ? interrupt-related registers: interrupt control register (xxicn), inte rrupt mask registers 0 to 3 (imr0 to imr3) ? power save control register (psc) ? csi-related registers: clocked serial interface mode registers 0, 1 (csim0, csim1) clocked serial interface clock select ion registers 0, 1 (csic0, csic1) clocked serial interface receive bu ffer registers 0, 1 (sirb0, sirb1) clocked serial interface receive buffe r registers l0, l1 (sirbl0, sirbl1) clocked serial interface transmit bu ffer registers 0, 1 (sotb0, sotb1) clocked serial interface transmit buffe r registers l0, l1 (sotbl0, sotbl1) clocked serial interface read-only receiv e buffer registers 0, 1 (sirbe0, sirbe1) clocked serial interface read-only receive buffer registers l0, l1 (sirbel0, sirbel1) clocked serial interface initial transmit buffer registers 0, 1 (sotbf0, sotbf1) clocked serial interface initial transmit buffer registers l0, l1 (sotbfl0, sotbfl1) serial i/o shift registers 0, 1 (sio0, sio1) serial i/o shift registers l0, l1 (siol0, siol1) prescaler mode register (prsm3) prescaler compare register (prscm3) remark xx: identification name of each peripheral unit (refer to table 7-2 ) n: peripheral unit number (refer to table 7-2 )
174 user?s manual u15195ej5v0ud chapter 8 clock generation function the clock generator (cg) generates and controls t he internal system clock (f xx ) that is supplied to each internal unit, such as the cpu. 8.1 features ? multiplier function using a phase locked loop (pll) synthesizer ? clock sources ? oscillation by connecting a resonator ? external clock ? power-saving modes ? halt mode ? idle mode ? software stop mode ? internal system clock output function 8.2 configuration x1 x2 clock generator (cg) cksel (f x ) cpu, on-chip peripheral i/o time base counter (tbc) clkout f xx remark f x : external resonator or external clock frequency f xx : internal system clock
chapter 8 clock generation function 175 user?s manual u15195ej5v0ud 8.3 input clock selection the clock generator consists of an oscillator and a pll synthesizer. for example, connecting a 4.0 mhz crystal resonator or ceramic resonator to the x1 and x2 pins enables a 40 mhz internal system clock (f xx ) to be generated when the multiplier is 10. also, an external clock can be input directly to the osci llator. in this ca se, the clock signal should be input only to the x1 pin (the x2 pin should be left open). two basic operation modes are provided for the clock generator. these are the pll mode and the direct m ode. the operation mode is selected by the cksel pin. the input to this pin is latched on reset. cksel operation mode 0 pll mode 1 direct mode caution the input level for the cksel pin must be fixed. if it is switched during operation, a malfunction may occur. 8.3.1 direct mode in the direct mode, the external clock is divided by two and the divided clock is supplied as the internal system clock. the maximum frequency that can be input in the direct mode is 50 mhz. this mode is used in application system where the v850e/ia2 operates at relatively low frequencies. caution in direct mode, an external clock must be input (an external resonator should not be connected). 8.3.2 pll mode in pll mode, an external resonator is connected or external clock is input and multiplied by the pll synthesizer. the multiplied pll output is divided by the division ratio s pecified by the clock control register (ckc) to generate a system clock that is 10, 5, 2. 5, or 1 times the frequency (f x ) of the external resonator or external clock. after reset, an internal system clock (f xx ) that is 1 time the frequency (1 f x ) of the internal clock frequency (f x ) is generated. when a frequency that is 10 times the clock frequency (f x ) (10 f x ) is generated, a system with low noise and low power consumption can be realized because a frequency of up to 40 mhz is obtained based on a 4 mhz external resonator or external clock. in pll mode, if the clock supply from an external resonator or external clock source stops, operation of the internal system clock (f xx ) based on the self-propelled frequency of the clock gen erator?s internal voltage controlled oscillator (vco) continues. in this case, f xx is undefined. however, do not devise an application method expecting to use this self-propelled frequency. example: clocks when pll mode (f xx = 10 f x ) is used internal system clock frequency (f xx ) external resonator or external clock frequency (f x ) 40.000 mhz 4.0000 mhz
chapter 8 clock generation function 176 user?s manual u15195ej5v0ud caution only an f x value for which 10 f x does not exceed the system clock maximum frequency (40 mhz) (i.e. 4 mhz) can be used for the oscilla tion frequency or external clock frequency. when 5 f x , 2.5 f x , or 1 f x is used, a frequency of 4 to 6.4 mhz can be used. remark note the following when pll mode is selected (f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x ) if the v850e/ia2 does not need to be op erated at a high frequency, use f xx = 5 f x , f xx = 2.5 f x , or f xx = 1 f x to reduce the power consumption by loweri ng the system clock frequency using software. 8.3.3 peripheral command register (phcmd) this is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system so that the applicat ion system is not halted u nexpectedly due to erroneous program ex ecution. this register is write- only in 8-bit units (when it is read, undefined data is read out). writing to the first specific register (ckc or flpmc regist er) is only valid after first writing to the phcmd register. because of this, the register value can be overwritten only in the specified sequence, preventing an illegal write operation from being performed. 7 6 5 4 3 2 1 0 address after reset phcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff800h undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific registers targeted are as follows. ? clock control register (ckc) ? flash programming mode control register (flpmc) the generation of an illegal store oper ation can be checked with the prerr bit of the peripheral status register (phs).
chapter 8 clock generation function 177 user?s manual u15195ej5v0ud 8.3.4 clock control register (ckc) the clock control register is an 8-bit register that controls the internal system clock (f xx ) in pll mode. it can be written to only by a specific sequence combination so that it cannot easily be ov erwritten by mistake due to erroneous program execution. this register can be read or written in 8-bit units. caution do not change the ckdiv2 to ckdiv0 bits in direct mode. 7 6 5 4 3 2 1 0 address after reset ckc 0 0 tbcs cesel 0 ckdiv2 ckdiv1 ckdiv0 fffff822h 00h bit position bit name function 5 tbcs selects the time base counter clock. 0: f x /2 8 1: f x /2 9 for details, see 8.6.2 time base counter (tbc) . 4 cesel specifies the functions of the x1 and x2 pins. 0: a resonator is connected to the x1 and x2 pins 1: an external clock is connected to the x1 pin when cesel = 1, the oscillator feedback loop is disconnected to prevent current leakage in software stop mode. sets the internal sy stem clock frequency (f xx ) when pll mode is used. ckdiv2 ckdiv1 ckdiv0 internal system clock (f xx ) 0 0 0 f x 0 0 1 2.5 f x 0 1 1 5 f x 1 1 1 10 f x other than above setting prohibited 2 to 0 ckdiv2 to ckdiv0 caution when changing the internal system clock during operation, be sure to set the clock to be changed after setting the ckdiv2 to ckdiv0 bits to 000 (f x ). example clock generator settings ckc register operation mode cksel pin ckdiv2 ckdiv0 ckdiv0 input clock (f x ) internal system clock (f xx ) direct mode high-level input 0 0 0 16 mhz 8 mhz 0 0 0 4 mhz 4 mhz 0 0 1 5 mhz 12.5 mhz 0 1 1 6.4 mhz 32 mhz pll mode low-level input 1 1 1 4 mhz 40 mhz other than above setting pr ohibited setting prohibited
chapter 8 clock generation function 178 user?s manual u15195ej5v0ud data is set in the clock control register (ckc) according to the following sequence. <1> disable interrupts (set the np bit of psw to 1) <2> prepare data in any one of the general-purpose registers to set in the specific register. <3> write arbitrary data to the peripheral command register (phcmd) <4> set the clock control register (c kc) (with the following instructions). ? store instruction (st/sst instruction) <5> insert five or more nop instructions (5 inst ructions (<5> to <9>)) <10> release the interrupt disabled state (set the np bit of psw to 0). [sample coding] <1> ldsr rx, 5 <2> mov 0x04, r10 <3> st.b r10, phcmd [r0] <4> st.b r10, ckc [r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to psw ry: value returned to psw no special sequence is required to read the specific register. cautions 1. if an interrupt is ack nowledged between the issuing of data to phcmd <3> and writing to the specific register immediately a fter <4>, the write operation to the specific register is not performed and a protection error (the prerr bi t of the phs register = 1) may occur. therefore, set the np bit of the psw to 1 <1 > to disable interrupt acknowledgment. also disable interrupt acknowledgment when selecti ng a bit manipulation instruction for the specific register setting. 2. although the data written to the phcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting <4> for writing to the phcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. before executing this processing, complete all dma transfer operations.
chapter 8 clock generation function 179 user?s manual u15195ej5v0ud 8.3.5 peripheral status register (phs) if a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protecti on error is generated, setting the status flag (prerr) to 1. this flag is a cumula tive flag. after checking the prerr flag, it is cleared to 0 by an instruction. this register can be read or written in 8-bit or 1-bit units 7 6 5 4 3 2 1 <0> address after reset phs 0 0 0 0 0 0 0 prerr fffff802h 00h bit position bit name function 0 prerr 0: protection error does not occur 1: protection error occurs the operation conditions of the prerr flag are as follows. set conditions: <1> if the operation of t he relevant store instruction for the on-chip peripheral i/o is not a write operation for the phcmd register, but the peri pheral specific register is written to. <2> if the first store instruction operation after the write operation to the phcmd register is for memory other than the specific registers and on-chip peripheral i/o. reset conditions: <1> if the prerr flag of the phs register is set to 0. <2> if the system is reset
chapter 8 clock generation function 180 user?s manual u15195ej5v0ud 8.4 pll lockup the lockup time (frequency stabilization time) is the time from when the power is turned on or the software stop mode is released until the phase locks at the prescribed frequen cy. the state until this stab ilization occurs is called a lockup state, and the stabilized state is called a lock state. the lock register (lockr) has a lock flag that re flects the stabilized state of the pll frequency. this register is read-only, in 8-bit or 1-bit units. caution when the pll is locked, the lock flag is 0. if the system then enters an unlocked state due to a standby, the lock flag becomes 1. if anything other than a standby causes the system to enter an unlocked state, the lock fl ag is not affected (lock = 0). 7 6 5 4 3 2 1 <0> address after reset lockr 0 0 0 0 0 0 0 lock fffff824h 0000000xb bit position bit name function 0 lock this is a read-only flag that indicates the pll state. this flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset. 0: indicates that the pll is locked. 1: indicates that the pll is not locked (unlock state). if the clock stops, the power fails, or some other factor oper ates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the lock flag using software immediately after operation begins so that processing does not begin until after the clock stabilizes. on the other hand, static proce ssing such as the setting of internal hardware or the initialization of register data or memory data can be executed without wa iting for the lock flag to be reset. the relationship between the oscillation st abilization time (the time from when t he resonator starts to oscillate until the input waveform stabilizes) when a resonator is used, an d the pll lockup time (the time until frequency stabilizes) is shown below. oscillation stabilization time < pll lockup time
chapter 8 clock generation function 181 user?s manual u15195ej5v0ud 8.5 power save control 8.5.1 overview the power save function has the following three modes. (1) halt mode in this mode, the clock generator (oscillator and pl l synthesizer) continues to operate, but the cpu's operation clock stops. since the supply of clocks to on-chip peripheral functions other than the cpu continues, operation continues. the power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combinat ion of halt mode and normal operation mode. the system is switched to halt mode by a specific instruct ion (the halt instruction). (2) idle mode in this mode, the clock generator (oscillator and pll synthesizer) continues to oper ate, but the supply of internal system clocks is stopped, which causes the overall system to stop. when the system is released from idle mode, it can be switched to normal operation mode quickly because the oscillator's oscillation stabi lization time need not be secured. the system is switched to idle mode ac cording to a psmr register setting. idle mode is located midway between software stop mode and halt mode in relation to the clock stabilization time and current consumption. it is used for situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) software stop mode in this mode, the overall system is stopped by stopping the cl ock generator (oscillator and pll synthesizer). the system enters an ultra-low pow er consumption state in which only leak current is lost. the system is switched to software stop mode according to a psmr register setting. (a) pll mode the system is switched to software stop mode by setting the register by software. the pll synthesizer's clock output is stopped at the same time that the oscillator is stopped. after software stop mode is released, the oscillator's oscillation stabiliz ation time must be secured while the system clock stabilizes. also, pll lockup time may be required depending on the program. when a resonator or external clock is connected, following the release of the software stop mode, execution of the program is started after the count time of the time base counter has elapsed. (b) direct mode to stop the clock, set the x1 pin to low level. after the release of software stop mode, execution of the program is started after the count-time of the time base counter has elapsed.
chapter 8 clock generation function 182 user?s manual u15195ej5v0ud figure 8-1 shows the operati on of the clock generator in normal operation mode, halt mode, idle mode, and software stop mode. an effective low power consumption system can be r ealized by combining these modes and switching modes according to the required use. figure 8-1. power save mode state transition diagram normal operation mode software stop mode set stop mode idle mode set idle mode release according to reset, nmi, or maskable interrupt note set halt mode release according to reset, nmi, or maskable interrupt halt mode release according to reset, nmi, or maskable interrupt note note intpn (n = 0 to 4, 20 to 25) however, in cases such as when a digital filter us ing clock sampling is selected as the noise eliminator for intp20 to intp25, the software stop or idle mode cannot be released.
chapter 8 clock generation function 183 user?s manual u15195ej5v0ud table 8-1. clock generator oper ation using power save control clock source power save mode oscillator pll synthesizer clock supply to peripheral i/o clock supply to cpu normal operation halt mode ? idle mode ? ? oscillation with resonator software stop mode ? ? ? ? normal operation ? halt mode ? ? idle mode ? ? ? pll mode external clock software stop mode ? ? ? ? normal operation ? ? halt mode ? ? ? idle mode ? ? ? ? direct mode external clock software stop mode ? ? ? ? remark : operating ? : stopped
chapter 8 clock generation function 184 user?s manual u15195ej5v0ud 8.5.2 control registers (1) power save mode register (psmr) this is an 8-bit register that controls the power save mode. it is effective only when the stb bit of the psc register is set to 1. writing to the psmr is executed by st ore instructions (st/sst instruction) and bit manipulation instructions (set1/clr1/not1 instruction). this register can be read or written in 8-bit or 1-bit units. 7 6 5 4 3 2 1 <0> address after reset psmr 0 0 0 0 0 0 0 psm fffff820h 00h bit position bit name function 0 psm specifies idle mode or software stop mode. 0: switches the system to idle mode 1: switches the system to software stop mode (2) command register (prcmd) this is an 8-bit register that is used to set protection for write operations to regi sters that can significantly affect the system so that the appl ication system is not halted unexpe ctedly due to erroneous program execution. writing to the first specific register (power save contro l register (psc)) is only valid after first writing to the prcmd register. because of this, the register value can be overwritten only by the specified sequence, preventing an illegal write o peration from being performed. this register is write-only in 8-bit uni ts. undefined data is read out if read. 7 6 5 4 3 2 1 0 address after reset prcmd reg7 reg6 reg5 reg4 reg3 reg2 reg1 reg0 fffff1fch undefined bit position bit name function 7 to 0 reg7 to reg0 registration code (arbitrary 8-bit data) the specific register targeted is t he power save control register (psc).
chapter 8 clock generation function 185 user?s manual u15195ej5v0ud (3) power save control register (psc) this is an 8-bit register that co ntrols the power save function. if releasing of interrupts are enabled by the setting of the nmim and intm bits, the software stop mode can be released by an interrupt request (except when interr upt servicing is disabled by the interrupt mask registers (imr0 to imr3)). the software stop mode is specifie d by the setting of the stb bit. this register, which is one of the specific registers, is effective onl y when accessed by a specific sequence during a write operation (see 3.4.9 specific registers ). this register can be read or written in 8-bit or 1-bit units. be sure to clear bits 7 and 6 to 0. if they are set to 1, the operat ion is not guaranteed. caution it is impossible to set the stb bit and nmim or intm bit at the same time. be sure to set the stb bit after setting the nmim or intm bit. 7 6 <5> <4> 3 2 <1> 0 address after reset psc 0 0 nmim intm 0 0 stb 0 fffff1feh 00h bit position bit name function 5 nmim this is the enable/disable setting bit for standby mode release using valid edge input of nmi note . 0: enables nmi cancellation 1: disables nmi cancellation 4 intm this is the enable/disable setting fo r standby mode release using an unmasked maskable interrupt (intpn) (n = 0 to 4, 20 to 25, 30, 31, 100, 101) note . 0: enables maskable interrupt cancellation 1: disables maskable interrupt cancellation 1 stb indicates the standby mode status. if 1 is written to this bit, the system ent ers standby mode (when it is in idle or software stop mode). when standby mode is released, this bit is automatically reset to 0. 0: standby mode is released 1: standby mode is in effect note setting these bits is valid only in the idle/software stop mode. data is set in the power save control regist er (psc) according to the following sequence. <1> set the power save mode register ( psmr) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <2> prepare data in any one of the general-purpose registers to set to the specific register. <3> write arbitrary data to the command register (prcmd). <4> set the power save control register (psc) (with the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> assert the nop instructions (5 instructions (<5> to <9>).
chapter 8 clock generation function 186 user?s manual u15195ej5v0ud [sample coding] <1> st.b r11, psmr [r0] ; set psmr register <2> mov 0 04, r10 ; prepare data for setting specific register in general-purpose register <3> st.b r10, prcmd [r0] ; write prcmd register <4> st.b r10, psc [r0] ; set psc register <5> nop ; dummy instruction <6> nop ; dummy instruction <7> nop ; dummy instruction <8> nop ; dummy instruction <9> nop ; dummy instruction (next instruction) ; execution routine after software stop mode and idle mode release no special sequence is required to read the specific register. cautions 1. interrupts are not acknowledged in store instructions for the command register. this coding is made on assumption that <3> and <4 > above are executed by the program with consecutive store instructions. if another instruction is set between <3> and <4>, the above sequence may become ineffecti ve when the interrupt is ackno wledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register used in specific register setting <4> for writing to the prcmd register (<3>). the same method should be applied when using a ge neral-purpose register for addressing. 3. at least 5 nop instructions must be inserted after executi ng a store instruction to the psc register to set software stop or idle mode. 4. before executing this processing, complete all dma transfer operations.
chapter 8 clock generation function 187 user?s manual u15195ej5v0ud 8.5.3 halt mode (1) setting and operation status in the halt mode, the clock generat or (oscillator and pll synthesizer) continues to operate, but the operation clock of the cpu is stopped. since the supp ly of clocks to on-chip peripheral i/o units other than the cpu continues, operation contin ues. the power consumption of th e overall system can be reduced by setting the system to halt mode while the cpu is idle. the system is switched to halt mode by the halt instruction. although program execution stops in t he halt mode, the contents of all r egisters, internal ram, and ports are maintained in the state they were in immediately before halt mode began. al so, operation continues for all on-chip peripheral i/o units (other than ports) that do not depend on cpu instruct ion processing. table 8-2 shows the status of each hardware unit in the halt mode. table 8-2. operation status in halt mode function operation status clock generator operating internal system clock operating cpu stopped ports maintained on-chip peripheral i/o (e xcluding ports) operating internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before halt mode began. ad0 to ad15 a16 to a21 rd, astb uwr, lwr wait operating clkout clock output
chapter 8 clock generation function 188 user?s manual u15195ej5v0ud (2) release of halt mode halt mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or reset pin input. (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request halt mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. however, if the system is set to halt mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, halt m ode is released, but the newly ge nerated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, halt mode is released and the newly generated interrupt request is acknowledged. table 8-3. operation after halt mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction (b) release by reset pin input this is the same as a normal reset operation.
chapter 8 clock generation function 189 user?s manual u15195ej5v0ud 8.5.4 idle mode (1) setting and operation status in the idle mode, the clock generator (oscillator and pl l synthesizer) continues to operate, but the supply of internal system clocks is stopped which c auses the overall system to stop. when idle mode is released, the system can be s witched to normal operation mode quickly because the oscillator's oscillation stabilization time or the pll lockup time do not need to be secured. the system is switched to idle mode by setting the psc or psmr register using a store instruction (st or sst instruction) or a bit manipulation instruct ion (set1, clr1, or not1 instruction) (see 8.5.2 control registers ). in the idle mode, program execution is stopped, and the contents of all registers, internal ram, and ports are maintained in the state they were in immediat ely before execution stopped. the operation of on-chip peripheral i/o units (excluding ports) also is stopped. table 8-4 shows the status of eac h hardware unit in the idle mode. table 8-4. operation status in idle mode function operation status clock generator operating internal system clock stopped cpu stopped ports maintained on-chip peripheral i/o (excluding ports) stopped (csi0 and csi1 are operable in slave mode) internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are maintained in the state they were in immediately before idle mode began. ad0 to ad15 a16 to a21 high impedance rd uwr, lwr high level output wait input (no sampling) astb high-level output clkout low-level output
chapter 8 clock generation function 190 user?s manual u15195ej5v0ud (2) release of idle mode idle mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intpn) note , or reset pin input (n = 0 to 4, 20 to 25). note when a digital filter using clock sampling is select ed as the noise eliminator for intp20 to intp25, idle mode cannot be released. (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request idle mode is released by an interrupt request onl y when transition to idle mode is performed with the intm and nmim bits of the psc register set to 0. idle mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intpn) regardless of the priority (n = 0 to 4, 20 to 25). the operation after release is as follows. caution when the nmim and intm bits of the psc register = 1, the idle mode cannot be released by the non-maskable interrupt request signal and un masked maskable interrupt request signal. table 8-5. operation after idle mode is released by interrupt request release source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to idle mode during a maskable interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being serviced, idle mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt reques t that is currently being servic ed, idle mode is released and the newly generated interrupt request is acknowledged. if the system is set to idle mode during an nmi se rvicing routine, idle mode is released, but the interrupt is not acknowledged (interrupt is held pending). interrupt servicing that is started when idle mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing that occu rs during an emergency (because the nmi interrupt handler address is unique). ther efore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the psmr register using a store instructi on or a bit manipulation instruction. by checking for this status during nmi interrupt servicing, an ordinary nmi can be distinguished from the pr ocessing that is started when idle mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation.
chapter 8 clock generation function 191 user?s manual u15195ej5v0ud 8.5.5 software stop mode (1) setting and operation status in the software stop mode, the cl ock generator (oscillator and pll synt hesizer) is stopped. the overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. the system is switched to software st op mode by using a store instructi on (st or sst instruction) or bit manipulation instruction (set1, clr1, or not1 in struction) to set the psc and psmr registers (see 8.5.2 control registers ). when pll mode and resonator connection mode (cesel bit of ckc register = 1) ar e used, the oscillator's oscillation stabilization time must be secu red after software stop mode is released. in both pll and direct mode, following the release of software stop mode, execution of the program is started after the count time of the time base counter has elapsed. although program execution stops in software stop mode, the contents of all registers, internal ram, and ports are maintained in the state they were in i mmediately before software stop mode began. the operation of all on-chip peripheral i/o uni ts (excluding ports) is also stopped. table 8-6 shows the status of each har dware unit in the software stop mode. table 8-6. operation stat us in software stop mode function operation status clock generator stopped internal system clock stopped cpu stopped ports maintained note on-chip peripheral i/o (excluding ports) stopped (csi0 and csi1 are operable in slave mode) internal data all internal data such as cpu registers, statuses, data, and the contents of internal ram are retained in the state before software stop mode has been set note . ad0 to ad15 a16 to a21 high impedance rd uwr, lwr high-level output wait input (no sampling) astb high-level output clkout low-level output note when the v dd value is within the operable range. howe ver, even if it drops below the minimum operable voltage, as long as the data retention voltage v dddr is maintained, the contents of only the internal ram will be maintained.
chapter 8 clock generation function 192 user?s manual u15195ej5v0ud (2) release of software stop mode software stop mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (intpn) note , or reset pin input. also, to release software stop mode when pll mode (cksel pin = low level) and resonator connection mode (cesel bi t of ckc register = 0) are used, the oscillator?s oscillation stabilization time must be secured (n = 0 to 4, 20 to 25) moreover, the oscillation stabilization time must be secured even when an external clock is connected (cesel bit = 1). see 8.4 pll lockup for details. note when a digital filter using clock sampling is select ed as the noise eliminator for intp20 to intp25, software stop mode cannot be released. (a) release by a non-maskable interrupt request or an unmasked maska ble interrupt request software stop mode is released by an interrupt request only when transition to software stop mode is performed with the intm and nmim bits of the psc register set to 0. software stop mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (intpn) regardless of the priority (n = 0 to 4, 20 to 25). the operation after release is as follows. caution when the nmim and intm bits of the psc register = 1, the software stop mode cannot be released by the non-maskable interr upt request signal and unmasked maskable interrupt request signal. table 8-7. operation after software stop mode is released by interrupt request cancellation source enable interrupt (ei) status disable interrupt (di) status non-maskable interrupt request branch to handler address maskable interrupt request branch to handler address or execute next instruction execute next instruction if the system is set to software stop mode during an interrupt servicing routine, operation will differ as follows. (i) if an interrupt request is generated with a lower pr iority than that of the interrupt request that is currently being servicing, software stop mode is released, but the newly generated interrupt request is not acknowledged. the new interrupt request is held pending. (ii) if an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, software stop mode is released and the newly generated interrupt request is acknowledged. if the system is set to software stop mode during an nmi servicing routine, software stop mode is released, but the interrupt is not ackn owledged (interrupt is held pending). interrupt servicing that is start ed when software stop mode is released by nmi pin input is handled in the same way as normal nmi interrupt servicing t hat occurs during an emergency (because the nmi interrupt handler address is unique) . therefore, when a program must be able to distinguish between these two situations, a software status must be prepar ed in advance and that status must be set before setting the psmr register using a store instru ction or a bit manipulation instruction. by checking for this status during nmi interrupt servic ing, an ordinary nmi can be distinguished from the servicing that is started when software stop mode is released by nmi pin input. (b) release by reset pin input this is the same as a normal reset operation.
chapter 8 clock generation function 193 user?s manual u15195ej5v0ud 8.6 securing oscillation stabilization time 8.6.1 oscillation stabilizatio n time security specification two specification methods can be used to secure the time from when software stop mode is released until the stopped oscillator stabilizes. (1) securing the time using an on-chip time base counter software stop mode is released when a valid edge is input to the nmi pin or a maskable interrupt request is input (intpn). when a valid edge is input to the pin c ausing the start of oscillat ion, the time base counter (tbc) starts counting, and the time un til the clock output from the oscillat or stabilizes is secured during that counting time (n = 0 to 4, 20 to 25). oscillation stabilization time = tbc counting time after a fixed time, internal system clock output be gins, and processing branches to the nmi interrupt or maskable interrupt (intpn) handler address. oscillation waveform (x2) set software stop mode oscillator is stopped clkout (output) internal main clock stop state nmi (input) note time base counter?s counting time note valid edge: when specified as the rising edge. the nmi pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance. software stop mode is immediately released if an operat ion that sets software stop mode before the cpu can acknowledge interrupts is performed due to nmi va lid edge input or maskable interrupt request input (intpn). if the direct mode or external clock connection mode (cesel bit of ckc register = 1) is used, program execution begins after the count time of the time base counter has elapsed. also, even if the pll mode and resonator connection mode (cesel bit of ckc register = 0) are used, program execution begins after the oscillation stab ilization time is secured by the time base counter.
chapter 8 clock generation function 194 user?s manual u15195ej5v0ud (2) securing the time according to th e signal level width (reset pin input) software stop mode is released by falling edge input to the reset pin. the time until the clock output from the oscillator stabilizes is secure d based on the low-level width of the signal that is input to the pin. the supply of internal system clocks be gins after a rising edge is input to the reset pin, and processing branches to the handler addr ess used for a system reset. oscillation waveform (x2) set software stop mode oscillator is stopped internal main clock stop state internal system reset signal oscillation stabilization time secured by reset reset (input) undefined clkout (output) undefined 8.6.2 time base counter (tbc) the time base counter (tbc) is used to secure the oscill ator?s oscillation stabilization time when software stop mode is released. when an external clock is connected (cesel bit of ckc regi ster = 1) or a resonator is connected (pll mode and cesel bit of ckc register = 0), the tbc counts the o scillation stabilization time after software stop mode is released, and program execution begi ns after the count is completed. the tbc count clock is selected by the tbcs bit of th e ckc register, and the next counting time can be set (reference). table 8-8. counting time examples (f xx = 10 f x ) counting time tbcs bit count clock f x = 4.0000 mhz 0 f x /2 8 16.4 ms 1 f x /2 9 32.8 ms f xx : internal system clock f x : external oscillation frequency
195 user?s manual u15195ej5v0ud chapter 9 timer/counter function 9.1 timer 0 9.1.1 features (timer 0) timers 00 and 01 (tm00, tm01) are 16-bit timer/counters ideal for controlling high -speed inverters such as motors. ? 3-phase pwm output function pwm mode 0 (symmetric triangular wave) pwm mode 1 (asymmetric triangular wave) pwm mode 2 (sawtooth wave) ? interrupt culling function culling ratios: 1/1, 1/2, 1/4, 1/8, 1/16 ? forcible 3-phase pwm output stop function 3-phase pwm output can be forcibly stopped by inputting a signal to the external signal input pin eson when an anomaly occurs. this function can also be used when the clock is stopped. ? real-time output function 3-phase pwm output or rectangular wave output can be selected at the desired timing. ? output of positive phase and neg ative phase or positive phase and in-phase of 3-phase pwm output
chapter 9 timer/counter function 196 user?s manual u15195ej5v0ud 9.1.2 function overview (timer 0) ? 16-bit timer (tm0n) for 3-phase pwm inverter control: 2 channels ? compare registers: 6 registers 2 channels ? 12-bit dead-time timers (dtmn0 to dtmn2): 3 timers 2 channels ? count clock division selectable by prescaler (set the frequency of the count clock to 40 mhz or less) ? base clock (f clk ): 2 types (set f clk to 40 mhz or less) f xx and f xx /2 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx selected f xx /2 selected 1/1 f xx f xx /2 1/2 f xx /2 f xx /4 1/4 f xx /4 f xx /8 1/8 f xx /8 f xx /16 1/16 f xx /16 f xx /32 1/32 f xx /32 f xx /64 ? interrupt request sources (a) compare-match interrupt request: 9 types ? interrupt request signal intcm0n3 generated by ma tch of tm0n register count value and compare register cm0n3 ? interrupt request signals intcm010 to intcm 012, intcm0n4, and intcm0n5 generated by match of tm0n register count value and compare registers cm010 to cm012, cm0n4, and cm0n5 setting condition intcm010 to intcm012, intcm0n4, intcm0n5 signal occurrence status cm010 to cm012, cm0n4, cm0n5 cm0n3 occurs cm010 to cm012, cm0n4, cm0n5 = 0000h occurs cm010 to cm012, cm0n4, cm0n5 > cm0n3 does not occur (b) underflow interrupt request: 2 types ? interrupt request signal inttm0n generat ed by underflow of the tm0n register ? external pulse output (to0n0 to to0n5): 6 2 channels remark f xx : internal system clock n = 0, 1
chapter 9 timer/counter function 197 user?s manual u15195ej5v0ud 9.1.3 functions added to v850e/ia2 (1) addition of bfcmn4 and cm0n4 regi sters, and bfcmn5 and cm0n5 registers when the tm0cen bit of the tmc0n register is 1 (counting enabled), transferring data from the bfcmn4 or bfcmn5 register to the cm0n4 or cm0n5 register is enabled or disabled by the bften bit of the tmc0n register (n = 0, 1). (2) compare-match interrupt out put function of cm010 to cm012, cm0n4, and cm0n5 registers (intcm010 to intcm012, intcm0n4, intcm0n5) the features of the compare-ma tch interrupt output function (intcm010 to intcm012, intcm0n4, intcm0n5) of the cm010 to cm012, cm0n4, and cm 0n5 registers are as follows (n = 0, 1): (a) this interrupt signal is not affected by the stintn bit of the tmc0n register t hat specifies occurrence of an interrupt when timer tm0n is started. (b) the compare-match interrupt output function of the cm010 to cm012, cm0n4, and cm0n5 registers does not have an interrupt culling func tion. therefore, it is not affe cted by the cul02 to cul00 bits of the tmc0n register. the sources of this interrupt signal are shown below. table 9-1. sources of intcm010 to intcm012, intcm0n4 , and intcm0n5 unit interrupt name a/d trigger function interrupt function dma trigger source intcm000 to intcm002 note tm00 intcm004, intcm005 intcm010 to intcm012 tm01 intcm014, intcm015 note the v850e/ia2 does not include intcm000 to intcm002. remarks 1. : function provided : function not provided 2. n = 0, 1
chapter 9 timer/counter function 198 user?s manual u15195ej5v0ud 9.1.4 basic configuration the basic configuration is shown below. figure 9-1. block diagram of timer 0 (mode 0: symmetric tria ngular wave, mode 1: asymmetric triangular wave) selector f xx /2 bfcmn3 cm0n3 bfcmn0 cm0n0 bfcmn1 cm0n1 bfcmn2 cm0n2 bfcmn4 cm0n4 bfcmn5 cm0n5 tm0n s/r 1/1 1/2 1/4 1/8 1/16 1/32 16 16 12 f clk intcm0n3 inttm0n intcm010 intcm011 intcm012 intcm0n4 intcm0n5 r s r s r s r s r s r s r s r s r s dtmn2 dtmn1 dtmn0 dtrrn alvto alvub alvvb alvwb output control by external input (eson), tm0n timer operation 6 underflow underflow underflow to0n0 (u phase) to0n1 (u phase) to0n2 (v phase) to0n3 (v phase) to0n4 (w phase) to0n5 (w phase) f xx remarks 1. tm0n: timer register cm0n0 to cm0n5: compare registers bfcmn0 to bfcmn5: buffer registers dtrrn: dead-time timer reload register dtmn0 to dtmn2: dead-time timers alvto: bit 7 of tomrn register alvub: bit 6 of tomrn register alvvb: bit 5 of tomrn register alvwb: bit 4 of tomrn register s/r: set/reset 2. n = 0, 1 3. f xx : internal system clock 4. f clk : base clock (40 mhz (max.))
chapter 9 timer/counter function 199 user?s manual u15195ej5v0ud figure 9-2. block diagram of ti mer 0 (mode 2: sawtooth wave) selector f xx /2 bfcmn3 cm0n3 bfcmn0 cm0n0 bfcmn1 cm0n1 bfcmn2 cm0n2 tm0n 1/1 1/2 1/4 1/8 1/16 1/32 16 16 12 f clk intcm0n3 r s r s r s dtmn2 dtmn1 dtmn0 dtrrn output control by external input (eson), tm0n timer operation clear underflow underflow underflow r s r s r s r s r s r s alvto alvub alvvb alvwb 6 to0n0 (u phase) to0n1 (u phase) to0n2 (v phase) to0n3 (v phase) to0n4 (w phase) to0n5 (w phase) bfcmn4 cm0n4 bfcmn5 cm0n5 intcm0n4 intcm0n5 intcm010 intcm011 intcm012 f xx remarks 1. tm0n: timer register cm0n0 to cm0n5: compare registers bfcmn0 to bfcmn5: buffer registers dtrrn: dead-time timer reload register dtmn0 to dtmn2: dead-time timers alvto: bit 7 of tomrn register alvub: bit 6 of tomrn register alvvb: bit 5 of tomrn register alvwb: bit 4 of tomrn register 2. n = 0, 1 3. f xx : internal system clock 4. f clk : base clock (40 mhz (max.))
chapter 9 timer/counter function 200 user?s manual u15195ej5v0ud (1) timers 00, 01 (tm00, tm01) tm0n operates as a 16-bit up/down timer or up timer. the cycle is c ontrolled by compare register 0n3 (cm0n3) (n = 0, 1). tm0n start/stop is controlled by the tm0cen bi t of timer control register 0n (tmc0n). division by the prescaler can be selected for the count clock from among f clk , f clk /2, f clk /4, f clk /8, f clk /16, f clk /32 using the prm02 to prm00 bits of the tmc0n registers (f clk : base clock, see 9.1.5 (1) timer 0 clock selection register (prm01) ). the conditions when tm0n becomes 0000h are as follows. ? reset input ? tm0cen bit = 0 ? tm0n register and compare register 0n3 (cm0n3) match (pwm mode 2 (sawtooth wave) only) ? immediately after overflow or underflow the tm0n timer has 3 operation modes, shown in table 9-2. the operation mode is selected using timer control register 0n (tmc0n). table 9-2. operation modes of timer 0 operation mode count operation timer clear source interrupt source bfcmn3 cm0n3 transfer timing bfcmn0 to bfcmn2, bfcmn4, bfcmn5 cm0n0 to cm0n2, cm0n4, cm0n5 transfer timing pwm mode 0 (symmetric triangular wave) up/down ? inttm0n, intcm010 to intcm012, intcm0n3 to intcm0n5 inttm0n inttm0n pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n, intcm010 to intcm012, intcm0n3 to intcm0n5 inttm0n inttm0n, intcm0n3 pwm mode 2 (sawtooth wave) up intcm0n3 intcm010 to intcm012, intcm0n3 to intcm0n5 intcm0n3 intcm0n3 caution even if tm0icn, cm03icn, or an interrupt mask flag of the imr0 register (tm0mkn or cm03mkn) is set (interrupt disabled) as the interrupt s ources inttm0n and intcm0n3, it simply results in no interrupt occurrence and does not af fect the operation of timer 0. the interrupt sources intcm010 to intcm012, intcm0n4, and intcm0n5 do not affect the operation of timer 0 regardless of whet her the interrupt is masked or not. remark n = 0, 1
chapter 9 timer/counter function 201 user?s manual u15195ej5v0ud (2) dead-time timers 00 to 02, 10 to 12 (dtm00 to dtm02, dtm10 to dtm12) dtmn0 to dtmn2 are dedicated 12-bit down timers that generate dead time, which is effective for inverter control applications. dtmn0 to dt mn2 operate as one-shot timers. counting by a dead-time timer is enabled or disabled by the tm0cedn bit of timer control register 0n (tmc0n) and cannot be controlled by software. de ad-time timer count start and stop is controlled by hardware. a dead-time timer starts counting down when the value of dead-time timer reload register n (dtrrn) is transferred in synchronization with the compare match timing of cm0n0 to cm0n2. when the value of a dead-time timer changes from 000h to fffh, the dead-time timer generates an underflow signal, and the timer stops at the value fffh. if the value of a dead-time timer matches the value of the corresponding compare register before underflow of the dead-time timer takes place, the value of dtrrn is transferred to the dead-time timer again, and the timer starts counting down. the count clock of the dead-time ti mer is fixed to the base clock (f clk ), and the dead-time width is (set value of dtrrn + 1)/base clock (f clk ). if tm0n operates in pwm mode 0 or pwm mode 1 with the dead-time timer count operation disabled, an inverted signal without dead time is output to to0n0 and to0n1, to0n2 and to0n3, and to0n4 and to0n5. (3) dead-time timer reload re gisters 0, 1 (dtrr0, dtrr1) the dtrrn register is a 12-bit register used to set the values of the three dead-time timers (dtmn0 to dtmn2 registers) (n = 0, 1). however, a value is transferred from the dtrrn register to each dead-time register independently. dtrrn can be read/written in 16-bit units. all 0s are read for the higher 4 bits when the dtrrn register is read accessed in 16 bits. 14 0 13 0 12 0 2 3 4 5 6 7 8 9 10 11 15 0 10 dtrr0 address fffff570h after reset 0fffh 14 0 13 0 12 0 2 3 4 5 6 7 8 9 10 11 15 0 10 dtrr1 address fffff5b0h after reset 0fffh cautions 1. changing the value of the dtrrn regi ster during tm0n operation (tm0cen bit of tmc0n register = 1) is prohibited. 2. be sure to write 0 to the higher 4 bits. (4) compare registers 000 to 002, 010 to 012 (cm000 to cm002, cm010 to cm012) cm0n0 to cm0n2 are 16-bit registers t hat always compare their own values with the value of tm0n. if the value of a compare register matches the value of tm0n, the compare register outputs a trigger signal, and changes the contents of the flip-flop (f/f) connected to the compar e register. each of cm0n0 to cm0n2 is provided with a buffer register (bfcmn0 to bfcmn2), so that the contents of the buffer are transferred to cm0n0 to cm0n2 at the next transfer timing. transfer is enabled or disabled by the bften bit of the tmc0n register. if cm010 to cm012 of timer 01 match tm01, the intcm010 to intcm012 interrupts occur.
chapter 9 timer/counter function 202 user?s manual u15195ej5v0ud (5) compare registers 004, 005, 014, 015 (cm004, cm005, cm014, cm015) cm0n4 and cm0n5 are 16-bit registers that always compar e their value with tm0n. if the value of these registers matches the value of tm0n, the registers generate an interrupt signal (intcm0n4 or intcm0n5). cm0n4 and cm0n5 are also provided with a buffer register (bfcmn4 or bfcmn5), t he contents of which are transferred to cm0n4 or cm0n5 at the next transfer timing. transfer is enabled or disabled by the bften bit of the tmc0n register. (6) compare registers 003, 013 (cm003, cm013) cm0n3 is a 16-bit register that always compare its value with the value of tm0n. if the values match, cm0n3 outputs an interrupt signal (intcm 0n3). cm0n3 controls the maximum count value of tm0n, and if the values match, it performs the following operat ions at the next timer count clock. ? in triangular wave setting mode (pwm modes 0, 1): switches tm0n operation from count up to count down ? sawtooth wave setting mode (pwm mode 2): clears the count value of tm0n cm0n3 also has a buffer register (bfcmn3) and transfer s the buffer contents to cm0n3 at the next transfer timing. transfer enable or disable is controll ed by the bfte3 bit of the tmc0n register. (7) buffer registers cm00 to cm 02, cm04, cm05, cm10 to cm12, cm14, cm15 (bfcm00 to bfcm02, bfcm04, bfcm05, bfcm10 to bfcm12, bfcm14, bfcm15) bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 are 16-bit regist ers that transfer data to the compare register (cm0n0 to cm0n2, cm0n4, cm0n5) corresponding to each buffer register when an interrupt signal (intcm0n3/inttm0n) is generated. these registers can be read/written in 16-bit units. caution the set values of the bf cmn0 to bfcmn2, bfcmn4, and bf cmn5 registers are transferred to the cm0n0 to cm0n2, cm0n4, and cm0n5 registers at the foll owing timing (n = 0, 1). ? when tm0cen bit of tmc0n register = 0: transfer at the next operation timing after writing to the bfcmn0 to bfcmn2 , bfcmn4, and bfcmn5 registers ? when tm0cen bit of tmc0n register = 1: the value of the bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 registers is transferred to the cm0n0 to cm0n2, cm0n4, and cm0n5 registers upon occurrence of inttm0n or intcm0 n3. at this time, transfer enable or disable is controlled by the bften bit of the timer control register (tmc0n).
chapter 9 timer/counter function 203 user?s manual u15195ej5v0ud 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm00 address fffff572h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm10 address fffff5b2h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm01 address fffff574h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm11 address fffff5b4h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm02 address fffff576h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm12 address fffff5b6h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm04 address fffff59ch after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm14 address fffff5dch after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm05 address fffff59eh after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm15 address fffff5deh after reset ffffh
chapter 9 timer/counter function 204 user?s manual u15195ej5v0ud (8) buffer registers cm03, cm13 (bfcm03, bfcm13) bfcmn3 is a 16-bit register that trans fers data to the compare register at any timing. transfer enable or disable is controlled by the bfte3 bit of the tmc0n register. bfcmn3 can be read/written in 16-bit units. cautions 1. the set value of the bfcmn3 register is transferred to the cm0n3 register at the following timing (n = 0, 1). ? when tm0cen bit of tmc0n register = 0: transfer at the next operation timing after writing to the bfcmn3 register ? when tm0cen bit of tmc0n register = 1: the value of the bfcmn3 register is transferred to the cm0n3 regi ster upon occurrence of inttm0n. at this time, transfer enable or disable is controlled by the bfte3 bi t of the timer control register (tmc0n). 2. setting the bfcmn3 register to 0000h is prohibited. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm03 address fffff578h after reset ffffh 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 bfcm13 address fffff5b8h after reset ffffh
chapter 9 timer/counter function 205 user?s manual u15195ej5v0ud 9.1.5 control registers (1) timer 0 clock selection register (prm01) the prm01 register is used to select the base clock (f clk ) of timer 0 (tm0n). it can be read/written in 8-bit or 1-bit units. caution always set this register before using the timer. 7 0 prm01 6 0 5 0 4 0 3 0 2 0 1 0 0 prm1 address fffff5d0h after reset 00h bit position bit name function 0 prm1 specifies the base clock (f clk ) of timer 0 (tm0n) (see figure 9-3 ). 0: f xx /2 1: f xx caution set f clk to 40 mhz or less. remark f xx : internal system clock figure 9-3. timer 00 and timer 01 clock timer 00 timer 01 prm1 f clk f xx /2 select f xx remarks 1. f xx : internal system clock 2. f clk : base clock
chapter 9 timer/counter function 206 user?s manual u15195ej5v0ud (2) timer control registers 00, 01 (tmc00, tmc01) tmc0n is a 16-bit register that sets the operation of timer 0 (tm0n). the tmc0n register can be read/ written in 16-bit units. if the higher 8 bits of the tmc0n register are used as the tmc0nh register and the lower 8 bits as the tmc0nl register, the register can be read/ written in 8-bit or 1-bit units. caution to operate timer 0, first set tm0c en = 0 and then set tm0cen = 1. (1/4) <14> stint0 13 cul02 12 cul01 2 mbfte 3 bften 4 bfte3 <5> tm0ced0 6 0 7 0 8 prm00 9 prm01 10 prm02 11 cul00 <15> tm0ce0 1 mod01 0 mod00 tmc00 address fffff57ah after reset 0508h <14> stint1 13 cul02 12 cul01 2 mbfte 3 bften 4 bfte3 <5> tm0ced1 6 0 7 0 8 prm00 9 prm01 10 prm02 11 cul00 <15> tm0ce1 1 mod01 0 mod00 tmc01 address fffff5bah after reset 0508h bit position bit name function 15 tm0cen specifies the operation of tm0n. 0: count disabled (stops afte r all count values are cleared) 1: count enabled caution when tm0cen = 0, to0n0 to to0n5 output becomes high impedance. 14 stintn specifies interrupt during tm0n timer start. 0: interrupt not generated at operation start 1: interrupt generated at operation start when stintn = 1, an interrupt is generat ed immediately after the rising edge of the tm0cen signal. when mod01 = 0 (triangular wave mode), the inttm0n interrupt (see figure 9-4 ) is generated, and when mod01 = 1 (sawtooth wave mode), the intcm0n3 interrupt is generated. cautions 1. changing the stintn bit during tm0n operation (tm0cen bit = 1) is prohibited. 2. the intcm010 to intcm012, intcm0n4, and intcm0n5 interrupts are not affected by the stintn bit (an interrupt does not occur when the timer is started if stintn = 1). specifies the interrupt culling ratio. cul02 cul01 cul00 interrupt culling ratio 0 0 0 1/1 0 0 1 1/2 0 1 0 1/4 0 1 1 1/8 1 0 0 1/16 other than above culling not performed 13 to 11 cul02 to cul00 remark n = 0, 1
chapter 9 timer/counter function 207 user?s manual u15195ej5v0ud (2/4) bit position bit name function 13 to 11 cul02 to cul00 cautions 1. the inttm0n and intcm0n3 interrupts can be culled at the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. even when bfte3 = 1, bften = 1 (settings to transfer data from the bfcmn0 to bfcmn3 registers to the cm0n0 to cm0n3 registers), transfer is not performed at the generation timing of the culled inttm0n and intcm0n3 interrupts if mbfte = 0. 3. if the culling ratio is changed during a count operation, the new culling ratio is applied after an interrupt has occurred at the culling ratio prior to the change (see figure 9-5) . 4. the intcm010 to intcm012, intcm0n4, and intcm0n5 interrupts are not affected by the cul02 to cul00 bits (the interrupts occur each time at the same culling ratio as when cul02 to cul00 = 000 (1/1)). specifies the count clock for tm0n. prm02 prm01 prm00 count clock 0 0 0 f clk 0 0 1 f clk /2 0 1 0 f clk /4 0 1 1 f clk /8 1 0 0 f clk /16 1 0 1 f clk /32 other than above setting prohibited 10 to 8 prm02 to prm00 caution the division ratio switch timing is from when the tm0n value has become 0000h and the inttm0n interrupt has occurred. therefore, the division ratio is not switched at the timing that corresponds to interrupt culling. remark for the base clock (f clk ), see 9.1.5 (1) timer 0 clock selection register (prm01) . 5 tm0cedn specifies the operation of the dtmn0 to dtmn2 timers.. 0: dtmn0 to dtmn2 perform count operation 1: dtmn0 to dtmn2 stopped cautions 1. changing the tm0cedn bit during tm0n operation (tm0cen = 1) is prohibited. 2. if tm0n is operated when tm0cedn = 1, a signal without dead time is output to the to0n0 to to0n5 pins. remark n = 0, 1
chapter 9 timer/counter function 208 user?s manual u15195ej5v0ud (3/4) bit position bit name function specifies transfer of data from the bf cmn3 register to the cm0n3 register. 0: transfer disabled 1: transfer enabled the transfer timing from the bfcmn3 regist er to the cm0n3 register is as follows. bfte3 tm0n operation mode bfcmn3 cm0n3 transfer timing 0 all modes no transfer 1 pwm mode 0 (symmetric triangular wave) inttm0n 1 pwm mode 1 (asymmetric triangular wave) inttm0n 1 pwm mode 2 (sawtooth wave) intcm0n3 4 bfte3 when bfte3 = 1, the value of the bfcm n3 register is transferred to the cm0n3 register upon occurrence of the inttm0n or intcm0n3 interrupt. specifies transfer of data from the bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 registers to the cm0n0 to cm 0n2, cm0n4, cm0n5 registers. 0: transfer disabled 1: transfer enabled bften tm0n operation mode bfcmn0 to bfcmn2, bfcmn4, bfcmn5 cm0n0 to cm0n2, cm0n4, cm0n5 transfer timing 0 all modes don?t transfer 1 pwm mode 0 (symmetric triangular wave) inttm0n 1 pwm mode 1 (asymmetric triangular wave) inttm0n, intcm0n3 1 pwm mode 2 (sawtooth wave) intcm0n3 3 bften when bften = 1, the values of the bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 registers are transferred to the cm0n0 to cm0n2, cm0n4, and cm0n5 registers upon occurrence of the inttm0n or intcm0n3 interrupt. when culling of the inttm0n and intcm0n3 interrupts is set by the cul02 to cul00 bits, this bit specifies whether to enable or disable the bfte3 and bften bit settings upon occurrence of an interrupt for culling. 0: disable the set values of the bfte3 and bften bits upon occurrence of a culling interrupt 1: enable the set values of the bfte3aand bften bits upon occurrence of a culling interrupt the various combinations are as follows. operation upon occurrence of interrupt for culling mbfte 0 1 0 bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bften 1 bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer disabled bfcmn0 to bfcmn2 cm0n0 to cm0n2 transfer enabled 0 bfcmn3 cm0n3 transfer disabled bfcmn3 cm0n3 transfer disabled bfte3 1 bfcmn3 cm0n3 transfer disabled bfcmn3 cm0n3 transfer enabled 2 mbfte . remark n = 0, 1
chapter 9 timer/counter function 209 user?s manual u15195ej5v0ud (4/4) bit position bit name function specifies the operation mode of tm0n. mod 01 mod 00 operation mode tm0n operation timer clear source bfcmn3 cm0n3 timing bfcmn0 to bfcmn2, bfcmn4, bfcmn5 cm0n0 to cm0n2, cm0n4, cm0n5 timing 0 0 pwm mode 0 (symmetric triangular wave) up/down ? inttm0n inttm0n 0 1 pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n inttm0n, intcm0n3 1 0 pwm mode 2 (sawtooth wave) up intcm0n3 intcm0n3 intcm0n3 1 1 setting prohibited 1, 0 mod01, mod00 caution changing the value of the mod01 and mod00 bits during tm0n operation (tm0cen bit = 1) is prohibited. remark n = 0, 1 figure 9-4. specification of inttm0n interrupt in pwm mode 0 (sy mmetric triangular wave), pwm mode 1 (asymmetric triangular wave) (mod 01, mod00 bits of tmc0n register = 0n) cm0n3 tm0n count value 0000h tm0cen specification from occurrence of inttm0n at first start after reset is possible using stintn bit inttm0n occurrence can be specified using stintn bit inttm0n occurrence inttm0n occurrence timer operation stopped remark n = 0, 1
chapter 9 timer/counter function 210 user?s manual u15195ej5v0ud figure 9-5. interrupt culling processing (a) pwm mode 0 (symmetric triangular wave) cm0n3 tm0n count value 0000h cul02 to cul00 inttm0n occurrence interrupt request interrupt culling 1/1 cycle interrupt culling 1/2 cycle inttm0n occurrence inttm0n occurrence inttm0n occurrence 000 001 remark n = 0, 1 (b) pwm mode 1 (asymmetric triangular wave) cm0n3 tm0n count value 0000h cul02 to cul00 inttm0n occurrence intcm0n3 occurrence interrupt request intcm0n3 occurrence intcm0n3 occurrence intcm0n3 occurrence inttm0n occurrence interrupt culling 1/1 cycle interrupt culling 1/2 cycle inttm0n occurrence inttm0n occurrence 000 001 remark n = 0, 1 (c) pwm mode 2 (sawtooth wave) cm0n3 tm0n count value 0000h cul02 to cul00 intcm0n3 occurrence interrupt request intcm0n3 occurrence interrupt culling 1/1 cycle interrupt culling 1/2 cycle intcm0n3 occurrence intcm0n3 occurrence 000 001 remark n = 0, 1
chapter 9 timer/counter function 211 user?s manual u15195ej5v0ud figure 9-6. interrupt culling ratio change timing (relationship between stintn bit se tting and cul bit change): pwm mode 1 (asymmetric triangular wave) inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 intcm0n3 000 001 010 interrupt culling 1/1 cycle interrupt culling 1/2 cycle interrupt culling 1/4 cycle tm0cen bit tm0n count value cul02 to cul00 bits stintn = 1 inttm0n inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 inttm0n intcm0n3 inttm0n intcm0n3 intcm0n3 001 010 000 interrupt culling 1/2 cycle interrupt culling 1/4 cycle interrupt culling 1/1 cycle tm0cen bit tm0n count value cul02 to cul00 bits stintn = 1 inttm0n inttm0n inttm0n inttm0n intcm0n3 intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n intcm0n3 inttm0n intcm0n3 intcm0n3 001 010 000 interrupt culling 1/2 cycle interrupt culling 1/4 cycle interrupt culling 1/1 cycle tm0cen bit tm0n count value cm0n3 0000h cm0n3 0000h cm0n3 0000h cul02 to cul00 bits stintn = 1 caution if, in tm0n, to realize the inttm0n and intc m0n3 culling function, the culling ratio is set to a value other than 1/1 by bits cul 02 to cul00 and counting is star ted, the subsequent interrupt output sequence will differ due to the set value of the stintn bit at count start. remark n = 0, 1
chapter 9 timer/counter function 212 user?s manual u15195ej5v0ud (3) timer unit control regist ers 00, 01 (tuc00, tuc01) tuc0n is an 8-bit register that c ontrols the to0n0 to to0n5 outputs. tuc0n can be read/written in 8-bit or 1-bit units. however, bit 0 is read-only. 7 0 tuc00 6 0 5 0 4 0 3 0 2 0 <1> tors0 <0> tosta0 address fffff57ch after reset 01h 7 0 tuc01 6 0 5 0 4 0 3 0 2 0 <1> tors1 <0> tosta1 address fffff5bch after reset 01h bit position bit name function 1 torsn flag that restarts to0n0 to to0n5 pin outputs that were forcibly stopped by eson pin input. output is resumed by writing ?1? to the torsn bit. cautions 1. if the level is set to the eson pin input level (tomr register toedg1 bit = 1, toedg0 bit = 0 or 1), the output disabled state is not released (tostan bit = 1) even if ?1? is written to the torsn bit while output is disabled (tostan bit = 1). if the input level is the inactive level, the output disabled state is released (tostan bit = 0). 2. if the edge is set to the eson pin input (toedg1 bit = 0, toedg0 bit = 0 or 1), the output disabled state is released (tostan bit = 0) when ?1? is written to the torsn bit while output is disabled (tostan bit = 1). 3. after reset, be sure to write ?1? to the torsn bit prior to starting to0n0 to to0n5 output. ?0? is read when the torsn bit is read. 0 tostan flag indicating to0n0 to to0n5 pin out put status according to es0n pin input 0: output enabled status 1: output disabled status remark n = 0, 1
chapter 9 timer/counter function 213 user?s manual u15195ej5v0ud (4) timer output mode registers 0, 1 (tomr0, tomr1) the tomrn register controls timer out put from the to0n0 to to0n5 pins. to prevent abnormal output from t he to0n0 to to0n5 pins due to illegal access, data is written to the tomrn register in the following two sequences. (a) write access to the tomr write enable register (specn), followed by (b) write access to the tomrn register write is not enabled via hardware unless these two sequences are implemented. tomrn can be read/written in 8-bit units. caution when interrupt requests are generated dur ing write access to the tomrn register (after write access to the specn register and prior to writing to the tomrn register), write processing to the tomrn register may not be performed normally if access to other addresses is performed using th e internal bus during servici ng of these interrupts. add one of the following processing items during the tomrn register write routine. ? prior to write access to the tomrn register , disable acknowledgment of all interrupts of the cpu. ? following write access to the to mrn register, check that writ e was performed normally. (1/2) 7 alvto tomr0 6 alvub 5 alvvb 4 alvwb 3 tosp 2 0 1 toedg1 0 toedg0 address fffff57dh after reset 00h 7 alvto tomr1 6 alvub 5 alvvb 4 alvwb 3 tosp 2 0 1 toedg1 0 toedg0 address fffff5bdh after reset 00h bit position bit name function 7 alvto specifies the active level of the to0n0, to0n2, and to0n4 pins. 0: active level is low level 1: active level is high level caution changing the alvto bit during tm0n operation (tm0cen = 1) is prohibited. 6 alvub specifies the output level of the to0n1 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when alvub = 1, the output level of to0n1 output is the same as to0n0. caution changing the alvub bit during tm0n operation (tm0cen = 1) is prohibited. remark n = 0, 1
chapter 9 timer/counter function 214 user?s manual u15195ej5v0ud (2/2) bit position bit name function 5 alvvb specifies the output level of the to0n3 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when alvvb = 1, the output level of to0n3 output is the same as to0n2. caution changing the alvvb bit during tm0n operation (tm0cen = 1) is prohibited 4 alvwb specifies the output level of the to0n5 pin. 0: inverted level of active level set by alvto bit 1: active level set by alvto bit when alvwb = 1, the output level of to0n5 output is the same as to0n4. caution changing the alvwb bit during tm0n operation (tm0cen = 1) is prohibited. 3 tosp controls to0n0 to to0n5 pin output stop via eson pin input. 0: enables eson pin input 1: disables eson pin input cautions 1. the output st op status can be released by writing ?1? to the torsn bit of the tuc0n register. the operation continues even if output is prohibited for all timers and counters. 2. before changing the eson pin input status from disabled to enabled (changing the tosp bit from 1 to 0), write ?1? to the torsn bit of the tucn register to reset the eson pin input status. these bits select the valid edge or level when setting forcible stop of to0n0 to to0n5 output via eson pin input using the tosp bit. toedg1 toedg0 operation 0 0 rising edge 0 1 falling edge 1 0 low level 1 1 high level 1, 0 toedg1, toedg0 cautions 1. changing the toedg1 and toedg0 bits during tm0n operation (tm0cen = 1) is prohibited. 2. before changing the settings of bits toedg1 and toedg0, write ?1? to the torsn bit of the tuc0n register to reset the eson pin input status. remark n = 0, 1
chapter 9 timer/counter function 215 user?s manual u15195ej5v0ud examples of the output waveforms of to000 and to00 1 when the higher 4 bits (alvto, alvub, alvvb, and alvwb) of the tomrn register are set in pwm mode 0 (asymmetric triangular waves) are shown below. figure 9-7. output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (without dead time (tm0ced0 bit = 1)) (a) tomr0 register value = 80h tm00 = cm000 to000 to001 tm00 = cm000 (b) tomr0 register value = 00h tm00 = cm000 to000 to001 tm00 = cm000 (c) tomr0 register value = c0h tm00 = cm000 to000 to001 tm00 = cm000 (d) tomr0 register value = 40h tm00 = cm000 to000 to001 tm00 = cm000
chapter 9 timer/counter function 216 user?s manual u15195ej5v0ud figure 9-8. output waveforms of to000 and to001 in pwm mode 0 (symmetric triangular waves) (with dead time (tm0ced0 bit = 0)) (a) tomr0 register value = 80h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (b) tomr0 register value = 00h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (c) tomr0 register value = c0h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period (d) tomr0 register value = 40h tm00 = cm000 to000 to001 tm00 = cm000 dead time period dead time period
chapter 9 timer/counter function 217 user?s manual u15195ej5v0ud data is set to timer output mode registers 0 and 1 (tomr0, tomr1) in the following sequence. <1> prepare the data to be set to timer output mode registers 0 and 1 (tomr0, tomr1) in a general-purpose register. <2> write data to tomr write enable registers 0 and 1 (sepc0, spec1). <3> set timer output mode registers 0 and 1 (tomr0, tomr1) (using the following instructions). ? store instruction (st/sst instructions) ? bit manipulation instruction (set1/clr1/not1 instructions) [description example] <1> mov 0x04, r10 <2> st.b r10, specn [r0] <3> st.b r10, tomrn [r0] remark n = 0, 1 to read the tomrn register, no s pecial sequence is required. cautions 1. prohibit interrupts between specn issuance (<2>) and th e tomrn register write that immediately follows (<3>). 2. the data written to the specn register is dummy data; use the same register as the general- purpose register used to set the tomrn regi ster (<3> in the ab ove example) for specn register write (<2> in the above example). the same applies when using a general-purpose register for addressing. 3. do not write to the specn register or tomrn register using dma transfer.
chapter 9 timer/counter function 218 user?s manual u15195ej5v0ud (5) pwm output enable regist ers 0, 1 (poer0, poer1) the poern register is used to make the external pulse output (to0n0 to to0n5) status inactive by software. poern can be read/written in 8-bit or 1-bit units. 7 0 poer0 6 0 <5> oe210 <4> oe200 <3> oe110 <2> oe100 <1> oe010 <0> oe000 address fffff57fh after reset 00h 7 0 poer1 6 0 <5> oe211 <4> oe201 <3> oe111 <2> oe101 <1> oe011 <0> oe001 address fffff5bfh after reset 00h bit position bit name function 5 oe21n specifies the output status of the to0n5 pin. 0: to0n5 output status is high impedance. 1: to0n5 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 4 oe20n specifies the output status of the to0n4 pin. 0: to0n4 output status is high impedance. 1: to0n4 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 3 oe11n specifies the output status of the to0n3 pin. 0: to0n3 output status is high impedance. 1: to0n3 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 2 oe10n specifies the output status of the to0n2 pin. 0: to0n2 output status is high impedance. 1: to0n2 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 1 oe01n specifies the output status of the to0n1 pin. 0: to0n1 output status is high impedance. 1: to0n1 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. 0 oe00n specifies the output status of the to0n0 pin. 0: to0n0 output status is high impedance. 1: to0n0 output status is controlled by tm0cen bit of tmc0n register and torton bit of pston register and eson pin. remark n = 0, 1
chapter 9 timer/counter function 219 user?s manual u15195ej5v0ud (6) pwm software timing output regi sters 0, 1 (psto0, psto1) the pston register is used to perform settings to output the desired waveforms to the external pulse output pins (to0n0 to to0n5) by software. pston can be read/written in 8-bit or 1-bit units. cautions 1. when the value of the torton bit has been changed from 0 to 1 during timer output (setting changed to software output), the ti ming is delayed by the dead-time portion when the output level differ s from the timer output signa l during output due to the settings of the uportn, vportn, and wportn bits. when the output level is the same as th e timer output signal dur ing output due to the settings of the uportn, vportn, and wpor tn bits, output is pe rformed maintaining the same output level. 2. if software output is enabled (torton bit = 1), the inttm0n a nd intcm0n3 interrupts and to0n0 to to0n5 output statuses are as follows during tm0n operation (tm0cen bit = 1). inttm0n and intcm0n3 interrupts: cont inue occurring at each timing in accordance with timer and compare operations. to0n0 to to0n5 outputs: software output has priority. 3. if the torton bit is changed from 1 to 0 during tm0n operation (tm0cen bit = 1), the software output state is retained for the to0n0 to to0n5 outputs until one of the set/reset condition of the flip-flop for the to 0n0 to to0n5 outputs shown in (a) below is generated. (a) set/reset conditions of flip-flop for to0n0 to to0n5 outputs output status operation mode conditions triangular wave mode (pwm mode 0, 1) compare match while tm0n is counting up timer output sawtooth wave mode (pwm mode 2) match between tm0n and cm0n3 registers set software output ? set (to 1) uportn, vportn, and wportn bits triangular wave mode (pwm mode 0, 1) compare match while tm0n is counting down timer output sawtooth wave mode (pwm mode 2) compare match with tm0n reset software output ? clear (to 0) uportn, vportn, and wportn bits remark n = 0, 1 4. if the same value is written to the up ortn (vportn, wportn) bit when torton =1, the to0n0 and to0n1 outputs (to0n2 and to 0n3, to0n4 and to0n5) are not changed.
chapter 9 timer/counter function 220 user?s manual u15195ej5v0ud (1/2) <7> torto0 psto0 6 0 5 0 4 0 3 0 <2> uport0 <1> vport0 <0> wport0 address fffff57eh after reset 00h <7> torto1 psto1 6 0 5 0 4 0 3 0 <2> uport1 <1> vport1 <0> wport1 address fffff5beh after reset 00h bit position bit name function 7 torton specifies to0n0 to to0n5 output control. 0: timer output 1: software output the change of the to0n0 to to0n5 signals during software output occurs when the torton bit is set (to 1) and a value is written to the uportn, vportn, and wportn bits. a dead-time timer can also be used. 2 uportn specifies the to0n0 (u phase)/to0n1 (u phase) pin output value. caution if the uportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n0/to0n1 output signal in the same way as during normal timer operation. 1 vportn specifies the to0n2 (v phase)/to0n3 (v phase) pin output value. caution if the vportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n2/to0n3 output signal in the same way as during normal timer operation. remark n = 0, 1 alvto bit: bit 7 of the tomrn register alvub bit: bit 6 of the tomrn register alvvb bit: bit 5 of the tomrn register uportn operation to0n0 inverted level of alvto bit setting when alvub = 0 level of alvto bit setting 0 to0n1 when alvub = 1 inverted level of alvto bit setting to0n0 level of alvto bit setting when alvub = 0 inverted level of alvto bit setting 1 to0n1 when alvub = 1 level of alvto bit setting vportn operation to0n2 inverted level of alvto bit setting when alvvb = 0 level of alvto bit setting 0 to0n3 when alvvb = 1 inverted level of alvto bit setting to0n2 level of alvto bit setting when alvvb = 0 inverted level of alvto bit setting 1 to0n3 when alvvb = 1 level of alvto bit setting
chapter 9 timer/counter function 221 user?s manual u15195ej5v0ud (2/2) bit position bit name function 0 wportn specifies the to0n4 (w phase )/to0n5 (w phase) pin output value. caution if the wportn bit setting value is changed when torton = 1, the dead-time setting becomes valid for the to0n4/to0n5 output signal in the same way as during normal timer operation. remark n = 0, 1 alvto bit: bit 7 of the tomrn register alvwb bit: bit 4 of the tomrn register the to0n0 to to0n5 pins can be set to timer output by a match between tm0n and the compare register or to software output using the pston register (torton bit = 1). software output has the priority over timer output. consequently, when the setting changes from tm0cen = 1 (timer operation enabled), torton = 1 (software output enabled) to tm0cen = 1 (timer operation enabled), torton = 0 (software output disabled), the to0n0 to to0n5 pins continue to perform software output until the occurrence of the firs t f/f set/reset due to a match between tm0n and the compare register after the torton bit setting changes. the relationship between th e settings of the torton and tm0cen bits when alvto = 1 and the output of to0n0 (negative phase side) is shown on the following pages (the positive phase side (to 0n1, to0n3, and to0n5) is dependent on the alvub, alvvb, and alvwb bits, so refe r to the explanations of each of these bits). wportn operation to0n4 inverted level of alvto bit setting when alvwb = 0 level of alvto bit setting 0 to0n5 when alvwb = 1 inverted level of alvto bit setting to0n4 inverted level of alvto bit setting when alvwb = 0 inverted level of alvto bit setting 1 to0n5 when alvwb = 1 level of alvto bit setting
chapter 9 timer/counter function 222 user?s manual u15195ej5v0ud figure 9-9. when uportn = 1 is set immediately before torton = 0 (switched by active value) cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output note 1 note 2 note 3 software output timer output p1 t1 cm0n3 cm0n3 cm0n3 note 2 note 2 note 1 note 4 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 1 to 0 while the uportn bit is set to 1 in the p1 period in figure 9-9 above, the f/f continues to hold the tort on bit setting of ?1? until the t1 timing. however, because the f/f is reset at the t1 timing (by a compare match of tm0n during down counting), the to0n0 output changes from 1 to 0.
chapter 9 timer/counter function 223 user?s manual u15195ej5v0ud figure 9-10. when uportn = 0 is set immediately before torton = 0 (switched by inactive value) cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output note 1 note 3 software output timer output p1 t2 cm0n3 cm0n3 cm0n3 note 2 note 1 note 2 note 4 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 1 to 0 while the uportn bit is set to 0 in the p1 period in figure 9- 10 above, the f/f continues to hold the torton bit setting of ?0? until the t2 timing. however, because the f/f is set at the t2 timing (by a compare match of tm0n during up counting), the to0n0 output changes from 1 to 0. note that to0n0 to to0n5 output will st op if the torton bit setting is changed from 1 to 0 while the tm0cen bit is 0.
chapter 9 timer/counter function 224 user?s manual u15195ej5v0ud figure 9-11. when uportn = 0 is se t immediately before torton = 1 cm0n3 0000h tm0n count value f/f intcm0n3 inttm0n to0n0 tm0cen torton uportn timer output software output timer output t3 cm0n3 cm0n3 cm0n3 note 2 note 1 note 1 note 2 note 1 note 4 note 3 notes 1. f/f set by compare match during up count 2. f/f reset by compare match during down count 3. f/f set by writing uportn bit 4. f/f reset by writing uportn bit remark n = 0, 1 if the setting of the torton bit changes from 0 to 1 while the uportn bit is set to 0 during tm0n operation (tm0cen = 1), the to0n0 output changes from 1 to 0 because the f/f is reset at the t3 timing. examples of the software output waveforms of to 000 and to001 based on the settings of the torton, uportn, vportn, and wportn bits are shown on the following pages.
chapter 9 timer/counter function 225 user?s manual u15195ej5v0ud figure 9-12. software output w aveforms of to000 and to001 (without dead time (tm0ced0 = 1)) (a) tomr0 register value = 80h uport0 1 to000 to001 uport0 0 (b) tomr0 register value = 00h uport0 1 to000 to001 uport0 0 (c) tomr0 register value = c0h uport0 1 to000 to001 uport0 0 (d) tomr0 register value = 40h uport0 1 to000 to001 uport0 0
chapter 9 timer/counter function 226 user?s manual u15195ej5v0ud figure 9-13. software output waveforms of to 000 and to001 (with dead time (tm0ced0 = 0)) (a) tomr0 register value = 80h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (b) tomr0 register value = 00h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (c) tomr0 register value = c0h uport0 1 to000 to001 uport0 0 dead-time period dead-time period (d) tomr0 register value = 40h uport0 1 to000 to001 uport0 0 dead-time period dead-time period
chapter 9 timer/counter function 227 user?s manual u15195ej5v0ud figure 9-14. software output wavef orms of to000 and to001 when ?1? is written to uport0 bit while torto0 = 1 (when tomr0 register value = 80h) (a) without dead ti me (tm0ced0 = 1) uport0 1 uport0 0 uport0 1 to000 to001 (b) with dead time (tm0ced0 = 0) uport0 1 uport0 0 uport0 1 to000 to001 dead-time period dead-time period the following table shows the output status of external pulse out put (in the case of to0n0). table 9-3. output status of extern al pulse output (in case of to0n0) oe00n bit torton, uportn bits tm0cen bit to0n0 0 0/1 0/1 high impedance 0 high impedance 0 1 timer output 1 1 0/1 output by uportn bit remarks 1. oe00n bit: bit 0 of poern register torton bit: bit 7 of pston register uportn bit: bit 2 of pston register tm0cen bit: bit 15 of tmc0n register 2. n = 0, 1
chapter 9 timer/counter function 228 user?s manual u15195ej5v0ud (7) tomr write enable registers 0, 1 (spec0, spec1) the specn register enabl es writing to the tomrn r egister. unless writing to the tomrn register is performed immediately after writing to the specn regist er (any data can be written), write processing to the tomrn register is not performed normally. normally, 0000h is read. the specn register can be read/written in 16-bit units. remark n = 0, 1 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 spec0 address fffff580h after reset 0000h 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 spec1 address fffff5c0h after reset 0000h
chapter 9 timer/counter function 229 user?s manual u15195ej5v0ud 9.1.6 operation remarks 1. in the explanation of operations in this section, the bits that affect the to0n0 to to0n5 outputs are assumed to be set as follows. alvto = 1, alvub = 0, al vvb = 0, alvwb = 0, torton =0 2. the f/f in this section indicates the flip-flop for controlling the output of the to0n0 to to0n5 pins. (1) basic operation timer 0 (tm0n) is a 16-bit interval timer that operates as an up/down timer or as an up timer. the cycle is controlled by compare register 0n3 (cm0n3) (n = 0, 1). all tm0n bits are cleared (0) by reset i nput and the count operation is stopped. count operation enable/disable is controlled by the tm 0cen bit of timer control register 0n (tmc0n). the count operation is started by setting the tm0cen bit to 1 by software. resetting the tm0cen bit to 0 clears tm0n and stops the count operation. when the value of compare register 0n3 (cm0n3) set beforehand and the value of the tm0n counter match, a match interrupt (intcm0n3) is generated. the count clock to tm0n can be selected from among 6 internal clocks using the tmc0n register. if tm0n has been set as an up/down timer, an underflow interrupt (inttm0n) is generated when tm0n becomes 0000h during down counting. tm0n has the following three operation modes, which are se lected using timer control register 0n (tmc0n). ? pwm mode 0: triangular wave modulation (right-left symmetric waveform control) ? pwm mode 1: triangular wave modulation (right-left asymmetric waveform control) ? pwm mode 2: sawtooth wave modulation control
chapter 9 timer/counter function 230 user?s manual u15195ej5v0ud table 9-4. operation modes of timer 0 (tm0n) tmc0n register mod01 mod00 operation mode tm0n operation timer clear source interrupt source bfcmn3 cm0n3 timing bfcmn0 to bfcmn2, bfcmn4, bfcmn5 cm0n0 to cm0n2, cm0n4, cm0n5 timing 0 0 pwm mode 0 (symmetric triangular wave) up/down ? inttm0n, intcm010 to intcm012, intcm0n3 to intcm0n5 inttm0n inttm0n 0 1 pwm mode 1 (asymmetric triangular wave) up/down ? inttm0n, intcm010 to intcm012, intcm0n3 to intcm0n5 inttm0n inttm0n, intcm0n3 1 0 pwm mode 2 (sawtooth wave) up intcm0n3 intcm010 to intcm012, intcm0n3 to intcm0n5 intcm0n3 intcm0n3 1 1 setting prohibited caution changing the mod01 and mod00 bits during tm0n operation (tm0cen = 1) is prohibited. remark n = 0, 1 the various operation modes are described below.
chapter 9 timer/counter function 231 user?s manual u15195ej5v0ud (2) pwm mode 0: triangular wave modulation (right-left sy mmetric waveform control) [setting procedure] (a) set pwm mode 0 (symmetric triangular wave) usin g the mod01 and mod00 bits of the tmc0n register. also set the active level of the to0n0 to to0n5 pins using the alvto bit of the tomrn register (n = 0, 1). (b) set the count clock of tm0n using the prm02 to prm00 bits of the tmc0n register. the transfer operation from bfcmn3 to cm0n3 is set using the b fte3 bit, and the transfer operation from bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 to cm0 n0 to cm0n2, cm0n4, and cm0n5 is set using the bften bit. (c) set the initial values. (i) specify the interrupt culling ratio using the cul 02 to cul00 bits of the tmc0n register. (ii) set the half-cycle width of the pwm cycle in bfcmn3. ? pwm cycle = bfcmn3 value 2 tm0n count clock (the tm0n count clock is set by the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set/reset timing of the f/f us ed in the pwm cycle in bfcmn0 to bfcmn2. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from the to0n0 to to0n5 pins. cautions 1. setting cm0n3 to 0000h is prohibited. 2. setting bfcmnx > bfcmn3 is prohibited when the tm0cen bit of the tmc0n register is 0 because the outputs of the to0n0 to to0n5 pins are the inverted levels of the settings (x = 0 to 2). also, setting bfcmnx > bfcmn3 is prohibited if the cm0nx register is 0 when the tm0cen bit of the tmc0n register. remark the tm0cen bit of the tmc0n register indi cates a transfer operation under the following conditions. ? when tm0cen bit of tmc0n register is 0 transfer to the cm0n0 to cm0n2, cm0n4, and cm 0n5 registers is performed at the next base clock (f clk ) after writing to the bfcmn0 to bfcm n2, bfcmn4, and bfcmn5 registers. ? when tm0cen bit of tmc0n register is 1 the value of the bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 regi sters is transferred to the cm0n0 to cm0n2, cm0n4, and cm0n5 registers upon occurrence of the inttm0n interrupt. transfer enable/disable at this time is controll ed by the bften bit of the tmc0n register.
chapter 9 timer/counter function 232 user?s manual u15195ej5v0ud [operation] in pwm mode 0, tm0n performs up/down count operat ion. when tm0n = 0000h during down counting, an underflow interrupt (inttm0n) is generated, and when tm0n = cm0n3 during up counting, a match interrupt (intcm0n3) is generated (n = 0, 1). switching from up counting to down counting is pe rformed when tm0n and cm0n3 match (intcm0n3), and switching from down counting to up counting is performed when a tm0n underflow occurs after tm0n becomes 0000h. the pwm cycle in this mode is (bfcmn3 value 2 tm0n count clock). note that the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is autom atically transferred by hardware to cm0n3 upon generation of the inttm0n interrupt. furthermore, calculation is performed by softw are processing started by inttm0n, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists of setti ng the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of the inttm0n interrupt. furthermore, so ftware processing is started up and calculation performed, and the set/reset timi ng of the f/f for the next cycle is set to bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: cm0n0 to cm0n2 match detection during tm0n up count operation ? reset: cm0n0 to cm0n2 match detection during tm0n down count operation in this mode, the f/f set/reset timing is performed at the same timing (right-left symmetric control). the values of dtrrn are transferred to the corresponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is started. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically generate a width at which the active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap (dead time). in this way, software processing is started by an in terrupt (inttm0n) that occurs once during every pwm cycle after initial setting has been performed, and by se tting the pwm cycle and pwm duty to be used in the next cycle, it is possible to autom atically output a pwm waveform to pins to0n0 to to0n5 taking into consideration the dead-time width (in the case of an interrupt culling ratio of 1/1).
chapter 9 timer/counter function 233 user?s manual u15195ej5v0ud [output waveform width with respect to set value] ? pwm cycle = bfcmn3 2 t tm0n ? dead-time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = { (cm0n3 ? cm0nx up ) + (cm0n3 ? cm0nx down ) } t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0nx down + cm0nx up ) t tm0n ? t dnm ? in this mode, cm0nx up = cm0nx down (however, within the same pwm cycle). since cm0nx up and cm0nx down in the negative phase formula are prepared in a separate pwm cycle, cm0nx up cm0nx down . f clk : base clock t tm0n : tm0n count clock cm0nx up : set value of cm0n0 to cm0n2 while tm0n is counting up cm0nx down : set value of cm0n0 to cm0n2 while tm0n is counting down the pin level when the to0n0 to to0n5 pins are reset is the high impedance state. when the control mode is selected thereafter, the following leve ls are output until tm0n is started. ? to0n0, to0n2, to0n4? when active low high level when active high low level ? to0n1, to0n3, to0n5? when active low low level when active high high level the active level is set with the alvto bit of the tomrn register. the default is active low. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value is set in the above form ula, the to0n0 to to 0n5 pins output a w aveform fixed to the inactive level waveform wit h active width ?0?. remarks. 1 m = 0 to 2 n = 0, 1 2. the interrupt request signal occurrence condi tions of intcm010 to intcm012, intcm0n4, and intcm0n5 are shown below. setting condition intcm010 to intcm012, intcm0n4, intcm0n5 signal occurrence status cm010 to cm012, cm0n4, cm0n5 cm0n3 occurs cm010 to cm012, cm0n4, cm0n5 = 0000h occurs cm010 to cm012, cm0n4, cm0n5 > cm0n3 does not occur
chapter 9 timer/counter function 234 user?s manual u15195ej5v0ud figure 9-15. operation timing in pwm m ode 0 (symmetric tr iangular wave) (1/2) (a) operation timing of compare regist ers 0n0 to 0n2 (cm0n0 to cm0n2) t t t t cm0n3 (d) cm0n3 (e) aa bb cm0nx match cm0nx match cm0nx match cm0nx match bc e a df b a ef d intcm0n3 intcm01x intcm01x intcm01x intcm01x inttm0n intcm0n3 inttm0n c tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx 0000h remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. to not use dead time, set the tm0cedn bit of the tmc0n register to 1. 6. the above figure shows an active-high case. 7. intcm01x is generated on a match between tm 01 and cm01x (a and b in the above figure). intcm00x is not generated. figure 9-16 shows the overall operation image.
chapter 9 timer/counter function 235 user?s manual u15195ej5v0ud figure 9-15. operation timing in pwm m ode 0 (symmetric tr iangular wave) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 (d) cm0n3 (e) aa bb cm0nx match cm0nx match cm0nx match cm0nx match bc e a df b a ef d intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx inttm0n intcm0n3 inttm0n c tm0n count value interrupt request bfcmnx bfcmn3 cm0n3 cm0nx 0000h remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 4, 5 4. intcm0nx is generated on a match between tm0n and cm0nx (a and b in the above figure). figure 9-16 shows the overall operation image.
chapter 9 timer/counter function 236 user?s manual u15195ej5v0ud figure 9-16. overall operation image of pwm mode 0 (symmetric triangular wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 cm0n3 cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 without dead time with dead time remark n = 0, 1
chapter 9 timer/counter function 237 user?s manual u15195ej5v0ud next, an example of the operation timing, which depe nds on the values set to cm0n0 to cm0n2, cm0n4, and cm0n5 (bfcmn0 to bfcmn2, bfcmn4, bfcmn5) is shown. (a) when cm0nx (bfcmnx) cm0n3 is set figure 9-17. operation timing in pwm mode 0 (symmetric triangular wave, bfcmnx cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match (bfcmnx = cm0n3) bfcmnx cm0n3 bfcmnx cm0n3 a bfcmnx cm0n3 a inttm0n intcm0n3 intcm01x intcm01x intcm01x (bfcm1x = cm013) intcm0n3 inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h t t positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) dtmnx f/f remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 238 user?s manual u15195ej5v0ud figure 9-17. operation timing in pwm mode 0 (symmetric triangular wave, bfcmnx cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match (bfcmnx = cm0n3) bfcmnx cm0n3 bfcmnx cm0n3 a bfcmnx cm0n3 a inttm0n intcm0n3 intcm0nx intcm0nx intcm0nx (bfcmnx = cm0n3) intcm0n3 inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). when a value greater than cm0n3 is set to bfcm n0 to bfcmn2, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a low level, and the negative phase side (to 0n1, to0n3, to0n5 pins) continues to output a high level. this feature is effective for outputting a low-level or high-level width exceeding the pwm cycle in an application such as in verter control. furthermore, if cm0n0 to cm0n2 = cm0n3 is set, matching of tm0n and cm0n0 to cm0n2 is detected during down counting by tm0n, so that the f/f remains reset as is, and is not set. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same.
chapter 9 timer/counter function 239 user?s manual u15195ej5v0ud (b) when cm0nx (bfcmnx) = 0000h is set figure 9-18. operation timing in pwm mode 0 (s ymmetric triangular wave, bfcmnx = 0000h) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match 0000h 0000h a 0000h a inttm0n inttm0n intcm0n3 intcm0n3 intcm01x intcm01x intcm01x intcm01x tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h cm0nx match remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 240 user?s manual u15195ej5v0ud figure 9-18. operation timing in pwm mode 0 (s ymmetric triangular wave, bfcmnx = 0000h) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match 0000h 0000h a 0000h a inttm0n inttm0n intcm0n3 intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx tm0n count value bfcmnx interrupt request cm0nx 0000h cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). since tm0n = cm0n0 to cm0n2 = 0000h match is detec ted during up counting by tm0n, the f/f is just set and does not get reset. even when the setting value is 0000h, f/ f is changed in the cycle during which transfer is performed from bfcmn0 to bfcmn2 to cm0n0 to cm0n2 similarly to when the setting value is other than 0000h. figure 9-19 shows the change timing from the 100% duty state.
chapter 9 timer/counter function 241 user?s manual u15195ej5v0ud figure 9-19. change timing from 100% duty state (pwm mode 0) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 tm0n count value bfcm0nx cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) 0000h 0000h b c a a 0000h 0000h note b cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match cm0n3 bb cm0nx match cm0nx match cm0nx match t t t t t t inttm0n intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm01x intcm01x intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm 01 and cm01x (a and b in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 242 user?s manual u15195ej5v0ud figure 9-19. change timing from 100% duty state (pwm mode 0) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 tm0n count value bfcm0nx cm0nx interrupt request 0000h 0000h b c a a 0000h 0000h b cm0n3 cm0n3 aa cm0nx match cm0nx match cm0nx match cm0n3 bb cm0nx match cm0nx match cm0nx match inttm0n intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a and b in the above figure).
chapter 9 timer/counter function 243 user?s manual u15195ej5v0ud (3) pwm mode 1: triangular wave modulation (right-left asy mmetric waveform control) [setting procedure] (a) set pwm mode 1 (asymmetric triangular wave) using the mod01 and mod0 0 bits of the tmc0n register. also set the active level of the to0n0 to to0n5 pins using the alvto bit of the tomrn register (n = 0, 1). (b) set the count clock of tm0n using the prm02 to prm00 bits of the tmc0n register. the transfer operation from bfcmn3 to cm0n3 is set using the b fte3 bit, and the transfer operation from bfcmn0 to bfcmn2, bfcmn4, bfcmn5 to cm0n0 to cm0n2, cm0n4, and cm0n5 is set using the bften bit. (c) set the initial values. (i) specify the interrupt culling ratio using the cul02 to cul00 bits of the tmc0n register. (ii) set the half-cycle width of the pwm cycle in bfcmn3. ? pwm cycle = bfcmn3 value 2 tm0n count clock (the tm0n count clock is set by the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set timing of the f/f used in the pwm cycle in bfcmn0 to bfcmn2, bfcmn4, and bfcmn5. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from the to0n0 to to0n5 pins. caution setting cm0n3 to 0000h is prohibited. remark the tm0cen bit of the tmc0n register indicates transfer operation under the following conditions. ? when tm0cen bit of tmc0n register is 0 transfer to the cm0n0 to cm0n2, cm0n4, and cm 0n5 registers is performed at the next base clock (f clk ) after writing to the bfcmn0 to bfcm n2, bfcmn4, and bfcmn5 registers. ? when tm0cen bit of tmc0n register is 1 the value of the bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 regi sters is transferred to the cm0n0 to cm0n2, cm0n4, and cm0n5 regist ers upon occurrence of the inttm0n or intcm0n3 interrupt. transfer enable/disable at this time is controlled by the bften bit of the tmc0n register.
chapter 9 timer/counter function 244 user?s manual u15195ej5v0ud [operation] in pwm mode 1, tm0n performs up/down count operat ion. when tm0n = 0000h during down counting, an underflow interrupt (inttm0n) is generated, and when tm0n = cm0n3 during up counting, a match interrupt (intcm0n3) is generated (n = 0, 1). switching from up counting to down counting is pe rformed when tm0n and cm0n3 match (intcm0n3), and switching from down counting to up c ounting is performed by inttm0n. the pwm cycle in this mode is (bfcmn3 value 2 tm0n count clock). note that the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is autom atically transferred by hardware to cm0n3 upon generation of the inttm0n interrupt. furthermore, calculation is performed by softw are processing started by inttm0n, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists of se tting the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of inttm0n and intcm0n3 (tm0n and cm 0n3 match interrupts). furthermore, software processing is started up and calculation performed, and the set/reset timing of t he f/f after a half cycle is set in bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: cm0n0 to cm0n2 match detection during tm0n up count operation ? reset: cm0n0 to cm0n2 match detection during tm0n down count operation the values of dtrrn are transferred to the corres ponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is started. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically generate a width at which the active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap (dead time). in this way, software processing is started by tw o interrupts (inttm0n and intcm0n3) that occur during every pwm cycle after initial setting has been perform ed, and by setting the pwm cycle and pwm duty to be used after a half cycle, it is possible to automatically output a pwm waveform to pi ns to0n0 to to0n5 taking into consideration the dead-time width (in the ca se of an interrupt culling ratio of 1/1). the difference between right-left symmetric waveform contro l and control in this mode (right-left asymmetric waveform control) is that bfcmn0 to bfcmn2 are trans ferred to cm0n0 to cm0n2, and that the interrupt signals that start software processi ng consist just of inttm0n (generated once per pwm cycle) in the case of right-left symmetric waveform control, and inttm0n and intcm0n3 (generated twice per pwm cycle, or once per half cycle) in the case of right -left asymmetric waveform control.
chapter 9 timer/counter function 245 user?s manual u15195ej5v0ud [output waveform width with respect to set value] ? pwm cycle = bfcmn3 2 t tm0n ? dead time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = { (cm0n3 ? cm0nx up ) + (cm0n3 ? cm0nx down ) } t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0nx down + cm0nx up ) t tm0n ? t dnm f clk : base clock t tm0n : tm0n count clock cm0nx up : set value of cm0n0 to cm0n2 while tm0n is counting up cm0nx down : set value of cm0n0 to cm0n2 while tm0n is counting down the pin level when the to0n0 to to0n5 pins are reset is high impedance state. when the control mode is selected thereafter, the fo llowing levels are output unt il tm0n is started. ? to0n0, to0n2, to0n4? when active low high level when active high low level ? to0n1, to0n3, to0n5? when active low low level when active high high level the active level is set with the alvto bit of the tomrn register. the default is active low. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value is set in the above form ula, the to0n0 to to 0n5 pins output a w aveform fixed to the inactive level waveform wit h active width ?0?. remarks. 1 m = 0 to 2 n = 0, 1 2. the interrupt request signal occurrence condi tions of intcm010 to intcm012, intcm0n4, and intcm0n5 are shown below. setting condition intcm010 to intcm012, intcm0n4, intcm0n5 signal occurrence status cm010 to cm012, cm0n4, cm0n5 cm0n3 occurs cm010 to cm012, cm0n4, cm0n5 = 0000h occurs cm010 to cm012, cm0n4, cm0n5 > cm0n3 does not occur
chapter 9 timer/counter function 246 user?s manual u15195ej5v0ud figure 9-20. operation timing in pwm m ode 1 (asymmetric tr iangular wave) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t t cm0n3 (f) cm0n3 (g) a b c d cm0nx match cm0nx match cm0nx match cm0nx match bcde g a fh b a gh f intcm0n3 intcm01x intcm01x intcm01x intcm01x inttm0n intcm0n3 inttm0n cde tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx 0000h remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. to not use dead time, set the tm0cedn bit of the tmc0n register to 1. 6. the above figure shows an active-high case. 7. intcm01x is generated on a match between tm01 and cm01x (a to d in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 247 user?s manual u15195ej5v0ud figure 9-20. operation timing in pwm m ode 1 (asymmetric tr iangular wave) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5)) cm0n3 (f) cm0n3 (g) a b c d cm0nx match cm0nx match cm0nx match cm0nx match bcde g a fh b a gh f intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx inttm0n intcm0n3 inttm0n cde tm0n count value interrupt request bfcmnx bfcmn3 cm0n3 cm0nx 0000h remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 4, 5 4. intcm0nx is generated on a match between tm 0n and cm0nx (a to d in the above figure). figure 9-21 shows the overall operation image.
chapter 9 timer/counter function 248 user?s manual u15195ej5v0ud figure 9-21. overall operation image of pwm mode 1 (asymmetric triangular wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 cm0n3 cm0n2 cm0n2 cm0n1 cm0n1 cm0n0 cm0n0 without dead time with dead time remark n = 0, 1
chapter 9 timer/counter function 249 user?s manual u15195ej5v0ud (a) when bfcmnx cm0n3 is set in software pr ocessing started by intcm0n3 figure 9-22. operation timing in pwm mode 1 (asymmetric triangular wave, bfcmnx cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t cm0n3 cm0n3 a b cm0nx match cm0nx match cm0nx match (bfcmnx = cm0n3) inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bccc a b accc intcm0n3 intcm01x intcm01x intcm01x (bfcm1x = cm013) intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. c cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm 01 and cm01x (a and b in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 250 user?s manual u15195ej5v0ud figure 9-22. operation timing in pwm mode 1 (asymmetric triangular wave, bfcmnx cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 a b cm0nx match cm0nx match cm0nx match (bfcmnx = cm0n3) inttm0n inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h bccc a b accc intcm0n3 intcm0nx intcm0nx intcm0nx (bfcmnx = cm0n3) intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. c cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a and b in the above figure). when a value greater than cm0n3 is set to bfcm n0 to bfcmn2, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a low level, and the negative phase side (to 0n1, to0n3, to0n5 pins) continues to output a high level. this feature is effective for outputting a low-level or high-level width exceeding the pwm cycle in an application such as in verter control. furthermore, if cm0n0 to cm0n2 = cm0n3 is set, matching of tm0n and cm0n0 to cm0n2 is detected during down counting by tm0n, so that the f/f remains reset as is, and is not set. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same.
chapter 9 timer/counter function 251 user?s manual u15195ej5v0ud (b) when bfcmnx > cm0n3 is set in software processing started by inttm0n figure 9-23. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx > cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm01x intcm0n3 remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 252 user?s manual u15195ej5v0ud figure 9-23. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx > cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm0nx intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. b > cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). when a value greater than cm0n3 is set to bfcm n0 to bfcmn2, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a high level, and th e negative phase side (to0n1, to0n3, to0n5 pins) continues to output a low level. this feature is effective for outputti ng a low-level or high-level width exceeding the pwm cycle in an applicati on such as inverter control. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-24 shows the change timing from the 100% duty state.
chapter 9 timer/counter function 253 user?s manual u15195ej5v0ud figure 9-24. change timing from 100% duty state (pwm mode 1) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bbbbbcde note cm0n3 cm0n3 a cm0nx match cm0n3 c d cm0nx match cm0nx match abbbbbcde t t t t inttm0n intcm0n3 intcm01x intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n intcm01x intcm01x note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm01 and cm01x (a to c in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 254 user?s manual u15195ej5v0ud figure 9-24. change timing from 100% duty state (pwm mode 1) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 tm0n count value bfcm0nx 0000h cm0nx interrupt request bbbbbcde cm0n3 cm0n3 a cm0nx match cm0n3 c d cm0nx match cm0nx match abbbbbcde inttm0n intcm0n3 intcm0nx intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n intcm0nx intcm0nx remarks 1. n = 0, 1 2. x = 4, 5 3. b > cm0n3 4. intcm0nx is generated on a match between tm 0n and cm0nx (a to c in the above figure).
chapter 9 timer/counter function 255 user?s manual u15195ej5v0ud (c) when bfcmnx = 0000h is set in softw are processing started by intcm0n3 figure 9-25. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = 0000h) (1) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t cm0n3 cm0n3 a b cm0nx match cm0nx match inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h b 0000h 0000h 0000h a b a 0000h 0000h 0000h intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm0n3 inttm0n cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm 01 and cm01x (a and b in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 256 user?s manual u15195ej5v0ud figure 9-25. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = 0000h) (1) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 a b cm0nx match cm0nx match inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h b 0000h 0000h 0000h a b a 0000h 0000h 0000h intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 inttm0n cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a and b in the above figure). since a tm0n = cm0n0 to cm0n2 = 0000h match is detect ed during up counting by tm0n, the f/f is just set and is not reset. the f/f is also set upon ma tch detection in the cycle when 0000h is transferred to cm0n0 to cm0n2 by inttm0n interrupt. figure 9-26 shows the change timing from the 100% duty state.
chapter 9 timer/counter function 257 user?s manual u15195ej5v0ud figure 9-26. change timing from 100% duty state (1) (pwm mode 1) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bcde note cm0n3 cm0n3 a c cm0nx match cm0n3 d b cm0nx match cm0nx match 0000h 0000h 0000h 0000h d e t t t t t t inttm0n intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm01x intcm01x intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n cm0nx match cm0nx match 0000h 0000h 0000h 0000h bc a cm0nx match note the f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm01 and cm01x (a to d in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 258 user?s manual u15195ej5v0ud figure 9-26. change timing from 100% duty state (1) (pwm mode 1) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 tm0n count value bfcm0nx 0000h cm0nx interrupt request bcde cm0n3 cm0n3 a c cm0nx match cm0n3 d b cm0nx match cm0nx match 0000h 0000h 0000h 0000h d e inttm0n intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n cm0nx match cm0nx match 0000h 0000h 0000h 0000h bc a cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm 0n and cm0nx (a to d in the above figure).
chapter 9 timer/counter function 259 user?s manual u15195ej5v0ud (d) when bfcmnx = 0000h is set in so ftware processing started by inttm0n figure 9-27. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = 0000h) (2) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h 0000h 0000h 0000h 0000h a 0000h a 0000h 0000h 0000h intcm0n3 intcm01x intcm01x intcm01x intcm0n3 cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 260 user?s manual u15195ej5v0ud figure 9-27. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = 0000h) (2) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 a cm0nx match inttm0n inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h 0000h 0000h 0000h 0000h a 0000h a 0000h 0000h 0000h intcm0n3 intcm0nx intcm0nx intcm0nx intcm0n3 cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). since tm0n = cm0n0 to cm0n2 = 0000h match is detec ted during up counting by tm0n, the f/f is just set and is not reset. therefore, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a high level, and the negative phase side (to0n1, to0n3, to0n5 pins) continue s to output a low level. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-28 shows the change timing from the 100% duty state.
chapter 9 timer/counter function 261 user?s manual u15195ej5v0ud figure 9-28. change timing from 100% duty state (2) (pwm mode 1) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bcd note cm0n3 cm0n3 a cm0nx match cm0n3 b c cm0nx match cm0nx match a 0000h 0000h 0000h 0000h 0000h b d t t t t inttm0n intcm0n3 intcm01x intcm01x intcm01x intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n 0000h 0000h 0000h 0000h 0000h c cm0nx match cm0nx match intcm01x intcm01x note f/f is reset upon inttm0n occurrence. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. intcm01x is generated on a match between tm01 and cm01x (a to c in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 262 user?s manual u15195ej5v0ud figure 9-28. change timing from 100% duty state (2) (pwm mode 1) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 tm0n count value bfcm0nx 0000h cm0nx interrupt request bcd cm0n3 cm0n3 a cm0nx match cm0n3 b c cm0nx match cm0nx match a 0000h 0000h 0000h 0000h 0000h b d inttm0n intcm0n3 intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 intcm0n3 inttm0n inttm0n inttm0n 0000h 0000h 0000h 0000h 0000h c cm0nx match cm0nx match intcm0nx intcm0nx remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm 0n and cm0nx (a to c in the above figure).
chapter 9 timer/counter function 263 user?s manual u15195ej5v0ud (e) when bfcmnx = cm0n3 is set in software processing started by inttm0n figure 9-29. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t cm0n3 cm0n3 a cm0nx match cm0nx match inttm0n inttm0n tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm0n3 intcm01x intcm01x intcm01x cm0nx match remarks 1. n = 0, 1 2. x = 0 to 2 3. b = cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 264 user?s manual u15195ej5v0ud figure 9-29. operation timing in pwm mode 1 (asym metric triangular wave, bfcmnx = cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 a cm0nx match cm0nx match inttm0n inttm0n tm0n count value bfcmnx interrupt request cm0nx 0000h bbbb a b abbb intcm0n3 intcm0n3 intcm0nx intcm0nx intcm0nx cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. b = cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). since tm0n and cm0n0 to cm0n2 match is detect ed during count down of tm0n when bfcmn0 to bfcmn2 = cm0n3 has been set, the f/f remains reset as is and is not set. therefore, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a low level, an d the negative phase side (to0n1, to0n3, to0n5 pins) continues to out put a high level. moreover, the timing of matching with tm0n with cm0n0 to cm0n2 = cm0n3 is the cycle when transfe r is performed from bfcmn0 to bfcmn2 to cm0n0 to cm0n2 by intcm0n3. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same.
chapter 9 timer/counter function 265 user?s manual u15195ej5v0ud (4) pwm mode 2: sawtooth wave modulation [setting procedure] (a) set pwm mode 2 (sawtooth wave) using the mod01 and mod00 bits of the tmc0n register. also set the active level of the to0n0 to to0n5 pins us ing the alvto bit of the tomrn register. (b) set the count clock of tm0n using the prm02 to prm00 bits of the tmc0n register. the transfer operation from bfcmn3 to cm0n3 is set using the b fte3 bit, and the transfer operation from bfcmn0 to bfcmn2, bfcmn4, and bfcmn5 to cm0 n0 to cm0n2, cm0n4, and cm0n5 is set using the bften bit. (c) set the initial values. (i) specify the interrupt culling ratio using the cul02 to cul00 bits of the tmc0n register. (ii) set the cycle width of the pwm cycle in bfcmn3. ? pwm cycle = (bfcmn3 value + 1) tm0n count clock (the tm0n count clock is set by the tmc0n register.) (iii) set the dead-time width in dtrrn. ? dead-time width = (dtrrn + 1)/f clk f clk : base clock (iv) set the set/reset timing of the f/f us ed in the pwm cycle in bfcm0n0 to bfcm0n2. (d) clear (0) the tm0cedn bit of the tmc0n register to enable dead-time timer operation. set tm0cedn = 1 when not using dead time. (e) setting (1) the tm0cen bit of the tmc0n register starts tm0n counting, and a 6-channel pwm signal is output from pins to0n0 to to0n5. caution setting cm0n3 to 0000h is prohibited.
chapter 9 timer/counter function 266 user?s manual u15195ej5v0ud [operation] in pwm mode 2, tm0n performs up count operation, and when it matches the value of cm0n3, match interrupt intcm0n3 is generated and tm0n is cleared (n = 0, 1). the pwm cycle in this mode is ((bfcmn3 value + 1) tm0n count clock). note that the next pwm cycle width is set to bfcmn3. the data of bfcmn3 is automatically transferred by hardware to cm0n3 upon generation of the intcm0n3 interrupt. furthermore, calculation is performed by software processing started by intcm0n3, and the data for the next cycle is set to bfcmn3. data setting to cm0n0 to cm0n2, which control the pwm duty, is explained next. setting of data to cm0n0 to cm0n2 consists of setti ng the duty output from bfcmn0 to bfcmn2. the values of bfcmn0 to bfcmn2 are automatically transferred by hardware to cm0n0 to cm0n2 upon generation of the intcm0n3 interrupt. furthermore , software processing is started up and calculation performed, and reset timing of the f/f for t he next cycle is set to bfcmn0 to bfcmn2. the pwm cycle and the pwm duty are se t in the above procedure. the f/f set/reset conditions upon match of cm0n0 to cm0n2 are as follows. ? set: tm0n and cm0n3 match detection and rising edge of tm0cen bit of tmc0n register ? reset: tm0n and cm0n0 to cm0n2 match detection the values of dtrrn are transferred to the corres ponding dead-time timers (dtmn0 to dtmn2) in synchronization with the set/reset timing of the f/f, and down counting is started. dtmn0 to dtmn2 count down to 000h, and stop when they count down further to fffh. dtmn0 to dtmn2 can automatically generate a width at which the active levels of the positive phase (to0n0, to0n2, to0n4) and negative phase (to0n1, to0n3, to0n5) do not overlap (dead time). in this way, software processing is started by an in terrupt (intcm0n3) that o ccurs once during every pwm cycle after initial setting has been performed, and by se tting the pwm cycle and pwm duty to be used in the next cycle, it is possible to autom atically output a pwm waveform to pins to0n0 to to0n5 taking into consideration the dead-time width (in the case of an interrupt culling ratio of 1/1).
chapter 9 timer/counter function 267 user?s manual u15195ej5v0ud [output waveform width with respect to set value] ? pwm cycle = (bfcmn3 + 1) t tm0n ? dead time width t dnm = (dtrrn + 1)/f clk ? active width of positive phas e (to0n0, to0n2, to0n4 pins) = (cm0nx + 1) t tm0n ? t dnm ? active width of negative ph ase (to0n1, to0n3, to0n5 pins) = (cm0n3 ? cm0nx) t tm0n ? t dnm f clk : base clock t tm0n : tm0n count clock cm0nx: set value of cm0n0 to cm0n2 the pin level when the to0n0 to to0n5 pins are reset is the high impedance state. when the control mode is selected thereafter, the following levels are output until the tm0n is started. ? to0n0, to0n2, to0n4? when active low high level when active high low level ? to0n1, to0n3, to0n5? when active low low level when active high high level the active level is set with the alvto bit of the tomrn register. the default is active low. caution if a value such that the positive phase or negative phase active width is ?0? or a negative value is set in the above form ula, the to0n0 to to 0n5 pins output a w aveform fixed to the inactive level waveform wit h active width ?0?. remarks. 1 m = 0 to 2 n = 0, 1 2. the interrupt request signal occurrence condi tions of intcm010 to intcm012, intcm0n4, and intcm0n5 are shown below. setting condition intcm010 to intcm012, intcm0n4, intcm0n5 signal occurrence status cm010 to cm012, cm0n4, cm0n5 cm0n3 occurs cm010 to cm012, cm0n4, cm0n5 = 0000h occurs cm010 to cm012, cm0n4, cm0n5 > cm0n3 does not occur
chapter 9 timer/counter function 268 user?s manual u15195ej5v0ud figure 9-30. operation timing in pwm mode 2 (sawtooth wave) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t t t cm0n3 (d) cm0n3 (e) a b cm0nx match cm0nx match bc ef bc a a ef d d tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx bfcmn3 cm0n3 dtmnx f/f cm0nx 0000h intcm0n3 intcm01x intcm01x intcm0n3 set by rising edge of tm0cen bit remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm 01 and cm01x (a and b in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 269 user?s manual u15195ej5v0ud figure 9-30. operation timing in pwm mode 2 (sawtooth wave) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 (d) cm0n3 (e) a b cm0nx match cm0nx match bc ef bc a a ef d d tm0n count value interrupt request bfcmnx bfcmn3 cm0n3 cm0nx 0000h intcm0n3 intcm0nx intcm0nx intcm0n3 remarks 1. the above figure shows the timing chart when both bfte3 and bften of the tmc0n register are 1, and transfer from bfcmn3 to cm0n3, or fr om bfcmnx to cm0nx is enabled. transfer is not performed when bfte3 = 0 or bften = 0. 2. n = 0, 1 3. x = 4, 5 4. intcm0nx is generated on a match between tm0n and cm0nx (a and b in the above figure). figure 9-31 shows the overall operation image.
chapter 9 timer/counter function 270 user?s manual u15195ej5v0ud figure 9-31. overall operation image of pwm mode 2 (sawtooth wave) cm0n3 tm0n count value to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output to0n0 output to0n1 output to0n2 output to0n3 output to0n4 output to0n5 output 0000h cm0n2 cm0n1 cm0n0 cm0n3 cm0n2 cm0n1 cm0n0 without dead time with dead time remarks. 1. n = 0, 1 2. the above figure shows an active low case. since the f/f is set at the rising edge of the tm0cen bit of the tmc 0n register in the first cycle, the pwm signal can be output.
chapter 9 timer/counter function 271 user?s manual u15195ej5v0ud (a) when bfcmnx > cm0n3 is set figure 9-32. operation timing in pwm mode 2 (sawtooth wave, bfcmnx > cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t cm0n3 cm0n3 cm0n3 a cm0nx match bbb bb a a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm01x intcm0n3 intcm0n3 set by rising edge of tm0cen bit remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 272 user?s manual u15195ej5v0ud figure 9-32. operation timing in pwm mode 2 (sawtooth wave, bfcmnx > cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 a cm0nx match bbb bb a a tm0n count value interrupt request bfcmnx cm0nx 0000h intcm0n3 intcm0nx intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. b > cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). when a value greater than cm0n3 is set to bfcm n0 to bfcmn2, the positive phase side (to0n0, to0n2, to0n4 pins) outputs a high level, and th e negative phase side (to0n1, to0n3, to0n5 pins) continues to output a low level. since tm0n and cm 0n0 to cm0n2 match does not occur, the f/f is not reset. this feature is effective for outputting a lo w-level or high-level widt h exceeding the pwm cycle in an application such as inverter control. the above explanation applies to an active high case. in an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. figure 9-33 shows the change timing from the 100% duty state.
chapter 9 timer/counter function 273 user?s manual u15195ej5v0ud figure 9-33. change timing from 100% duty state (pwm mode 2) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) cm0n3 tm0n count value bfcm0nx 0000h cm0nx dtmnx f/f interrupt request positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) ab b c d ab b c note cm0n3 cm0n3 a c cm0nx match cm0nx match cm0n3 t t t t t intcm0n3 intcm01x intcm01x intcm0n3 intcm0n3 intcm0n3 note the f/f is reset upon a match with cm0nx. remarks 1. n = 0, 1 2. x = 0 to 2 3. b > cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm 01 and cm01x (a and c in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 274 user?s manual u15195ej5v0ud figure 9-33. change timing from 100% duty state (pwm mode 2) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 tm0n count value bfcm0nx 0000h cm0nx interrupt request ab b c d ab b c cm0n3 cm0n3 a c cm0nx match cm0nx match cm0n3 intcm0n3 intcm0nx intcm0nx intcm0n3 intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. b > cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a and c in the above figure). the timing at which the f/f is reset is upon occu rrence of a match with cm0n0 to cm0n2 as usual.
chapter 9 timer/counter function 275 user?s manual u15195ej5v0ud (b) when bfcmnx = cm0n3 is set figure 9-34. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t t t cm0n3 cm0n3 cm0n3 a cm0nx match bbb bb a a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm0n3 intcm0n3 set by rising edge of tm0cen bit cm0nx match cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 0 to 2 3. b = cm0n3 4. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 5. the above figure shows an active-high case. 6. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 276 user?s manual u15195ej5v0ud figure 9-34. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 a cm0nx match bbb bb a a tm0n count value interrupt request bfcmnx cm0nx 0000h intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 cm0nx match cm0nx match cm0nx match remarks 1. n = 0, 1 2. x = 4, 5 3. b = cm0n3 4. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). if match signal intcm0n3 for tm0n and cm0n3 and the match signal for tm0n and cm0n0 to cm0n2 conflict, reset of the f/f takes precedence, so that the f/f is not set following a match of cm0n0 to cm0n2 (= cm0n3) and tm0n.
chapter 9 timer/counter function 277 user?s manual u15195ej5v0ud (c) when bfcmnx = 0000h is set figure 9-35. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = 0000h) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) t t w w w cm0n3 cm0n3 cm0n3 a cm0nx match cm0nx match cm0nx match cm0nx match bbb bb a a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h note intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm0n3 intcm0n3 note set at the rising edge of the tm0cen bit. remarks 1. n = 0, 1 2. x = 0 to 2 3. t: dead time = (dtrrn + 1)/f clk (f clk : base clock) 4. the above figure shows an active-high case. 5. w: width between cm0n3 match and cm 0nx match (timer count clock) 6. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 278 user?s manual u15195ej5v0ud figure 9-35. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = 0000h) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 a cm0nx match cm0nx match cm0nx match cm0nx match bbb bb a a tm0n count value interrupt request bfcmnx cm0nx 0000h intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure). if cm0n0 to cm0n2 = 0000h has been set, the output waveform resulting from the tm0n count clock rate and the dtrrn set value differ.
chapter 9 timer/counter function 279 user?s manual u15195ej5v0ud (d) when bfcmnx = 0000h is set while dtmnx = 000h or tm0cedn bit = 1 a pulse equivalent to one count clock of the timer is output. figure 9-36. operation timing in pwm m ode 2 (sawtooth wave, bfcmnx = 0000h) while dtmnx = 000h or tm0cedn bit = 1 (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) w w w cm0n3 cm0n3 cm0n3 a cm0nx match cm0nx match cm0nx match cm0nx match bbb bb a a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) interrupt request bfcmnx dtmnx f/f cm0nx 0000h note intcm0n3 intcm01x intcm01x intcm01x intcm01x intcm0n3 intcm0n3 note set at the rising edge of the tm0cen bit. remarks 1. n = 0, 1 2. x = 0 to 2 3. the above figure shows an active-high case. 4. w: width of a pulse equivalent to one count clock of the timer from cm0n3 match 5. intcm01x is generated on a match between tm01 and cm01x (a in the above figure). intcm00x is not generated.
chapter 9 timer/counter function 280 user?s manual u15195ej5v0ud figure 9-36. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = 0000h while dtmnx = 000h or tm0cedn bit = 1) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 a cm0nx match cm0nx match cm0nx match cm0nx match bbb bb a a tm0n count value interrupt request bfcmnx cm0nx 0000h intcm0n3 intcm0nx intcm0nx intcm0nx intcm0nx intcm0n3 intcm0n3 remarks 1. n = 0, 1 2. x = 4, 5 3. intcm0nx is generated on a match between tm0n and cm0nx (a in the above figure).
chapter 9 timer/counter function 281 user?s manual u15195ej5v0ud (e) when bfcmnx = cm0n3 = a is set figure 9-37. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3 = a) (when dtrrn = 0000h, tm0cedn bit of tmc0n regi ster = 1, alvto bit of tomrn register = 1 (pwm driving, active l evel = high) are set) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) l cm0n3 cm0n3 cm0n3 cm0nx match cm0nx match cm0nx match a a aaa a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 interrupt request remarks 1. n = 0, 1 2. x = 0 to 2 3. the above figure shows an active-low case. 4. for the timing including the dead time, refer to figure 9-35 .
chapter 9 timer/counter function 282 user?s manual u15195ej5v0ud figure 9-37. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3 = a) (when dtrrn = 0000h, tm0cedn bit of tmc0n regi ster = 1, alvto bit of tomrn register = 1 (pwm driving, active l evel = high) are set) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 cm0nx match cm0nx match cm0nx match a a aaa a tm0n count value bfcmnx cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 interrupt request remarks 1. n = 0, 1 2. x = 4, 5 3. for the timing including the dead time, refer to figure 9-35 .
chapter 9 timer/counter function 283 user?s manual u15195ej5v0ud figure 9-38. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3 = a) (when dtrrn = 0000h, tm0cedn bit of tmc0n regi ster = 1, alvto bit of tomrn register = 0 (pwm driving, active l evel = low) are set) (1/2) (a) operation timing of compare regi sters 0n0 to 0n2 (cm0n0 to cm0n2) l l h cm0n3 cm0n3 cm0n3 cm0nx match cm0nx match cm0nx match a a aaa a tm0n count value positive phase (to0n0, to0n2, to0n4) negative phase (to0n1, to0n3, to0n5) bfcmnx dtmnx f/f cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 interrupt request remarks 1. n = 0, 1 2. x = 0 to 2 3. the above figure shows an active-high case. 4. for the timing including the dead time, refer to figure 9-35 .
chapter 9 timer/counter function 284 user?s manual u15195ej5v0ud figure 9-38. operation timing in pwm mode 2 (sawtooth wave, bfcmnx = cm0n3 = a) (when dtrrn = 0000h, tm0cedn bit of tmc0n regi ster = 1, alvto bit of tomrn register = 0 (pwm driving, active l evel = low) are set) (2/2) (b) operation timing of compare re gisters 0n4 and 0n5 (cm0n4, cm0n5) cm0n3 cm0n3 cm0n3 cm0nx match cm0nx match cm0nx match a a aaa a tm0n count value bfcmnx cm0nx 0000h intcm0n3 intcm0n3 intcm0n3 interrupt request remarks 1. n = 0, 1 2. x = 4, 5 3. for the timing including the dead time, refer to figure 9-35 .
chapter 9 timer/counter function 285 user?s manual u15195ej5v0ud 9.1.7 operation timing (1) tm0cen bit write and tm0n timer operation timing figure 9-39 shows the timing from when the tm0cen bit of the tmc0n register is written until the tm0n timer starts operating. figure 9-39. tm0cen bit write and tm0n timer operation timing register write timing 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h f clk tm0cen bit write timing tm0n caution the operation of tm0n starts 2f clk after the register write timing. remark f clk : base clock
chapter 9 timer/counter function 286 user?s manual u15195ej5v0ud (2) interrupt generation timing the interrupt generation timing at the tm0n count clock settings (prm 02 to prm00 bits of the tmc0n register) in the various modes is described below. figure 9-40. interrupt generation ti ming in pwm mode 0 (symmetric triangular wave), pwm mode 1 (asymmetric triangular wave) (a) when count clock = f clk 0002h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h 0001h 0002h 0001h 0000h cm0nx tm0n intcm0nx inttm0n f clk (b) when count clock = f clk /4 0002h 0000h 0001h 0002h 0001h 0000h cm0nx tm0n intcm0nx inttm0n f clk cautions 1. intcm0nx is generated at the next f clk after detection of a tm0n and cm0nx match. 2. inttm0n is generated at the next f clk after detection of a tm0n and 0000h match. 3. inttm0n is generated at the next f clk after detection of a tm0n and 0000h match, even if the count clock is 1/2, 1/8, 1/16, or 1/32. remarks 1. n = 0, 1 2. where n = 0: x = 3 to 5 where n = 1: x = 0 to 5 3. f clk : base clock
chapter 9 timer/counter function 287 user?s manual u15195ej5v0ud figure 9-41. interrupt generation ti ming in pwm mode 2 (sawtooth wave) (a) when count clock = f clk 0002h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h 0000h 0001h 0002h cm0nx tm0n intcm0nx f clk (b) when count clock = f clk /4 0002h 0000h 0001h 0002h 0000h 0001h cm0nx tm0n intcm0nx f clk cautions 1. intcm0nx is generated at the next f clk after detection of a tm0n and cm0nx match. 2. intcm0nx is gene rated at the next f clk after detection of a tm0n and cm0nx match even if the count clock is 1/2, 1/8, 1/16, or 1/32. remarks 1. n = 0, 1 2. where n = 0: x = 3 to 5 where n = 1: x = 0 to 5 3. f clk : base clock
chapter 9 timer/counter function 288 user?s manual u15195ej5v0ud (3) relationship between inte rrupt generation and stintn bit of tmc0n register the interrupt generation timing for the setting of the st intn bit of the tmc0n register and the interrupt culling ratio setting (bits cul02 to cul00) in the various modes is described below. if, to realize the inttm0n and intcm0n3 interrupt culling function for tm 0n, bits cul02 to cul00 of the tmc0n register are set for a culling ratio other than 1/ 1, and count operation is st arted, the interrupt output order differs according to the setting of the stintn bit when counting starts. figure 9-42. interrupt generation timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave): in case of interrupt culling ratio of 1/1 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk remarks 1. n = 0, 1 2. f clk : base clock
chapter 9 timer/counter function 289 user?s manual u15195ej5v0ud figure 9-43. interrupt generation timing in pwm mode 0 (symmetr ic triangular wave), pwm mode 1 (asymmetric triangular wave): in case of interrupt culling ratio of 1/2 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 inttm0n f clk remarks 1. n = 0, 1 2. f clk : base clock
chapter 9 timer/counter function 290 user?s manual u15195ej5v0ud figure 9-44. interrupt generation timi ng in pwm mode 2 (sawtooth wave): in case of interrupt culling ratio of 1/1 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk remarks 1. n = 0, 1 2. f clk : base clock
chapter 9 timer/counter function 291 user?s manual u15195ej5v0ud figure 9-45. interrupt generation timing in pwm mode 2 (sawtooth wave): in case of interrupt culling ratio of 1/2 (a) when stintn bit = 0 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk (b) when stintn bit = 1 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h 0004h 0000h 0001h 0002h 0003h cm0n3 tm0cen bit tm0n intcm0n3 f clk remarks 1. n = 0, 1 2. f clk : base clock
chapter 9 timer/counter function 292 user?s manual u15195ej5v0ud (4) to0n0 to to0n5 output timing figure 9-46. to0n0 to to0n5 output timing in pwm mode 0 (symmetric tria ngular wave), pwm mode 1 (asymmetric triangular wave) 0003h 0002h 0008h 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0002h ffffh ffffh ffffh 0001h 0000h 0002h 0001h 0000h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 0001h 0002h 0003h cm0nx tm0n dtmnx match signal f/f to0n0, to0n2, to0n4 to0n1, to0n3, to0n5 dtrrn f clk cm0n3 tm0cen bit remarks 1. the above figure shows the timing until the compare register and the tm0n timer match and the to0n0 to to0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. f clk : base clock
chapter 9 timer/counter function 293 user?s manual u15195ej5v0ud figure 9-47. to0n0 to to0n5 output timing in pwm mode 2 (sawtooth wave) 0005h 0002h 000ah 0001h 0002h 0003h 0004h 0005h 0002h ffffh 0000h ffffh ffffh 0001h 0000h 0002h 0001h 0000h 0002h ffffh 0001h 0000h 0006h 0007h 0008h 0009h 000ah 0000h 0001h 0002h 0003h 0004h 0005h 0006h cm0nx tm0n dtmnx match signal f/f to0n0, to0n2, to0n4 to0n1, to0n3, to0n5 dtrrn f clk cm0n3 tm0cen bit remarks 1. the above figure shows the timing until the co mpare register and the tm0n timer match and the to0n0 to to0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. f clk : base clock
chapter 9 timer/counter function 294 user?s manual u15195ej5v0ud 9.2 timer 1 9.2.1 features (timer 1) timer 10 (tm10) is a 16-bit up/down counter that performs the following operations. ? general-purpose timer mode (see 9.2.5 (1) operation in general-purpose timer mode .) free-running timer pwm output ? up/down counter mode (see 9.2.5 (2) operation in udc mode .) udc mode a (mode 1, mode 2, mode 3, mode 4) udc mode b (mode 1, mode 2, mode 3, mode 4) 9.2.2 function overview (timer 1) ? 16-bit 2-phase encoder input up/down counter & general-purpose timer (tm10) ? compare registers: 2 ? capture/compare registers: 2 ? interrupt request sources ? capture/compare match interrupt: 2 types ? compare match interrupt request: 2 types ? capture request signal: 2 types ? the tm10 value can be latched using the valid edge of the intp100 and intp101 pins corresponding to the capture/compare register as the capture trigger. ? count clock selectable through division by prescaler (s et the frequency of the count clock to 10 mhz or less) ? base clock (f clk ): 1 type (set f clk to 20 mhz or less) f xx /2 ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). division ratio base clock (f clk ) 1/2 f xx /4 1/4 f xx /8 1/8 f xx /16 1/16 f xx /32 1/32 f xx /64 1/64 f xx /128 1/128 f xx /256
chapter 9 timer/counter function 295 user?s manual u15195ej5v0ud ? pwm output function in the general-purpose timer mode, 16-bit resolu tion pwm can be output from the to10 pin. ? timer clear the following timer clear operations are perform ed according to the mode that is used. (a) general-purpose timer mode: timer clear operatio n is possible upon occurrence of match with cm100 set value. (b) up/down counter mode: the timer clear operati on can be selected from among the following four conditions. (i) timer clear performe d upon occurrence of match with cm100 set value during tm10 up count operation, and timer clear performed upon occurr ence of match with cm101 set value during tm10 down count operation. (ii) timer clear performed only by external input. (iii) timer clear performed upon occurrence of match between tm10 count value and cm100 set value. (iv) timer clear performed upon occurrence of exte rnal input and match betw een tm10 count value and cm100 set value. ? external pulse output (to10): 1 remark f xx : internal system clock
chapter 9 timer/counter function 296 user?s manual u15195ej5v0ud 9.2.3 basic configuration the basic configuration is shown below. table 9-5. timer 1 configuration list timer count clock register read/write generated interrupt signal capture trigger tm10 read/write ? ? cm100 read/write intcm100 ? cm101 read/write intcm101 ? cc100 read/write intcc100 intp100 timer 1 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 cc101 read/write intcc101 intp100 or intp101 remark f xx : internal system clock figure 9-48 shows the block diagram of timer 1. figure 9-48. block di agram of timer 1 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 edge detector output control selector selector edge detector clock controller edge detector edge detector edge detector clr1, clr0 cm101 cm100 tm10 tm10 clear control cc101 cc100 msel cmd tm1ubd0 enmd alvt10 rlen tm1udf0 tm1ovf0 clear tclr selclk f clk internal bus internal bus tclr10/ intp101 tcud10/ intp100 tiud10 f xx /2 intp100/ intcc100 intp101 note / intcc101 to10 intcm100 intcm101 selector note the int101 interrupt is the signa l of the capture trigger signal fr om the intp101 pin or the capture trigger signal from the intp100 pin, sele cted by the csl0 bit of the csl10 register. remarks 1. f xx : internal system clock 2. f clk : base clock (20 mhz (max.))
chapter 9 timer/counter function 297 user?s manual u15195ej5v0ud (1) timer 10 (tm10) tm10 is a general-purpose timer (in general-purpose mode) and 2-phase encoder input up/down counter (in udc mode). this timer counts up in the general-purpose ti mer mode and counts up/down in the udc mode. it can be read/written in 16-bit units. cautions 1. writing to tm10 is enabled only when the tm1ce0 bit of the tmc10 register is 0 (count operation disabled). 2. continuous reading of tm10 is prohibited. if tm10 is continuously read, the second read value may differ from the actual value. if tm10 must be read twice, be sure to read another register between the firs t and the second read operation. 3. writing the same value to the tm10, cc100, and cc101 registers, and the status10 register is prohibited. writing the same value to the ccr0, tum0 , tmc10, sesa10, and prm10 registers, and cm100 and cm101 registers is permitted (wri ting the same value is guaranteed even during a count operation). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 tm10 address fffff5e0h after reset 0000h tm10 start and stop is controlled by the tm1ce0 bit of timer control register 10 (tmc10). the tm10 operation consists of the following two modes. (a) general-purpose timer mode in the general-purpose timer mode, tm10 operates as a 16-bit interval timer, free-running timer, or pwm output. counting is performed based on the clock selected by software. division by the prescaler can be selected for the count clock from among f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, or f clk /128 using the prm12 to prm10 bits of prescaler mode register 10 (prm10). (f clk : base clock, refer to 9.2.4 (1) timer 1/timer 2 clo ck selection register (prm02) ). (b) up/down counter mode (udc mode) in the udc mode, tm10 functions as a 16-bit up/do wn counter that perfo rms counting based on the tcud10 and tiud10 input signals. this mode is divided into the udc mode a and udc mode b, depending on the condition of clearing tm10. the conditions for clearing tm10 are as follows, depending on the operation mode.
chapter 9 timer/counter function 298 user?s manual u15195ej5v0ud table 9-6. timer 1 (tm10) clear conditions tum0 register tmc10 register operation mode cmd bit msel bit enmd bit clr1 bit clr0 bit tm10 clear 0 clearing not performed (free-running timer) general-purpose timer mode 0 0 1 cleared upon match with cm100 set value 0 0 cleared only by tclr10 input 0 1 cleared upon match with cm100 set value during up count operation 1 0 cleared by tclr10 input or upon match with cm100 set value during up count operation udc mode a 1 0 1 1 clearing not performed udc mode b 1 1 cleared upon match with cm100 set value during up count operation or upon match with cm101 set value during down count operation other than the above setting prohibited remark : indicates that the set value of that bit is ignored.
chapter 9 timer/counter function 299 user?s manual u15195ej5v0ud 9.2.4 control registers (1) timer 1/timer 2 clock sel ection register (prm02) the prm02 register is used to select the base clock (f clk ) of timer 1 and timer 2. this register can be read/written in 8-bit or 1-bit units. cautions 1. always set 01h to this register before using the timers 1 and 2. setting to other than 01h is prohibited. 2. set f clk to 20 mhz or less. 7 0 prm02 6 0 5 0 4 0 3 0 2 0 1 0 0 prm2 address fffff5d8h after reset 00h bit position bit name function 0 prm2 specifies the base clock (f clk ) of timer 1 and timer 2. 1: f clk = f xx /2 remark f xx : internal system clock
chapter 9 timer/counter function 300 user?s manual u15195ej5v0ud (2) timer unit mode register 0 (tum0) the tum0 register is an 8-bit register used to specif y the tm10 operation mode or to control the operation of the pwm output pin. tum0 can be read/written in 8-bit or 1-bit units. cautions 1. changing the value of the tum0 re gister during tm10 operation (tm1ce0 bit of tmc10 register = 1) is prohibited. 2. when the cmd bit = 0 (gen eral-purpose timer mode), setting msel = 1 (udc mode b) is prohibited. 7 cmd tum0 6 0 5 0 4 0 3 toe10 2 alvt10 1 0 0 msel address fffff5ebh after reset 00h bit position bit name function 7 cmd specifies tm10 operation mode. 0: general-purpose timer mode (up count) 1: udc mode (up/down count) 3 toe10 specifies timer output (to10) enable. 0: timer output disabled 1: timer output enabled caution when cmd bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe10 bit. at this time, timer output consists of the negative phase level of the level set by the alvt10 bit. 2 alvt10 specifies active level of timer output (to10). 0: active level is high level 1: active level is low level caution when cmd bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe10 bit. at this time, timer output consists of the negative phase level of the level set by the alvt10 bit. 0 msel specifies operation in udc mode (up/down count) 0: udc mode a tm10 can be cleared by setting the clr1, clr0 bits of the tmc10 register. 1: udc mode b tm10 is cleared in the following cases. ? upon match with cm100 during tm10 up count operation ? upon match with cm101 during tm10 down count operation when udc mode b is set, the enmd, clr1, and clr0 bits of the tmc10 register become invalid.
chapter 9 timer/counter function 301 user?s manual u15195ej5v0ud (3) timer control register 10 (tmc10) the tmc10 register is used to enable/disable tm10 operat ion and to set transfer and timer clear operations. tmc10 can be read/written in 8-bit or 1-bit units. caution changing the values of the tmc10 regist er bits other than the tm1ce0 bit during tm10 operation (tm1ce0 = 1) is prohibited. (1/2) 7 0 tmc10 <6> tm1ce0 5 0 4 0 3 rlen 2 enmd 1 clr1 0 clr0 address fffff5ech after reset 00h bit position bit name function 6 tm1ce0 enables/disables tm10 operation. 0: tm10 count operation disabled 1: tm10 count operation enabled 3 rlen enables/disables transfer from cm100 to tm10. 0: transfer disabled 1: transfer enabled cautions 1. when rlen = 1, the value set to cm100 is transferred to tm10 upon occurrence of a tm10 underflow. 2. the rlen bit is valid only in udc mode a (tum0 register?s cmd bit = 1, msel bit = 0). in the general-purpose timer mode (cmd bit = 0) and in udc mode b (cmd bit = 1, msel bit =1), a transfer operation is not performed even the rlen bit is set (1). 2 enmd enables/disables clearing of tm10 in general-purpose timer mode (cmd bit of tum0 register = 0). 0: clear disabled (free-running mode) clearing is not performed even when tm10 and cm100 values match. 1: clear enabled clearing is performed when tm10 and cm100 values match. caution the enmd bit setting becomes invalid in udc mode (cmd bit of tum0 register = 1).
chapter 9 timer/counter function 302 user?s manual u15195ej5v0ud (2/2) bit position bit name function controls tm10 clear operation in udc mode a. clr1 clr0 specifies tm10 clear source 0 0 cleared only by external input (tclr10) 0 1 cleared upon match of tm10 count value and cm100 set value 1 0 cleared by tclr10 input or upon match of tm10 count value and cm100 set value 1 1 not cleared 1, 0 clr1, clr0 cautions 1. clearing by match of the tm10 count value and cm100 set value is valid only during a tm10 up count operation (tm10 is not cleared during a tm10 down count operation). 2. the clr1 and clr0 bit settings are invalid in general-purpose timer mode (cmd bit of tum0 register = 0). 3. the clr1 and clr0 bit settings are invalid in udc mode b (msel bit of tum0 register = 1). 4. when clearing by tclr10 has been enabled by bits clr1 and clr0, clearing is performed whether the value of the tm1ce0 bit is 1 or 0. (4) capture/compare control register 0 (ccr0) the ccr0 register specifies the op eration mode of the capture/comp are registers (cc100, cc101). ccr0 can be read/written in 8-bit or 1-bit units. caution overwriting the ccr0 register during tm10 operation (tm1ce0 bit = 1) is prohibited. 7 0 ccr0 6 0 5 0 4 0 3 0 2 0 1 cms1 0 cms0 address fffff5eah after reset 00h bit position bit name function 1 cms1 specifies operation mode of cc101. 0: capture register 1: compare register 0 cms0 specifies operation mode of cc100. 0: capture register 1: compare register
chapter 9 timer/counter function 303 user?s manual u15195ej5v0ud (5) signal edge selection register 10 (sesa10) the sesa10 register is used to specif y the valid edge of external interr upt requests from external pins (intp100, intp101, tiud10, tcud10, tclr10). the valid edge (rising edge, falling edge, or both edges ) can be specified independently for each pin. sesa10 can be read/written in 8-bit or 1-bit units. cautions 1. changing the values of the sesa10 register bits duri ng tm10 operation (tm1ce0 = 1) is prohibited. 2. be sure to set (to 1) the tm1ce0 bit of timer control register 10 (tmc10) even when timer 1 is not used and the tcud10/intp 100 and tclr10/intp101 pins are used as intp100 and intp101. (1/2) 7 tesud01 sesa10 6 tesud00 5 cesud01 4 cesud00 3 ies1011 2 ies1010 1 ies1001 0 ies1000 address fffff5edh after reset 00h tiud10, tcud10 tclr10 intp101 intp100 bit position bit name function specifies valid edge of pins tiud10, tcud10. tesud01 tesud00 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 7, 6 tesud01, tesud00 cautions 1. the set values of the tesud01 and tesud00 bits are only valid in udc mode a and udc mode b. 2. if mode 4 is specified as the operation mode of tm10 (specified by the prm12 to prm10 bits of the prm10 register), the valid edge specifications for the tiud10 and tcud10 pins (bits tesud01 and tesud00) are not valid.
chapter 9 timer/counter function 304 user?s manual u15195ej5v0ud (2/2) bit position bit name function specifies valid edge of tclr10 pin. cesud01 cesud00 valid edge 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 5, 4 cesud01, cesud00 the set values of bits cesud01 and cesud00 and the tm10 operation are related as follows. 00: tm10 cleared after detection of falling edge of tclr10 01: tm10 cleared after detection of rising edge of tclr10 10: tm10 cleared status held while tclr10 input is low level 11: tm10 cleared status held while tclr10 input is high level caution the set values of the cesud01 and cesud00 bits are valid only in udc mode a. specifies valid edge of the pin (intp101/intp100) selected by the csl0 bit of the csl10 register. ies1011 ies1010 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 3, 2 ies1011, ies1010 specifies valid edge of intp100 pin. ies1001 ies1000 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies1001, ies1000
chapter 9 timer/counter function 305 user?s manual u15195ej5v0ud (6) prescaler mode register 10 (prm10) the prm10 register is used to perform the following selections. ? selection of count clock in general-purpose ti mer mode (cmd bit of tum0 register = 0) ? selection of count operation mode in udc mode (cmd = 1) prm10 can be read/written in 8-bit or 1-bit units. cautions 1. overwriting the prm 10 register during tm10 operation (tm1 ce0 bit = 1) is prohibited. 2. clearing the prm12 bit to 0 is prohibited in udc mode (cmd bit of tum0 register = 1). 3. when tm10 is in mode 4, specification of the valid edge for the tiud10 and tcud10 pins is valid. 7 0 prm10 6 0 5 0 4 0 3 0 2 prm12 1 prm11 0 prm10 address fffff5eeh after reset 07h bit position bit name function specifies the up/down count operation mode during input of the clock rate when the internal clock of the tm10 is used, or during external clock (tiud10) input. cmd = 0 cmd = 1 prm12 prm11 prm10 count clock count clock udc mode 0 0 0 setting prohibited 0 0 1 f clk /2 0 1 0 f clk /4 0 1 1 f clk /8 setting prohibited 1 0 0 f clk /16 mode 1 1 0 1 f clk /32 mode 2 1 1 0 f clk /64 mode 3 1 1 1 f clk /128 tiud10 mode 4 2 to 0 prm12 to prm10 remark f clk : base clock (a) in general-purpose timer mode (c md bit of tum0 register = 0) the count clock is specified by bits prm12 to prm10. (b) udc mode (cmd bit of tum0 register = 1) the tm10 count triggers in the udc mode are as follows. operation mode tm10 operation mode 1 down count when tcud10 = high level up count when tcud10 = low level mode 2 up count upon detection of valid edge of tiud10 input down count upon detection of valid edge of tcud10 input mode 3 up count upon detection of valid edge of tiud10 input when tcud10 = high level down count upon detection of valid edge of tiud10 input when tcud10 = low level mode 4 automatic judgment upon detection of both edges of tiud10 input and both edges of tcud10 input
chapter 9 timer/counter function 306 user?s manual u15195ej5v0ud (7) status register 0 (status0) the status0 register indicates t he operating status of tm10. status0 is read-only, in 8-bit or 1-bit units. 7 0 status0 6 0 5 0 4 0 3 0 <2> tm1udf0 <1> tm1ovf0 <0> tm1ubd0 address fffff5efh after reset 00h bit position bit name function 2 tm1udf0 tm10 underflow flag 0: no tm10 count underflow 1: tm10 count underflow caution the tm1udf0 bit is cleared (to 0) upon completion of a read access to the status0 register from the cpu. 1 tm1ovf0 tm10 overflow flag 0: no tm10 count overflow 1: tm10 count overflow caution the tm1ovf0 bit is cleared (to 0) upon completion of a read access to the status0 register from the cpu. 0 tm1ubd0 indicates the operating status of tm10 up/down count. 0: tm10 up count in progress 1: tm10 down count in progress caution the state of the tm1ubd0 bit differs according to the mode as follows. ? the tm1ubd0 bit is fixed to 0 in general-purpose timer mode (cmd bit of tum0 register = 0). ? the tm1ubd0 bit indicates the tm10 up-/down-count status in udc mode (cmd bit of tum0 register = 1). (8) cc101 capture input selection register (csl10) the csl10 register is used to select the intp101 or intp100 pin to input a capture signal when the cc101 register is used as a capture register. csl10 can be read/written in 8-bit or 1-bit units. 7 0 csl10 6 0 5 0 4 0 3 0 2 0 1 0 0 csl0 address fffff5f6h after reset 00h bit position bit name function 0 csl0 specifies capture input to cc101. 0: intp101 1: intp100
chapter 9 timer/counter function 307 user?s manual u15195ej5v0ud (9) compare register 100 (cm100) cm100 is a 16-bit register that al ways compares its value with the val ue of tm10. when the value of a compare register matches the value of tm10, an interr upt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tum0 register = 0) and udc mode a (msel bit of tum0 register = 0), an interrupt signal (intcm100) is generated upon occurrence of a match. ? in udc mode b (msel bit of tum0 register = 1), an interrupt signal (intcm100) is generated only upon occurrence of a match during a down count operation. cm100 can be read/written in 16-bit units. caution when the tm1ce0 bit of the tmc10 register is 1, it is prohibited to overwrite the value of the cm100 register. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm100 address fffff5e2h after reset 0000h (10) compare register 101 (cm101) cm101 is a 16-bit register that always compares its value with the value of tm10. when the value of the compare register matches the value of tm10, an interr upt signal is generated. the interrupt generation timing in the various modes is described below. ? in the general-purpose timer mode (cmd bit of tum0 register = 0) and udc mode a (msel bit of tum0 register = 0), an interrupt signal (intcm101) is generated upon occurrence of a match. ? in udc mode b (msel bit of tum0 register = 1), an interrupt signal (intcm101) is generated only upon occurrence of a match during a down count operation. cm101 can be read/written in 16-bit units. caution when the tm1ce0 bit of the tmc10 register is ?1?, it is pr ohibited to overwrite the value of the cm101 register. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cm101 address fffff5e4h after reset 0000h
chapter 9 timer/counter function 308 user?s manual u15195ej5v0ud (11) capture/compare register 100 (cc100) cc100 is a 16-bit register. it can be specified as a capture register or as a compare register using capture/compare control register 0 (ccr0). cc1 00 can be read/written in 16-bit units. cautions 1. when used as a captu re register (cms0 bit of ccr0 register = 0), write access is prohibited. 2. when used as a compare register (cms0 bit of ccr0 register = 1) during tm10 operation (tm1ce0 bit of tmc10 register = 1) , overwriting the cc100 register values is prohibited. 3. when tm10 has been stopped (tm1ce0 bit of tmc10 register = 0), the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, set a new compare value. 5. continuous reading of cc 100 is prohibited. if cc100 is continuously read, the second read value may differ from the actual value. if cc100 must be read twice, be sure to read another register between the fi rst and the second read operation. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc100 address fffff5e6h after reset 0000h (a) when set as a capture register when cc100 is set as a capture register, the valid edge of the corresponding external interrupt signal (intp100) is detected as the capture trigger. tm10 latches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the c apture register until the next capture operation. the valid edge of external interrupts (rising edge, falli ng edge, both rising and falling edges) is selected by signal edge selection register 10 (sesa10). when the cc100 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of the intp100 signal. (b) when set as a compare register when cc100 is set as a compare register, it always co mpares its own value with the value of tm10. if the value of cc100 matches the valu e of the tm10, cc100 generates an interrupt signal (intcc100).
chapter 9 timer/counter function 309 user?s manual u15195ej5v0ud (12) capture/compare register 101 (cc101) cc101 is a 16-bit register. it can be specified as a capture register or as a compare register using capture/compare control register 0 (ccr0). cc1 01 can be read/written in 16-bit units. cautions 1. when used as a captu re register (cms1 bit of ccr0 register = 0), write access is prohibited. 2. when used as a compare register (cms1 bit of ccr0 register = 1) during tm10 operation (tm1ce0 bit of tmc10 register = 1) , overwriting the cc101 register values is prohibited. 3. when tm10 has been stopped (tm1ce0 bit of tmc10 register = 0), the capture trigger is disabled. 4. when the operation mode is changed from capture register to co mpare register, newly set a compare value. 5. continuous reading of cc 101 is prohibited. if cc101 is continuously read, the second read value may differ from the actual value. if cc101 must be read twice, be sure to read another register between the fi rst and the second read operation. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cc101 address fffff5e8h after reset 0000h (a) when set as a capture register when cc101 is set as a capture register, the valid edge of either corresponding external interrupt signal (intp100 or intp101) is selected with the selector, a nd the valid edge of the selected external interrupt signal is detected as the capture trigger. tm10 la tches the count value in synchronization with the capture trigger (capture operation). the latched value is held in the c apture register until the next capture operation. the valid edge of external interrupts (rising edge, falli ng edge, both rising and falling edges) is selected by signal edge selection register 10 (sesa10). when the cc101 register is specif ied as a capture register, inte rrupts are generated upon detection of the valid edge of either the intp100 or intp101 signal. (b) when set as a compare register when cc101 is set as a compare register, it always co mpares its own value with the value of tm10. if the value of cc101 matches the valu e of the tm10, cc101 generates an interrupt signal (intcc101).
chapter 9 timer/counter function 310 user?s manual u15195ej5v0ud 9.2.5 operation (1) operation in genera l-purpose timer mode tm10 can perform the following operations in the general-purpose timer mode. (a) interval operation (when enmd bit of tmc10 register = 1) tm10 and cm100 always compare their values a nd the intcm100 interr upt is generated upon occurrence of a match. tm10 is cleared (0000h) at the count clock following the match. furthermore, when one more count clock is input, tm10 counts up to 0001h. the interval time can be calculated with the following formula. interval time = (cm100 value + 1) tm10 count clock rate (b) free-running operation (when enmd bit of tmc10 register = 0) tm10 performs a full count operation from 0000h to ffffh, and after the tm1ovf 0 bit of the status0 register is set (to 1), tm10 is cleared to 0000h at the next count clock and resumes counting. the free-running cycle can be calcul ated by the following formula. free-running cycle = 65,536 tm10 count clock rate (c) compare function tm10 connects two compare register (cm100, cm10 1) channels and two capture/compare register (cc100, cc101) channels. when the tm10 count value and the set value of one of the compare registers match, a match interrupt (intcm100, intcm101, intcc100 note , intcc101 note ) is output. particularly in the case of interval operation, tm10 is cleared upon generat ion of the intcm100 interrupt. note this match interrupt is generated when cc100 and cc 101 are set to the compare register mode. (d) capture function tm10 connects two capture/compare regi ster (cc100, cc101) channels. when cc100 and cc101 are set to the capture regist er mode, the value of tm10 is captured in synchronization with the corresponding capture trigger signal. furthermore, an interrupt request signal (intcc100, intcc101) is generated by the valid edge of the intp100, intp101 input signals specifie d as the capture trigger signals.
chapter 9 timer/counter function 311 user?s manual u15195ej5v0ud table 9-7. capture trigger signal (t m10) to 16-bit capture register capture register capture trigger signal cc100 intp100 cc101 intp100 or intp101 remark cc100 and cc101 are capture/compare registers. which of these registers is used is specified by capture/compare c ontrol register 0 (ccr0). the valid edge of the capture tri gger is specified by signal edge selection register 10 (sesa10). if both the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the input pulse width externally. if a single edge is sele cted as the capture trigger, the input pulse cycle can be measured. (e) pwm output operation pwm output operation is performed from the to10 pi n by setting tm10 to the general-purpose timer mode (cmd bit = 0) using timer unit mode register 0 (tum0). the resolution is 16 bits, and t he count clock can be selected from among seven internal clocks (f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, f clk /128). figure 9-49. tm10 block diagram (d uring pwm output operation) tm10 (16 bits) compare register (cm100) compare register (cm101) s intcm100 intcm101 alvt10 tum0 register clear 16 16 to10 q r f clk /2 f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 f clk /128 caution be sure to set the count cl ock of tm10 to 10 mhz or lower. remark f clk : base clock
chapter 9 timer/counter function 312 user?s manual u15195ej5v0ud (i) description of operation the cm100 register is a compare register used to se t the pwm output cycle. when the value of this register matches the value of tm10, the intcm100 interrupt is generated. the compare match is saved by hardware, and tm10 is cleared at the next count clock after the match. the cm101 register is a compare register used to set the pwm output duty. set the duty required for the pwm cycle. figure 9-50. pwm signal output e xample (when alvt10 bit = 0 is set) cm100 set value cm101 set value tm10 to10 intcm100 intcm101 cautions 1. changing the values of the cm100 and cm101 registers is prohibited during tm10 operation (tm1ce0 bit of tmc10 register = 1). 2. changing the value of the alvt10 bit of the tum0 register is prohibited during tm10 operation. 3. pwm signal output is performed from th e second pwm cycle after the tm1ce0 bit is set (to 1).
chapter 9 timer/counter function 313 user?s manual u15195ej5v0ud (2) operation in udc mode (a) overview of operation in udc mode the count clock input to tm10 in the udc mode (cmd bi t of tum0 register = 1) can only be externally input from the tiud10 and tcud10 pins. up/dow n count judgment in the udc mode is determined based on the phase difference of the tiud10 and tcud 10 pin inputs according to the prm10 register setting (there is a total of four choices). table 9-8. list of count operations in udc mode prm10 register prm12 prm11 prm10 operation mode tm10 operation 1 0 0 mode 1 down count when tcud10 = high level up count when tcud10 = low level 1 0 1 mode 2 up count upon detection of valid edge of tiud10 input down count upon detection of valid edge of tcud10 input 1 1 0 mode 3 up count upon detection of valid edge of tiud10 input when tcud10 = high level down count upon detection of valid edge of tiud10 input when tcud10 = low level 1 1 1 mode 4 automatic judgment upon detection of both edges of tiud10 input and both edges of tcud10 input the udc mode is further divided into two modes a ccording to the tm10 clear conditions (a count operation is performed only with tiud10 and tcud10 input in both modes). ? udc mode a (tum0 register?s cmd bit = 1, msel bit = 0) the tm10 clear source can be selected as only external clear input (tclr10), a match signal between the tm10 count value and the cm100 set val ue during up count operation, or the logical sum (or) of the two signals, using bits clr1 and cl r0 of the tmc10 register. tm10 can transfer the value of cm100 upon occurrence of a tm10 underflow. ? udc mode b (tum0 register?s cmd bit = 1, msel bit = 1) the status of tm10 after a match of the tm10 count value and cm100 set value is as follows. <1> in the case of an up count operation, tm10 is cleared (0000h), and the intcm100 interrupt is generated. <2> in the case of a down count operati on, the tm10 count value is decremented ( ? 1). the status of tm10 after a match of the tm10 count value and cm101 set value is as follows. <1> in the case of an up count operation, t he tm10 count value is incremented (+1). <2> in the case of a down count operation, tm10 is cleared (0000h), and the intcm101 interrupt is generated.
chapter 9 timer/counter function 314 user?s manual u15195ej5v0ud (b) up/down count operation in udc mode tm10 up/down count judgment in the udc mode is determined based on the phase difference of the tiud10 and tcud10 pin inputs according to the prm10 register setting. (i) mode 1 (prm10 register?s prm12 bit = 1, prm11 bit = 0, prm10 bit = 0) in mode 1, the following count operations are performed based on the level of t he tcud10 pin upon detection of the valid edge of the tiud10 pin. ? tm10 down count operation when tcud10 pin = high level ? tm10 up count operation when tcud10 pin = low level figure 9-51. mode 1 (when rising edge is specified as valid edge of tiud10 pin) tiud10 tcud10 tm10 0006h 0007h down count up count 0005h 0004h 0005h 0006h 0007h figure 9-52. mode 1 (when rising edge is specified as valid edge of tiud10 pin): in case of simultaneous tcud10, tcud10 pin edge timing 0007h tiud10 tcud10 tm10 0006h down count up count 0005h 0004h 0005h 0006h 0007h
chapter 9 timer/counter function 315 user?s manual u15195ej5v0ud (ii) mode 2 (prm10 register?s prm12 bit = 1, prm11 bit = 0, prm10 bit = 1) the count conditions in mode 2 are as follows. ? tm10 up count upon detection of valid edge of tiud10 pin ? tm10 down count upon detection of valid edge of tcud10 pin caution if the count clock is simultaneously input to the tiud10 pin and the tcud10 pin, count operation is not performed and the immediately preceding value is held. figure 9-53. mode 2 (when rising edge is speci fied as valid edge of tiud10, tcud10 pins) 0006h tiud10 tcud10 tm10 0007h 0008h up count hold value down count 0007h 0006h 0005h (iii) mode 3 (prm10 register?s prm12 = 1, prm11 = 1, prm10 = 0) in mode 3, when two signals 90 degrees out of phas e are input to the tiud10 and tcud10 pins, the level of the tcud10 pin is sampled at the input of the valid edge of the tiud10 pin (refer to figure 9-54 ). if the tcud10 pin level sampled at the valid edge input to the tiud10 pin is low, tm10 counts down when the valid edge is input to the tiud10 pin. if the tcud10 pin level sampled at the valid edge input to the tiud10 pin is high, tm10 counts up when the valid edge is input to the tiud10 pin. figure 9-54. mode 3 (when rising edge is specified as valid edge of tiud10 pin) 0007h tiud10 tcud10 tm10 0008h up count down count 0009h 000ah 0009h 0008h 0007h
chapter 9 timer/counter function 316 user?s manual u15195ej5v0ud figure 9-55. mode 3 (when rising edge is specified as valid edge of tiud10 pin): in case of simultaneous tiud 10, tcud10 pin edge timing 0007h tiud10 tcud10 tm10 0008h up count down count 0009h 000ah 0009h 0008h 0007h (iv) mode 4 (prm10 register?s prm 12 = 1, prm11 = 1, prm10 = 1) in mode 4, when two signals out of phase are input to the tiud10 and tcud10 pins, up/down operation is automatically judged and counting is performed according to the timing shown in figure 9-56 . in mode 4, counting is executed at both the rising and falling edges of the two signals input to the tiud10 and tcud10 pins. theref ore, tm10 counts four times per cycle of an input signal ( 4 count). figure 9-56. mode 4 tiud10 tcud10 tm10 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h up count down count cautions 1. when mode 4 is speci fied as the operation mode of tm10, the valid edge specifications for the tiud10 and tcud10 pins are not valid. 2. if the tiud10 pin edge and tcud10 pin edge are input simultaneously in mode 4, tm10 continues the same count operation (up or down) it was performing i mmediately before the input.
chapter 9 timer/counter function 317 user?s manual u15195ej5v0ud (c) operation in udc mode a (i) interval operation the operations at the count clock following a match of the tm10 count value and the cm100 set value are as follows. ? in case of up count operation: tm10 is cleared (0 000h) and the intcm100 interrupt is generated. ? in case of down count operation: the tm10 count value is decremented ( ? 1) and the intcm100 interrupt is generated. remark the interval operation can be combin ed with the transfer operation. (ii) transfer operation if tm10 becomes 0000h during down counting when th e rlen bit of the tmc10 register is 1, the cm100 register set value is transferred to tm10 at the next count clock. remarks 1. transfer enable/disable can be set using the rlen bit of the tmc10 register. 2. the transfer operation can be combin ed with the interval operation. figure 9-57. example of tm10 operation when interval operation and transfer operation are combined tm10 and cm100 match & timer clear tm10 underflow & cm100 data transfer tm10 count value cm100 set value up count down count 0000h (iii) compare function tm10 connects two compare register (cm100, cm1 01) channels and two capture/compare register (cc100, cc101) channels. when the tm10 count value and the set value of one of the compare registers match, a match interrupt (intcm100, intcm101, intcc100 note , intcc101 note ) is output. note this match interrupt is generated when cc100 and cc101 are set to the compare register mode. (iv) capture function tm10 connects two capture/compare regi ster (cc100, cc101) channels. when cc100 and cc101 are set to the capture regist er mode, the value of tm10 is captured in synchronization with the corresponding capture tr igger signal. a capture interrupt (intcc100, intcc101) is generated upon detec tion of the valid edge.
chapter 9 timer/counter function 318 user?s manual u15195ej5v0ud (d) operation in udc mode b (i) basic operation the operations at the nex t count clock after the count value of tm10 and the cm100 set value match when tm10 is in udc mode b are as follows. ? in case of up count operation: tm10 is cleared (0 000h) and the intcm100 interrupt is generated. ? in case of down count operation: the tm10 count value is decremented ( ? 1). the operations at the nex t count clock after the count value of tm10 and the cm101 set value match when tm10 is in udc mode b are as follows. ? in case of up count operation: the tm10 count value is incremented (+1). ? in case of down count operation: tm10 is cleared (0000h) and the intcm101 interrupt is generated. figure 9-58. example of tm10 operation in udc mode cm100 set value cm101 set value tm10 count value clear tm10 not cleared if count clock counts down following match clear tm10 not cleared if count clock counts up following match (ii) compare function tm10 connects two compare register (cm100, cm1 01) channels and two capture/compare register (cc100, cc101) channels. when the tm10 count value and the set value of one of the compare registers match, a match interrupt (intcm100 (only during up count operation), intcm101 (only during down count operation), intcc100 note , intcc101 note ) is output. note this match interrupt is generated when cc100 and cc101 are set to the compare register mode. (iii) capture function tm10 connects two capture/compare regi ster (cc100, cc101) channels. when cc100 and cc101 are set to the capture regist er mode, the value of tm10 is captured in synchronization with the corresponding capture tr igger signal. a capture interrupt (intcc100, intcc101) is generated upon detec tion of the valid edge.
chapter 9 timer/counter function 319 user?s manual u15195ej5v0ud 9.2.6 supplementary descript ion of internal operation (1) clearing of count value in udc mode b when tm10 is in udc mode b, the conditions to clear the count value are as follows. ? in case of tm10 up-count operation: tm10 count value is cleared upon match with the cm100 register ? in case of tm10 down-count operation: tm10 count value is cleared upon match with the cm101 register figure 9-59. clear operation after match of cm100 register set value and tm10 count value (a) up count up count count clock (rising edge set as valid edge) cm100 register fffeh tm10 cleared tm10 ffffh 0000h 0001h ffffh up count up count (b) up count down count count clock (rising edge set as valid edge) cm100 register fffeh tm10 not cleared tm10 ffffh fffeh fffdh ffffh up count down count
chapter 9 timer/counter function 320 user?s manual u15195ej5v0ud figure 9-60. clear operation after match of cm101 register set value and tm10 count value (a) down count down count count clock (rising edge set as valid edge) cm101 register 00ffh tm10 cleared tm10 00feh 0000h ffffh 00feh down count down count (b) down up count count clock (rising edge set as valid edge) cm101 register 00ffh tm10 not cleared tm10 00feh 00ffh 0100h 00feh down count up count (2) transfer operation if tm10 becomes 0000h during down counting when the rlen bit of the tmc10 register is 1 in udc mode a, the set value of the cm100 register is transferred to tm10 at the next count clock. the transfer operation is not performed during up counting. figure 9-61. internal operat ion during transfer operation count clock (rising edge set as valid edge) cm100 register 0001h transfer operation performed. tm10 0000h cm100 set value cm100 set value ? 1 ffffh down count down count
chapter 9 timer/counter function 321 user?s manual u15195ej5v0ud (3) interrupt signal outpu t upon compare match an interrupt signal is output when the count value of tm10 matches the set value of the cm100, cm101, cc100 note , or cc101 note register. the interrupt generation timing is as follows. note when cc100 and cc101 are set to the compare register mode. figure 9-62. interrupt output upon compare match (cm101 with operation mode set to general-purpose timer mode and count clock set to f clk /2) count clock f clk cm101 0007h tm10 internal match signal intcm101 0008h 000bh 0009h 0009h 000ah remark f clk : base clock an interrupt signal such as the one illustrated in figu re 9-62 is output at the next count clock following a match of the tm10 count value and the set val ue of the corresponding compare register. (4) tm1ubd0 flag (bit 0 of status0 register) operation in the udc mode (cmd bit of tum0 register = 1), the tm1ubd0 flag changes as follows during tm10 up/down count operation at every internal operation clock. figure 9-63. tm1ubd0 flag operation count clock tm1ubd0 0001h 0000h tm10 0000h 0001h 0001h 0000h
chapter 9 timer/counter function 322 user?s manual u15195ej5v0ud 9.3 timer 2 9.3.1 features (timer 2) timers 20 and 21 (tm20, tm21) are 16-bit general-purpos e timer units that perform the following operations. ? pulse interval or frequency measurement and programmable pulse output ? interval timer ? pwm output timer ? 32-bit capture timer when 2 timer/count er channels are connected in cascade (in this case, four 32-bit captur e register channels can be used.) 9.3.2 function overview (timer 2) ? 16-bit timer/counter (tm20, tm21): 2 channels ? bit length timer 2 registers (tm20, tm21): 16 bits during cascade operation: 32 bits (higher 16 bits: tm21, lower 16 bits: tm20) ? capture/compare register in 16-bit mode: 6 in 32-bit mode: 4 (capture mode only) ? count clock division selectable by prescaler (set the frequency of the count clock to 10 mhz or less) ? base clock (f clk ): 1 type (set f clk to 20 mhz or less) f xx /2 ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). division ratio base clock (f clk ) 1/2 f xx /4 1/4 f xx /8 1/8 f xx /16 1/16 f xx /32 1/32 f xx /64 1/64 f xx /128 1/128 f xx /256
chapter 9 timer/counter function 323 user?s manual u15195ej5v0ud ? interrupt request sources ? compare-match interrupt request: 6 types perform comparison with subchannel n capture/compare register and generate the intcc2n interrupt upon compare match. ? timer/counter overflow interrupt request: 2 types the inttm20 (inttm21) interrupt is generated when t he count value of tm20 (tm21) becomes ffffh. ? capture request the count values of tm20 and tm21 can be latched using an external pin (intp2n) notes 1, 2 , tm10 interrupt signals (intcm100, intcm101) and interrupt r equests by software as capture triggers. ? pwm output function control of the output of t he to21 to to24 pins in the compare mode and pwm output can be performed using the compare match timing of subchannels 1 to 4 and the zero count signal of the timer/counter. ? timer count operation with external clock input note 2 timer count operation can be performed usin g the pin ti2 clock input signal. ? timer count enable operation note 3 with external pin input note 2 timer count enable operation can be perform ed using the tclr2 pin input signal. ? timer/counter clear control notes 3, 4 with external pin input note 2 timer/counter clear operation can be perform ed using the tclr2 pin input signal. ? up/down count control notes 3, 5 with external pin input note 2 up/down count operation in the compare mode can be controlled using the tclr2 pin input signal. ? output delay operation a clock-synchronized output delay can be added to t he output signal of the to21 to to24 pins. this is effective as an emi countermeasure. ? input filter an input filter can be inserted at the input stage of external pins (t i2, intp20 to intp25, tclr2) and the tm10 interrupt signals (refer to 12.5.3 (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) ). notes 1. for the registers used to specify the valid edge fo r external interrupt requests (intp20 to intp25) to timer 2, refer to 7.3.8 (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) . 2. the pairs ti2 and intp20, to21 and intp21, to22 and intp22, to23 and intp23, to24 and intp24, tclr2 and intp25 are alternate function pins. 3. the count enable operation for the timer/counter vi a external pin input, timer/counter clear operation, and up/down count control cannot be perf ormed all at the same time. 4. in the case of 32-bit cascade connection, a clear operation by external pin input (tclr2) cannot be performed. 5. up/down count control using 32-bit ca scade connection cannot be performed. remark f xx : internal system clock n = 0 to 5
chapter 9 timer/counter function 324 user?s manual u15195ej5v0ud 9.3.3 basic configuration the basic configuration is shown below. table 9-9. timer 2 configuration list timer count clock register read/write generated interrupt signal capture trigger other functions tm20 ? inttm20 ? note 1 tm21 ? inttm21 ? note 1 cvse00 read/write intcc20 intp20/intp25 ? cvse10 read/write intcc21 intp21/intp24 buffer/ note 2 cvse20 read/write intcc22 intp22/intp23 buffer/ note 2 cvse30 read/write intcc23 intp23/intp22 buffer/ note 2 cvse40 read/write intcc24 intp24/intp21 buffer/ note 2 cvse50 read/write intcc25 intp25/intp20 ? cvpe40 read intcc24 intp24/intp21 note 2 cvpe30 read intcc23 intp23/intp22 note 2 cvpe20 read intcc22 intp22/intp23 note 2 timer 2 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 cvpe10 read intcc21 intp21/intp24 note 2 notes 1. cascade operation with tm20 and tm21 is possible. 2. cascade operation using the cvsen0 and cvpen0 registers is possible (n = 1 to 4). remark f xx : internal system clock the following shows the capture/ compare operation sources. table 9-10. capture/compare operation sources register subchannel no. timer to be captured timer to be compared timer captured in 32-bit cascade connection cvse00 0 tm20 tm20 ? cvpen0 n tm21 when bfeey bit of cmsem0 register = 0 tm20 when tb1ey, tb0ey bits of cmsem0 register = 01 tm21 cvsen0 n tm20 when bfeey bit of cmsem0 register = 0 used as buffer tm20 cvse50 5 tm21 tm21 ? remark n = 1 to 4 m: m = 12 when n = 1, 2, m = 34 when n = 3, 4 y: y = 1, 2 when m = 12, y = 3, 4 when m = 34
chapter 9 timer/counter function 325 user?s manual u15195ej5v0ud the following shows the output level sources during timer output. table 9-11. output level s ources during timer output to2n toggle mode 0 (otmen1, otmen0 = 00) toggle mode 1 (otmen1, otmen0 = 01) toggle mode 2 (otmen1, otmen0 = 10) toggle mode 3 (otmen1, otmen0 = 11) trigger compare match of sub- channel n compare match of sub- channel n tm20 = 0 compare match of sub- channel n tm21 = 0 compare match of sub- channel n compare match of sub- channel n + 1 output level active output inactive output active output inactive output active output inactive output active output inactive output remarks 1. n = 1 to 4 2. otmen1, otmen0: bits 13, 12, 9, 8, 5, 4, 1, and 0 of timer 2 out put control register 0 (octle0)
chapter 9 timer/counter function 326 user?s manual u15195ej5v0ud figure 9-64 shows the block diagram of timer 2. figure 9-64. block di agram of timer 2 ed1 eclr cnt = max. cnt = 0 r cnt = max. cnt = 0 r ct ed2 s/t ra rb rn output circuit 1 s/t ra rb rn output circuit 2 s/t ra rb rn output circuit 3 ed1 reload2a reload2b ed2 ed1 eclr ct ctc casc ed2 subchannel 4 cvse40 (16-bit) cvpe40 (16-bit) ed1 reload2a reload2b ed2 subchannel 1 cvse10 (16-bit) cvpe10 (16-bit) ed1 reload2a reload2b ed2 subchannel 2 cvse20 (16-bit) cvpe20 (16-bit) ed1 reload2a reload2b ed2 subchannel 3 cvse30 (16-bit) cvpe30 (16-bit) s/t ra rb rn output circuit 4 cvse00 (16-bit) tm20 (16-bit) intcc20 intcc21 intcc22 intcc23 intcc24 intcc25 inttm20 to21 to22 to23 to24 inttm21 cvse50 (16-bit) tm21 (16-bit) tine5 edge selection tine4 edge selection tine3 edge selection tine2 edge selection tine1 edge selection tine0 edge selection input filter input filter input filter input filter input filter input filter timer connection selector tcounte1 edge selection tcounte0 f clk edge selection tclr2/ intp25 ti2/ intp20 f xx /2 intp24 intp23 intp22 intp21 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 subchannel 5 subchannel 0 selector selector selector remark f xx : internal system clock f clk : base clock (20 mhz (max.))
chapter 9 timer/counter function 327 user?s manual u15195ej5v0ud table 9-12. meaning of si gnals in block diagram signal name meaning casc note 1 tm21 count signal input in 32-bit mode cnt count value of timer 2 (cnt = max.: maximu m value count signal output of timer 2 (generated when tm2n = ffffh), cnt = 0: zero count signal output of timer 2 (generated when tm2n = 0000h)) ct tm2n count signal input in 16-bit mode ctc tm21 count signal input in 32-bit mode eclr external control signal input from tclr2 input ed1, ed2 capture event signal input from edge selector r note 2 compare match signal input (subchannel 0/5) ra tm20 zero count signal input (reset signal of output circuit) rb tm21 zero count signal input (reset signal of output circuit) reload2a tm20 zero count signal input (generated when tm20 = 0000h) reload2b tm21 zero count signal input (generated when tm21 = 0000h) rn subchannel x interrupt signal inpu t (reset signal of output circuit) s/t subchannel x interrupt signal inpu t (set signal of output circuit) tcounte0, tcounte1 timer 2 count enable signal input tinem timer 2 subchannel m capture event signal input notes 1. tm21 performs a count operation when casc (cnt = max. for tm20) is generated and the rising edge of ctc is detected in the 32-bit mode. 2. tm20/tm21 clear by subchannel 0/5 compare matc h or count direction can be controlled. remark m = 0 to 5 n = 0, 1 x = 1 to 4
chapter 9 timer/counter function 328 user?s manual u15195ej5v0ud (1) timers 20, 21 (tm20, tm21) the features of tm2n are listed below. ? free-running counter that enables counter clearing by compare match of subchannel 0 and subchannel 5 ? can be used as a 32-bit capture timer when tm20 and tm21 are connected in cascade. ? up/down control, counter clear, and count operation enable/disable can be controlled by external pin (tclr2) ? counter up/down and clear operation cont rol method can be set by software. ? stop upon occurrence of count value 0 and count oper ation start/stop can be controlled by software. (2) timer 2 subchannel 0 capture /compare register (cvse00) the cvse00 register is the 16-bit captur e/compare register of subchannel 0. in the capture register mode, it captures the tm20 count value. in the compare register mode, it detects a match with tm20. this register can be read/written in 16-bit units. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse00 address fffff660h after reset 0000h (3) timer 2 subchannel n main capture/compare register (cvpen0) (n = 1 to 4) the cvpen0 register is the subchannel n 16 -bit main capture/compare register. in the capture register mode, this register captures the value of tm 21 when the bfeen bit of the cmsem0 register = 0 (m = 12, 34). when the bfeen bit = 1, th is register holds the value of tm20 or tm21. in compare register mode, a match between this r egister and tm2x is detected (tm2x = timer/counter selected by tb1en and tb0en bits). if the capture register mode is selected in the 32-bit mode (value of tb1en, tb0en bits of cmsem0 register = 11b), this register captures the contents of tm21 (higher 16 bits). this register is read-only, in 16-bit units. caution when the bfeen bit = 1, a compare match occurs on star ting the timer in the compare register mode because the values of both th e tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits (n = 1 to 4)). after that, the value of the sub register (cvsen0) is wri tten to the main register (cvpen0). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe10 address fffff652h after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe20 address fffff656h after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe30 address fffff65ah after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvpe40 address fffff65eh after reset 0000h
chapter 9 timer/counter function 329 user?s manual u15195ej5v0ud (4) timer 2 subchannel n sub capture/compare register (cvsen0) (n = 1 to 4) the cvsen0 register is the subchannel n 16-bit sub capture/compare register. in the compare register mode, this register can be us ed as a buffer. in the capture register mode, this register captures the value of tm20 when the bfeen bit of the cm sem0 register = 0 (m = 12, 34). if the capture register mode is selected in the 32- bit mode (value of tb1en and tb0en bits of cmsem0 register = 11b), this register captures the contents of tm20 (lower 16 bits). the cvsen0 register can be written on ly in the compare register mode. if this register is written in the capture register mode, t he contents written to cvsen0 register will be lost. this register can be read/written in 16-bit units. caution when the bfeen bit = 1, a compare match occurs on star ting the timer in the compare register mode because the values of both th e tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits (n = 1 to 4)). after that, the value of the sub register (cvsen0) is wri tten to the main register (cvpen0). 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse10 address fffff650h after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse20 address fffff654h after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse30 address fffff658h after reset 0000h 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse40 address fffff65ch after reset 0000h (5) timer 2 subchannel 5 capture /compare register (cvse50) the cvse50 register is the 16-bit captur e/compare register of subchannel 5. in the capture register mode, it c aptures the count value of tm21. in the compare register mode, it detects a match with tm21. this register can be read/written in 16-bit units. 14 13 12 2 3 4 5 6 7 8 9 10 11 15 10 cvse50 address fffff662h after reset 0000h
chapter 9 timer/counter function 330 user?s manual u15195ej5v0ud 9.3.4 control registers (1) timer 1/timer 2 clock sel ection register (prm02) the prm02 register is used to select the base clock (f clk ) of timer 1 and timer 2. this register can be read/written in 8-bit or 1-bit units. cautions 1. always set this register to 01h before using timer 1 and timer 2. setting of other than 01h is prohibited. 2. set f clk to 20 mhz or less. 7 0 prm02 6 0 5 0 4 0 3 0 2 0 1 0 0 prm2 address fffff5d8h after reset 00h bit position bit name function 0 prm2 specifies the base clock (f clk ) of timer 1 and timer 2. 1: f clk = f xx /2 remark f xx : internal system clock (2) timer 2 clock stop register 0 (stopte0) the stopte0 register is used to stop t he operation clock input to timer 2. this register can be read/written in 16-bit units. when the higher 8 bits of the stopte0 register are used as the stopte0h register, and the lower 8 bits are used as the stopte0l register, the stopte0h regist er can be read/written in 8-bit or 1-bit units, and the stopte0l register is read-only, in 8-bit units. cautions 1. initialize timer 2 when the stfte bit = 0. timer 2 cannot be initialized when the stfte bit = 1. 2. if, following initialization, the value of the stfte bit is made ?1?, the initialized state is maintained. 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 <15> stfte 1 0 0 0 stopte0 address fffff640h after reset 0000h bit position bit name function 15 stfte stops the operation clock to timer 2. 0: normal operation 1: stop operation clock to timer 2
chapter 9 timer/counter function 331 user?s manual u15195ej5v0ud (3) timer 2 count clock/control e dge selection register 0 (cse0) the cse0 register is used to specify the tm2n coun t clock and the control valid edge (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the cse0 register are used as the cse0h register, and the lower 8 bits are used as the cse0l register, they can be read/written in 8-bit or 1-bit units. 14 0 13 0 12 0 2 cse02 3 cse10 4 cse11 5 cse12 6 cese0 7 cese1 8 tes0e0 9 tes0e1 10 tes1e0 11 tes1e1 15 0 1 cse01 0 cse00 cse0 address fffff642h after reset 0000h bit position bit name function specifies the valid edge of the tm2n inte rnal count clock (tcounten) signal. tesne1 tesne0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges note 11, 10, 9, 8 tesne1, tesne0 specifies the valid edge of the tm2n external clear input (tclr2). cese1 cese0 valid edge 0 0 falling edge 0 1 rising edge 1 0 through input (no clear operation) 1 1 both rising and falling edges 7, 6 cese1, cese0 selects internal count clock (tcounten) of tm2n. csen2 csen1 csen0 count clock 0 0 0 f clk /2 note 0 0 1 f clk /4 0 1 0 f clk /8 0 1 1 f clk /16 1 0 0 f clk /32 1 0 1 f clk /64 1 1 0 f clk /128 1 1 1 selects input signal from external clock input pin (ti2) as clock. 5 to 3, 2 to 0 csen2, csen1, csen0 note setting tesne1, tesne0 = 11b and csen2 to csen0 = 000b at the same time is prohibited. remark n = 0, 1 f clk : base clock
chapter 9 timer/counter function 332 user?s manual u15195ej5v0ud (4) timer 2 subchannel input event e dge selection register 0 (sese0) the sese0 register specifies the valid edge of the external capture signal input (tinen) for the subchannel n capture/compare register performing capture (n = 0 to 5). this register can be read/written in 16-bit units. when the higher 8 bits of the sese0 re gister are used as the sese0h register, and the lower 8 bits are used as the sese0l register, they can be read/ written in 8-bit or 1-bit units. 14 0 13 0 12 0 2 iese10 3 iese11 4 iese20 5 iese21 6 iese30 7 iese31 8 iese40 9 iese41 10 iese50 11 iese51 15 0 1 iese01 0 iese00 sese0 address fffff644h after reset 0000h bit position bit name function specifies the valid edge of external capture signal input (tinen) for subchannel n capture/compare register performing capture. iesen1 iesen0 valid edge 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges 11 to 0 iesen1, iesen0 remark n = 0 to 5
chapter 9 timer/counter function 333 user?s manual u15195ej5v0ud (5) timer 2 time base control register 0 (tcre0) the tcre0 register controls the op eration of tm2n (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the tcre0 register are used as the tcre0h register, and the lower 8 bits are used as the tcre0l register, they can be read/written in 8-bit or 1-bit units. cautions 1. if ecren = 1 and eceen = 1 have been se t, it is not possible to input an external clear signal (tclr2) for tm2n. in this case, first set clren = 1, and then clear tm2n by software (n = 0, 1). 2. when clearing is performed using the ec lr signal, the tm2n counter is cleared with a delay of (1 internal count clock set with bits csen2 to csen0 of the cse0 register) + 2 base clocks. therefore, if external clock inpu t is selected as the in ternal count clock, the counter is not cleared until the external clock (ti2) is input. 3. the ecren bit and the eceen bit cannot be set to 1. 4. if the eceen bit is set to 1 and the ecre n bit is set to 0, a down count operation cannot be performed. 5. when udsen1, udsen0 = 01 and osten = 1, the counter does not count up when the counter value is 0. therefore, when the count er value is 0, set osten = 0, and after the value of the counter ceases to be 0, set osten = 1. also, on the application, change the value of osten from 0 to 1 using the su bchannels 0 and 5 in terrupt signals. 6. when the tm2n count value is cleared (0) by setting clre n to 1, the clren = 1 setting must be held for at least on e of the internal count clocks set by the csen2 to csen0 bits of the cse0 register. example when timer 20 (tm20) is cleared (0) <1> select f clk /2 as tm20 internal count clock 14 0 13 0 12 0 2 0 3 4 5 6 7 8 9 10 11 15 0 1 0 0 0 cse0 <2> clear (0) the tm20 count value 6 1 5 0 4 0 0 1 2 3 0 7 0 tcre0l <3> set the conditions required for the tm20 count clock 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 cse0 <4> start the tm20 count operation 6 0 5 1 4 0 0 1 2 3 0 7 0 tcre0l
chapter 9 timer/counter function 334 user?s manual u15195ej5v0ud (1/2) <14> clre1 <13> cee1 12 ecre1 2 oste0 3 ecee0 4 ecre0 <5> cee0 <6> clre0 7 0 8 udse10 9 udse11 10 oste1 11 ecee1 15 case1 1 udse01 0 udse00 tcre0 address fffff646h after reset 0000h bit position bit name function 15 case1 specifies 32-bit cascade operation mode for tm21 (tm21 counts upon overflow of tm20 (carry count)). 0: not connected in cascade note 1 1: 32-bit cascade operation mode notes 2, 3 notes 1. tm21 counts at ct signal input in the count enabled state. 2. tm21 counts at ctc and casc signal inputs in the count enabled state. 3. only the capture register mode can be used for the capture/compare register. cautions 1. when case1 = 1, set the tbye1 and tbye0 bits of the cmsex0 register to 11 (x = 12, 34, y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4). 2. when case1 = 0, tcounte1 is selected as the count of tm21. when case1 = 1, tcounte0 and the tm20 overflow signal are selected as the count of tm21. 14, 6 clren specifies software clear for tm2n. 0: tm2n operation continued 1: tm2n count value cleared (0) caution do not perform the software clear and hardware clear operations simultaneously. 13, 5 ceen specifies tm2n count operation enable/disable. 0: count operation stopped 1: count operation enabled 12, 4 ecren specifies tm2n external clear (t clr2) operation enable/disable via eclr signal input. 0: tm2n external clear (tclr2) operation not enabled 1: tm2n external clear (tclr2) operation enabled cautions 1. in the 32-bit cascade operation mode (case1 = 1), the tm2n external clear operation is not performed. 2. when the count value is cleared by inputting the eclr signal while ecren = 1, the ecren = 1 setting must be held for at least one of the internal count clocks set by the csen2 to csen0 bits of the cse0 register. 3. in the 32-bit cascade operation mode (case1 = 1), only tm21 is affected by the ecren bit setting. remark n = 0, 1
chapter 9 timer/counter function 335 user?s manual u15195ej5v0ud (2/2) bit position bit name function 11, 3 eceen specifies tm2n count operation enable/disable through eclr signal input. 0: tm2n count operation not enabled 1: tm2n count operation enabled cautions 1. in the 32-bit cascade operation mode (case1 = 1), the tm2n count operation using eclr signal input is not performed. 2. when the eceen bit = 1, always set the cese1 and cese0 bits of the cse0 register to 10 (through input). 3. in the 32-bit cascade operation mode (case1 = 1), only tm21 is affected by the eceen bit setting. 10, 2 osten specifies stop mode. 0: tm2n count stopped when count value is 0. 1: tm2n count not stopped when count value is 0. caution when the tm2n count stop is cancelled when the oste1n bit = 1 (tm2n count is stopped when the count value is 0), tm2n counts up except when the udsen1, udsen0 bits = 10. the count direction when the udsen1 and udsen0 bits = 10 is determined by the value of eclr . specifies tm2n up/down count. udsen1 udsen0 count 0 0 perform only up count. clear tm2n with compare match signal. 0 1 count up after tm2n has become 0, and count down after a compare match occurs for subchannels 0, 5 (triangular wave up/down count). 1 0 selects up/down count according to the eclr signal input. up count when eclr = 1 down count when eclr = 0 1 1 setting prohibited 9, 8, 1, 0 udsen1, udsen0 cautions 1. in the 32-bit cascade operation mode (case1 bit = 1), set the udsen1 and udsen0 bits to 00. 2. when the udsen1 and udsen0 bits = 10, be sure to set the cese1 and cese0 bits of the cse0 register to 10 (through input). 3. when the udsen1 and udsen0 bits = 10, compare match between tm2n and cvsex0 has no effect on the tm2n count operation (x: 0 when n = 0, 5 when n = 1). remark n = 0, 1
chapter 9 timer/counter function 336 user?s manual u15195ej5v0ud (6) timer 2 output control register 0 (octle0) the octle0 register controls timer output from the to2n pin (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the octl e0 register are used as a octle0h register, and the lower 8 bits are used as a octle0l register, they can be read/written in 8-bit or 1-bit units. 14 alve 4 13 otme 41 12 otme 40 2 alve 1 3 swfe 1 4 otme 20 5 otme 21 6 alve 2 7 swfe 2 8 otme 30 9 otme 31 10 alve 3 11 swfe 3 15 swfe 4 1 otme 11 0 otme 10 octle0 address fffff648h after reset 0000h bit position bit name function 15, 11, 7, 3 swfen fixes the to2n pin output le vel according to the setting of alven bit. 0: output level not fixed. 1: when alven = 0, output level fixed to low level. when alven = 1, output level fixed to high level. 14, 10, 6, 2 alven specifies the active level of the to2n pin output. 0: active level is high level 1: active level is low level specifies toggle mode. otmen1 otmen0 toggle mode 0 0 toggle mode 0: reverse output level of to2n output every time a subchannel n compare match occurs. 0 1 toggle mode 1: upon subchannel n compare match, set to2n output to active level, and when tm20 is ?0?, set to2n output to inactive level. 1 0 toggle mode 2: upon subchannel n compare match, set to2n output to active level, and when tm21 is ?0?, set to2n output to inactive level. 1 1 toggle mode 3: upon subchannel n compare match, set to2n output to active level, and upon subchannel n + 1 compare match, set to2n output to inactive level (when n = ?4?, n + 1 becomes ?1?). 13, 12, 9, 8, 5, 4, 1, 0 otmen1, otmen0 cautions 1. when the otmen1 and otmen0 bits = 11 (toggle mode 3), if the same output delay operation settings are made when setting the odlen2 to odlen0 bits of the odele0 register, two outputs change simultaneously upon 1 subchannel n compare match. 2. if two or more signals are input simultaneously to the same output circuit, s/t signal input has a higher priority than ra, rb, and rn signal inputs. remark n = 1 to 4
chapter 9 timer/counter function 337 user?s manual u15195ej5v0ud (a) caution for pwm output change timing if the swfen bit is changed from 1 to 0 when the timer is operating while the internal pwm output operation is being performed, then the output level be comes active. after that, pwm output from the to2n pin is performed upon a compare match at subch annel n. however, the first pwm output change timing varies as follows, depending on the internal output level and the swfen bit clear timing. figure 9-65. pwm output change timing (i) example 1 to2n output (alven bit = 1) pwm output change timing swfen bit internal output level (ii) example 2 to2n output (alven bit = 1) pwm output change timing swfen bit internal output level remark n = 1 to 4
chapter 9 timer/counter function 338 user?s manual u15195ej5v0ud (7) timer 2 subchannel 0, 5 capture/com pare control register (cmse050) the cmse050 register controls the timer 2 subchannel 0 capture/compare register (cvse00) and the timer 2 subchannel 5 capture/compare register (cvse50). this register can be read/written in 16-bit units. 14 0 13 eeve5 12 0 2 ccse0 3 lnke0 4 0 5 eeve0 6 0 7 0 8 0 9 0 10 ccse5 11 lnke5 15 0 1 0 0 0 cmse050 address fffff64ah after reset 0000h bit position bit name function 13, 5 eeven enables/disables event detection by subchannel n capture/compare register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 11, 3 lnken specifies capture event signal i nput from edge selection to ed1 or ed2. 0: in capture register mode, ed1 signal input selected. in compare register mode, lnken bit has no influence. 1: in capture register mode, ed2 signal input selected. in compare register mode, lnken bit has no influence. 10, 2 ccsen selects capture/compare register operation mode. 0: operates in capture register mode . the tm20 and tm21 count statuses can be read with subchannel 0 and subchannel 5, respectively. 1: operates in compare register mode. tm2m is cleared upon detection of match between subchannel n and tm2m. remark m = 0, 1 n = 0, 5
chapter 9 timer/counter function 339 user?s manual u15195ej5v0ud (8) timer 2 subchannel 1, 2 capture/com pare control register (cmse120) the cmse120 register controls the timer 2 subchannel n sub capture/ compare register (cvsen0) and the timer 2 subchannel n main capture/compar e register (cvpen0) (n = 1, 2). this register can be read/written in 16-bit units. (1/2) 14 0 13 eeve2 12 bfee2 2 ccse1 3 lnke1 4 bfee1 5 eeve1 6 0 7 0 8 tb0e2 9 tb1e2 10 ccse2 11 lnke2 15 0 1 tb1e1 0 tb0e1 cmse120 address fffff64ch after reset 0000h bit position bit name function 13, 5 eeven enables/disables event detection for cmse120 register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 12, 4 bfeen specifies the buffer operation of subchannel n sub capture/compare register (cvsen0). 0: subchannel n sub capture/compare register (cvsen0) not used as buffer. 1: subchannel n sub capture/compare register (cvsen0) used as buffer. caution when the bfeen bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits (n = 1 to 4)). after that, the value of the sub register (cvsen0) is writ ten to the main register (cvpen0). remarks 1. the operations in the capture register mode and compare register mode when the subchannel n sub capture/compare register (cvsen0) is not used as a buffer are shown below. ? in capture register mode: the cpu can read both the master register (cvpen0) and slave register (cvse n0). the next event is ignored until the cpu finishes reading the master register. tm20 capture is performed by th e slave register, and tm21 capture is performed by the master register. ? in compare register mode: the cp u writes to the slave register (cvsen0), and immediately after, the same contents as those of the slave register are written to the master register (cvpen0). 2. the operations in the capture register mode and compare register mode when the subchannel n sub capture/compare register (cvsen0) is used as a buffer are shown below. ? in capture register mode: when t he cpu reads the master register (cvpen0), the master register updates the value held by the slave register (cvsen0) immediately before the cpu read operation. when a capture event occurs, the timer/counter value at that time is always saved in the slave register. ? in compare register mode: the cp u writes to the slave register (cvsen0) and these contents are tran sferred to the master register (cvpen0) set by the lnken bits. remark n = 1, 2
chapter 9 timer/counter function 340 user?s manual u15195ej5v0ud (2/2) bit position bit name function 11, 3 lnken selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: ed1 signal input selected in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register upon occurrence of a tm2x compare match (tm2x = timer/counter selected by bits tb1en, tb0en). 1: ed2 signal input selected in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register when the tm2x count value becomes 0 (tm2x = timer/ counter selected by bits tb1en, tb0en). 10, 2 ccsen selects capture/compare register operation mode. 0: capture register mode 1: compare register mode sets subchannel n timer/counter. tb1en tb0en subchannel n timer/counter 0 0 subchannel n not used. 0 1 tm20 set to subchannel n. 1 0 tm21 set to subchannel n. 1 1 32-bit mode note (both tm20 and tm21 selected) 9, 8, 1, 0 tb1en, tb0en note in the 32-bit mode, the effect of the bfeen bit is ignored. also, the cvsen0 register cannot be used as a buffer in this mode. caution when the tb1en, tb0en bits are set to 11, set the case1 bit of the tcre0 register to 1. remark n = 1, 2
chapter 9 timer/counter function 341 user?s manual u15195ej5v0ud (9) timer 2 subchannel 3, 4 capture/com pare control register (cmse340) the cmse340 register controls the timer 2 subchannel n sub capture/ compare register (cvsen0) and the timer 2 subchannel n main capture/compare register (cvpen0). this register can be read/written in 16-bit units. (1/2) 14 0 13 eeve4 12 bfee4 2 ccse3 3 lnke3 4 bfee3 5 eeve3 6 0 7 0 8 tb0e4 9 tb1e4 10 ccse4 11 lnke4 15 0 1 tb1e3 0 tb0e3 cmse340 address fffff64eh after reset 0000h bit position bit name function 13, 5 eeven enables/disables event detection by cmse340 register. 0: ed1 and ed2 signal inputs ignored (not hing is done even if these signals are input). 1: operation caused by ed1 and ed2 signal inputs enabled. 12, 4 bfeen specifies the subchannel n sub capture/compare register (cvsen0) buffer operation. 0: subchannel n sub capture/compare register (cvsen0) not used as buffer 1: subchannel n sub capture/compare register (cvsen0) used as buffer caution when the bfeen bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the tm2x and cvpen0 registers are 0 after reset (tm2x = timer/counter selected by tb1en and tb0en bits (n = 1 to 4)). after that, the value of the sub register (cvsen0) is writ ten to the main register (cvpen0). remarks 1. the operations in the capture register mode and compare register mode when the subchannel n sub capture/compare register (cvsen0) is not used as a buffer are shown below. ? in capture register mode: the cpu can read both the master register (cvpen0) and slave register (cvse n0). the next event is ignored until the cpu finishes reading the master register. tm20 capture is performed by th e slave register, and tm21 capture is performed by the master register. ? in compare register mode: the cp u writes to the slave register (cvsen0), and immediately after, the same contents as those of the slave register are written to the master register (cvpen0). 2. the operations in the capture register mode and compare register mode when the subchannel n sub capture/compare register (cvsen0) is used as a buffer are shown below. ? in capture register mode: when t he cpu reads the master register (cvpen0), the master register updates the value held by the slave register (cvsen0) immediately before the cpu read operation. when a capture event occurs, the timer/counter value at that time is always saved in the slave register. ? in compare register mode: the cp u writes to the slave register (cvsen0) and these contents are tran sferred to the master register (cvpen0) set by the lnken bits. remark n = 3, 4
chapter 9 timer/counter function 342 user?s manual u15195ej5v0ud (2/2) bit position bit name function 11, 3 lnken selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: ed1 signal input selected in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register upon occurrence of a tm2x compare match (tm2x = timer/ counter selected with bits tb1en, tb0en). 1: ed2 signal input selected in capture register mode. in the compare register mode, the data of the cvsen0 register is transferred to the cvpen0 register when the tm2x count value becomes 0 (tm2x = timer/ counter selected by bits tb1en, tb0en). 10, 2 ccsen selects capture/compare register operation mode. 0: capture register mode 1: compare register mode sets subchannel n timer/counter. tb1en tb0en subchannel n timer/counter 0 0 subchannel n not used 0 1 tm20 set to subchannel n. 1 0 tm21 set to subchannel n. 1 1 32-bit mode note (both tm20 and tm21 selected) 9, 8, 1, 0 tb1en, tb0en note in the 32-bit mode, the effect of the bfeen bit is ignored. also, the cvsen register cannot be used as a buffer in this mode. caution when the tb1en, tb0en bits are set to 11, set the case1 bit of the tcre0 register to 1. remark n = 3, 4
chapter 9 timer/counter function 343 user?s manual u15195ej5v0ud (10) timer 2 time base status register 0 (tbstate0) the tbstate0 register indicates t he status of tm2n (n = 0, 1). this register can be read/written in 16-bit units. when the higher 8 bits of the tbstat e0 register are used as the tbstat e0h register, and the lower 8 bits are used as the tbstate0l r egister, they can be read/written in 8-bit or 1-bit units. caution the ecfen, rsfen, and udfen bits are read-only bits. 14 0 13 0 12 0 <2> ecfe0 <3> ovfe0 4 0 5 0 6 0 7 0 <8> udfe1 <9> rsfe1 <10> ecfe1 <11> ovfe1 15 0 <1> rsfe0 <0> udfe0 tbstate0 address fffff664h after reset 0101h bit position bit name function 11, 3 ovfen indicates tm2n overflow status. 0: no overflow 1: overflow caution if write access to the tbstate0 register is performed when an overflow has not been detected, the ovfen bit is cleared (0). 10, 2 ecfen indicates the eclr signal input status. 0: low level 1: high level 9, 1 rsfen indicates the tm2n count status. 0: tm2n is not counting. 1: tm2n is counting (either up or down) 8, 0 udfen indicates the tm2n up/down count status. 0: tm2n is in the down count mode. 1: tm2n is in the up count mode. remark n = 0, 1
chapter 9 timer/counter function 344 user?s manual u15195ej5v0ud (11) timer 2 capture/compare 1 to 4 status register 0 (ccstate0) the ccstate0 register indicates the status of t he timer 2 subchannel sub capture/compare register (cvsen0) and the timer 2 subchannel main capture/ compare register (cvpen0) (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the ccstate0 register are us ed as the ccstate0h register, and the lower 8 bits are used as the ccstate0l register, they c an be read/written in 8-bit or 1-bit units. caution the bffen1 a nd bffen0 bits are read-only bits. <14> cefe4 13 bffe41 12 bffe40 <2> cefe1 3 0 4 bffe20 5 bffe21 <6> cefe2 7 0 8 bffe30 9 bffe31 <10> cefe3 11 0 15 0 1 bffe11 0 bffe10 ccstate0 address fffff666h after reset 0000h bit position bit name function 14, 10, 6, 2 cefen indicates the capt ure/compare event occurrence status. 0: in capture register mode: no capture operation has occurred. in compare register mode: no compare match has occurred. 1: in capture register mode: at least one capture operation has occurred. in compare register mode: at least one compare match has occurred. caution the cefen bit can be cleared (0) by performing a write access to the ccstate0 register when no capture operation or compare match has occurred. when bit manipulation is performed on the cefe1 (cefe3) and cefe2 (cefe4) bits, both bits are cleared. indicates the capture buffer status. bffen1 bffen0 capture buffer status 0 0 no value in buffer 0 1 subchannel n master register (cvpen0) contains a capture value. slave register (cvsen0) does not contain a value. 1 0 both subchannel n master register (cvpen0) and slave register (cvsen0) contain a capture value. 1 1 unused 13, 12, 9, 8, 5, 4, 1, 0 bffen1, bffen0 caution the bffen1 and bffen0 bits return a value only when subchannel n sub capture/compare register (cvsen0) buffer operation (bit bfeen of cmsem0 register = 1) is selected or when capture register mode (bit ccsen of cmsem0 register = 0) is selected. 0 is read when the compare register mode (ccsen bit = 1) is selected. remark m = 12, 34 n = 1 to 4
chapter 9 timer/counter function 345 user?s manual u15195ej5v0ud (12) timer 2 output delay register 0 (odele0) the odele0 register sets the output delay operatio n synchronized with the clock to the to2n pin?s output delay circuit (n = 1 to 4). this register can be read/written in 16-bit units. when the higher 8 bits of the odele0 register are us ed as the odele0h register, and the lower 8 bits are used as the odele0l register, they can be read/written in 8-bit or 1-bit units. 14 odle42 13 odle41 12 odle40 2 odle12 3 0 4 odle20 5 odle21 6 odle22 7 0 8 odle30 9 odle31 10 odle32 11 0 15 0 1 odle11 0 odle10 odele0 address fffff668h after reset 0000h bit position bit name function specifies output delay operation. odlen2 odlen1 odlen0 set output delay operation 0 0 0 output delay operation not performed. 0 0 1 sets output delay of 1 system clock. 0 1 0 sets output delay of 2 system clocks. 0 1 1 sets output delay of 3 system clocks. 1 0 0 sets output delay of 4 system clocks. 1 0 1 sets output delay of 5 system clocks. 1 1 0 sets output delay of 6 system clocks. 1 1 1 sets output delay of 7 system clocks. 14 to 12, 10 to 8, 6 to 4, 2 to 0 odlen2, odlen1, odlen0 remark the odlen2, odlen1, and odlen0 bits are used for emi countermeasures. remark n = 1 to 4
chapter 9 timer/counter function 346 user?s manual u15195ej5v0ud (13) timer 2 software event capture register (csce0) the csce0 register sets capture operation by software in the capture register mode. this register can be read/written in 16-bit units. 14 0 13 0 12 0 2 seve2 3 seve3 4 seve4 5 seve5 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 seve1 0 seve0 csce0 address fffff66ah after reset 0000h bit position bit name function 5 to 0 seven specifies capture operation by software in capture register mode. 0: normal operation continued. 1: capture operation performed. cautions 1. the seven bit ignores the settings of the eeven and the lnken bits of the cmsem0 register. 2. the seven bit is automatically cleared (0) at the end of an event. 3. the seven bit ignores all the internal limitation statuses of the timer 2 unit. remark m = 12, 34, 05 n = 0 to 5
chapter 9 timer/counter function 347 user?s manual u15195ej5v0ud 9.3.5 operation (1) edge detection the edge detection timing is shown below. figure 9-66. edge detection timing f clk 00b 01b 10b 11b muxtb0 ct ed1, ed2 eclr note tinex, tclr2, tcounten note the set values of the tesne1 and tesne0 bits and the cese1 and cese0 bits of the cse0 register, and the iesex1 and iesex0 bits of t he sese0 register are shown. remarks 1. f clk : base clock 2. ct: tm2n count signal input in the 16-bit mode eclr: external control signal input from tclr2 input ed1, ed2: capture event signal input from edge selector muxtb0: tm20 multiplex signal tcounten: timer 2 count enable signal input tinex: timer 2 subchannel x capture event signal input (x = 0 to 5) 3. n = 0, 1 x = 0 to 5
chapter 9 timer/counter function 348 user?s manual u15195ej5v0ud (2) basic operation of timer 2 figures 9-67 to 9-70 show the basic operation of timer 2. figure 9-67. timer 2 up count timing (when tcre0 register?s udsen 1, udsen0 bits = 00b, eceen bit = 0, ecren bit = 0, clren bit = 0, case1 bit = 0) f clk fffdh (stop) fffeh ffffh 0000h 1234h 1235h 0000h (stop) ct cnt r note 2 inttm2n (output) cnt = 0 osten bit note 1 ceen bit note 1 notes 1. bits oste, cee of tcre0 register 2. can control tm20/tm21 clear by subchannel 0/5 compare match or count direction. remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode r: compare match signal input (subchannel 0/5) 3. n = 0, 1
chapter 9 timer/counter function 349 user?s manual u15195ej5v0ud figure 9-68. external control timing of timer 2 (when tcre0 register?s udsen1, udsen0 bits = 00b, osten bit = 0, ceen bit = 1, case1 bit = 0) f clk ecren bit note clren bit note eclr cnt ct eceen bit note 1234h 1235h 0000h 0001h 0000h note bits eceen, ecren, clren of tcre0 register remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode eclr: external control signal input from tclr2 pin input 3. n = 0, 1
chapter 9 timer/counter function 350 user?s manual u15195ej5v0ud figure 9-69. operation in timer 2 up/down count mode (when tcre0 register?s eceen bit = 0, ecren bit = 0, clren bit = 0, osten bit = 0, ceen bit = 1, case1 bit = 0) f clk eclr r note 2 cnt inttm2n (output) cnt = 0 ct udsen1, udsen0 bits note 1 ffffh 0000h 0001h don't care 01b 10b 0002h 0001h 0000h 0001h 0002h 0003h 0002h fffeh notes 1. udsen1, udsen0 bits of tcre0 register 2. can control tm20/tm21 clear by subchannel 0/5 compare match or count direction. remarks 1. f clk : base clock 2. cnt: count value of timer 2 ct: tm2n count signal input in 16-bit mode eclr: external control signal input from tclr2 pin input r: compare match signal input (subchannel 0/5) 3. n = 0, 1
chapter 9 timer/counter function 351 user?s manual u15195ej5v0ud figure 9-70. timing in 32-bit cascade operation mode (whe n tcre0 register?s udsen1, udsen0 bits = 00b, eceen bit = 0, ecren bi t = 0, clren bit = 0, osten bit = 0, ceen bit = 1, case1 bit = 1) f clk cnt[tb0] cnt[tb1] ctc casc note [tb1] fffbh fffch fffdh fffeh ffffh 0000h 0001h 0002h 0003h 0004h 1234h 1235h note if, in the 32-bit mode, casc (cnt = max. for tm 20) is input to tm21 and the ctc rising edge is detected, tm21 performs a count operation. remarks 1. f clk : base clock 2. casc: tm21 count signal input in 32-bit mode cnt: count value of timer 2 ctc: tm21 count signal input in 32-bit mode tb0: count value of tm20 tb1: count value of tm21 3. n = 0, 1
chapter 9 timer/counter function 352 user?s manual u15195ej5v0ud (3) operation of capture/compare register (subchannels 1 to 4) subchannels 1 to 4 receive the count value of the timer 2 multiplex count generator. the multiplex count generator is an internal unit of tm 2n that supplies the multiplex count value muxcnt to subchannels 1 to 4. the count value of tm20 is output to subchannels 1 to 4 at the rising edge of muxtb0, and the count value of tm21 is output to subchan nels 1 to 4 at the rising edge of muxtb1. figure 9-71 shows the block diagram of the timer 2 multiplex count generator, and figure 9-72 shows the multiplex count timing. figure 9-71. block diagram of ti mer 2 multiplex count generator muxtb0 (to subchannel m capture/compare register) muxtb1 (to subchannel m capture/compare register) muxcnt (to subchannel m capture/compare register) f clk cnt (from tm20) cnt (from tm21) multiplex control timer 2 multiplex count generator remarks 1. f clk : base clock 2. cnt: count value of timer 2 muxtb0, muxtb1: multiplex signal of tm20, tm21 muxcnt: count value to subchannel m 3. m = 1 to 4
chapter 9 timer/counter function 353 user?s manual u15195ej5v0ud figure 9-72. multiplex count timing f clk muxtb0 muxtb1 muxcnt cnt (0) cnt (1) fffeh ffffh 0000h 1235h 1234h tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 0001h fffeh 1234h ffffh ffffh ffffh 1234h 1234h 0000h 1234h 1235h 0000h 1235h 0000h 0001h 0001h 0001h 1235h 1235h 1235h remarks 1. f clk : base clock 2. cnt: count value of timer 2 muxtb0, muxtb1: multiplex signal of tm20, tm21 muxcnt: count value to subchannel m (m = 1 to 4) tb0: count value of tm20 tb1: count value of tm21 figures 9-73 to 9-78 show the operation of the c apture/compare register (subchannels 1 to 4).
chapter 9 timer/counter function 354 user?s manual u15195ej5v0ud figure 9-73. capture operation: 16-bit buffer- less mode (when operation is delayed through setting of lnkey bit of cmsex0 register, and cmsex0 register?s ccsey bit = 0, bfeey bit = 0, eevey bit = 1, and cs ce0 register?s sevey bit = 0) cvpem0 register f clk muxtb0 muxtb1 ed1 ed2 capture_p capture_s read_enable_p cvsem0 register muxcnt tb0ey bit note 1 tb1ey bit note 1 lnkey bit note 1 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 1 5 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 14 note 2 note 2 undefined undefined 24 13 11 notes 1. bits tb0ey, tb1ey of cmsex register 2. if an event occurs at this timing, it is ignored. remarks 1. f clk : base clock 2. capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register ed1, ed2: capture event signal input from edge selector muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing for cvpem0 register tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4
chapter 9 timer/counter function 355 user?s manual u15195ej5v0ud figure 9-74. capture operati on: mode with 16-bit buffer note 1 (when cmsex0 register?s tbye1 bit = 0, tbye0 bit = 1, ccsey bit = 0, lnke y bit = 0, bfeey bit = 1, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk muxtb0 muxtb1 buffer read_enable_p cvpem0 register cvsem0 register muxcnt ed1 capture_p capture_s tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 1 5 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 new event 14 note 2 note 3 undefined undefined 2 4 capture 23 4 8 shift l event notes 1. to operate tm2n in the mode with 16-bit buffer, per form a capture at least twice at the start of an operation and read the cvpem0 register. also, read the cvpem0 register after performing a capture at least once. 2. a write operation to the cvpen0 register is not performed at these signal inputs because the cvsem0 register operates as a buffer. 3. after this timing, a write operation from the cvsem 0 register to the cvpem0 register is enabled. remarks 1. f clk : base clock 2. buffer: timing of write operation from cvsem0 register to cvpem0 register capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register ed1: capture event signal input from edge selector muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing of cvpem0 register tb0: count value of tm20; tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4
chapter 9 timer/counter function 356 user?s manual u15195ej5v0ud figure 9-75. capture operation: 32-bit cascad e operation mode (when cmsex register?s tbye1 bit = 1, tbye0 bit = 1, ccsey bit = 0, lnkey bit = 0, bfeey bit = arbitrary, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk casc note 1 muxtb0 muxtb1 muxcnt ed1 capture_s capture_p read_enable_p cvsem0 register cvpem0 register tcounte0 = tcounte1 cnt (0) cnt (1) fffeh ffffh 0000h 1235h 1234h tb0 tb1 tb0 tb1 tb0 undefined undefined 0000h 1235h 0001h 1235h tb1 tb0 tb1 tb0 tb1 tb0 tb1 note 2 note 3 tb0 tb1 enable the next capture tb0 tb1 tb0 tb1 tb0 tb1 0001h fffeh 1234h ffffh ffffh ffffh 1234h 1234h 0000h 1234h 1235h 0000h 1235h 0000h 0001h 0001h 0001h 1235h 1235h 1235h note 2 note 3 notes 1. tm21 performs a count operation when, in the 32-bit m ode, casc (cnt = max. for tm20) is input to tm21 and the rising edge of ctc is detected. 2. if an event occurs during this timing, it is ignored. 3. cpu read access is not performed at this timing (wait status). remarks 1. f clk : base clock 2. capture_p: capture trigger signal of main capture register capture_s: capture trigger si gnal of sub capture register casc: tm21 count signal in 32-bit mode cnt: count value of timer 2 ed1: capture event sig nal input from edge selector muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 read_enable_p: read timing of cvpem0 register tb0: count value of tm20 tb1: count value of tm21 tcounte0, tcounte1: count enable signal input of timer 2 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4
chapter 9 timer/counter function 357 user?s manual u15195ej5v0ud figure 9-76. capture operation: capture contro l by software and trigger timing (when cmsex0 register?s tbye1 bit = 0, tbye0 bit = 1, cc sey bit = 0, lnkey bit = 0, bfeey bit = 1) f clk eevey bit note 1 sevey bit note 2 muxtb0 muxtb1 muxcnt ed1 capture_p capture_s buffer cvsem0 register cvpem0 register undefined undefined 4 4 9 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 4 78 5 9 10 6 11 7 8 9 10 12 13 14 cleared by timer set by software event detection by eevey bit prohibited l notes 1. eevey bit of cmsex0 register 2. sevey bit of csce0 register remarks 1. f clk : base clock 2. buffer: timing of write operation from cvsem0 register to cvpem0 register capture_p: capture trigger si gnal of main capture register capture_s: capture trigger si gnal of sub capture register ed1: capture event sig nal input from edge selector muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4
chapter 9 timer/counter function 358 user?s manual u15195ej5v0ud figure 9-77. compare operation: buffer-less mode (when cmsex0 register?s ccsey bit = 1, lnkey bit = arbitrary, bfeey bit = 0) f clk tb0ey bit note 1 tb1ey bit note 1 muxtb0 muxtb1 muxcnt write_enable_s reload_primary cvsem0 register cvpem0 register reload1 intccm tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb0 tb1 tb0 tb1 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 7 78 9 10 9 11 8 9 10 67 8 2 2 9 9 8 8 note 3 note 3 note 3 note 3 note 2 notes 1. tb1ey, tb0ey bits of cmsex0 register 2. no interrupt is generated due to a compare ma tch with counter differing from that set by the tb1ey and tb0ey bits. 3. intcc2m is generated to match the cycle from the rising edge to the falling edge of muxtb0. remarks 1. f clk : base clock 2. muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 reload1: compare match signal reload_primary: timing of write operation fr om cvsem0 register to cvpem0 register write_enable_s: timing of c vsem0 register write operation tb0: count value of tm20 tb1: count value of tm21 3. m = 1 to 4, x = 12, 34
chapter 9 timer/counter function 359 user?s manual u15195ej5v0ud figure 9-78. compare operation: mode with bu ffer (when operation is delayed through setting of lnkey bit of cmsex0 register, cmsex0 regi ster?s ccsey bit = 1, bfeey bit = 1) f clk lnkey bit note write_enable_s muxtb0 muxtb1 muxcnt reload2a reload1 reload_primary cvsem0 register cvpem0 register intcc2m (output) tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 tb0 tb1 51 62 3 4 78 5 9106117012 12 13 14 4 471 71 note lnkey bit of cmsex0 register remarks 1. f clk : base clock 2. muxcnt: count value to subchannel m muxtb0, muxtb1: multiplex signal of tm20, tm21 reload1: compare match signal reload2a: zero count signal input of tm20 (occurs when tm20 = 0000h) reload_primary: timing of write operation from cvsem0 register to cvpem0 register write_enable_s: timing of cvsem0 register write operation tb0: count value of tm20 (in this figure, the maximum count value is 7) tb1: count value of tm21 3. m = 1 to 4, x = 12, 34 y: when x = 12, y = 1, 2, and when x = 34, y = 3, 4
chapter 9 timer/counter function 360 user?s manual u15195ej5v0ud (4) operation of capture/compare register (subchannels 0, 5) figures 9-79 and 9-80 show the operation of the capture/compare register (subchannels 0, 5). figure 9-79. capture operation: timer 2 count value read timing (when cmse050 register?s ccsey bit = 0, eevey bit = 1, and csce0 register?s sevey bit = 0) f clk ed1 ed2 capture_s read_enable_s cvsey0 register cnt lnkey note 1 123456 78910 0 note 2 note 2 undefined 2 6 9 notes 1. lnkey bit of cmse050 register 2. if an event occurs at this timing, it is ignored. remarks 1. f clk : base clock 2. cnt: count value of timer 2 capture_s: capture trigger si gnal of sub capture register ed1, ed2: capture event signal inputs from edge selector read_enable_s: read timing for cvsey0 register 3. y = 0, 5
chapter 9 timer/counter function 361 user?s manual u15195ej5v0ud figure 9-80. compare operation: timing of co mpare match and write operation to register (when cmse050 register?s ccsey bit = 1, eevey bit = arbitrary, and csce0 register?s sevey bit = arbitrary) f clk cvsey0 register match r note 1 intcc20, intcc25 (output) cnt cpu write c/c 12 2 34 4 56 78 8 910 0 note 2 note 3 note 2 note 2 note 3 note 3 notes 1. can control tm20/tm21 clear by subchannel 0/5 compare match and count direction 2. when the match signal occurs, the same wa veform as the match signal is generated. 3. the pulse width is always 1 clock. remarks 1. f clk : base clock 2. cnt: count value of timer 2 match: cvsey0 regist er compare match timing r: compare match input (subchannel 0/5)
chapter 9 timer/counter function 362 user?s manual u15195ej5v0ud (5) operation of output circuit figures 9-81 to 9-84 show the output circuit operation. figure 9-81. signal output operation: toggl e mode 0 and toggle mode 1 (when octle0 register?s swfen bit = 0, and odele0 regi ster?s odlen2 to odlen0 bits = 0) f clk ra rb rn to2n timer output (alven bit = 0 note 2 ) to2n timer output (alven bit = 1 note 2 ) otmen1, otmen0 bits note 1 s/t 00b 01b notes 1. otmen1, otmen0 bits of octle0 register 2. alven bit of octle0 register remarks 1. f clk : base clock 2. ra: zero count signal input of tm20 (output circuit reset signal) rb: zero count signal input of tm21 (output circuit reset signal) rn: interrupt signal input of subchannel n (output circuit reset signal) s/t: interrupt signal input of subc hannel n (output circuit set signal) 3. n = 1 to 4
chapter 9 timer/counter function 363 user?s manual u15195ej5v0ud figure 9-82. signal output operation: toggl e mode 2 and toggle mode 3 (when octle0 register?s swfen bit = 0, and odele0 re gister?s odlen2 to odlen0 bits = 0) f clk ra rb rn to2n timer output (alven bit = 0 note 2 ) to2n timer output (alven bit = 1 note 2 ) otmen1, otmen0 bits note 1 s/t 10b 11b notes 1. otmen1, otmen0 bits of octle0 register 2. alven bit of octle0 register remarks 1. f clk : base clock 2. ra: zero count signal input of tm20 (output circuit reset signal) rb: zero count signal input of tm21 (output circuit reset signal) rn: interrupt signal input of subchannel n (output circuit reset signal) s/t: interrupt signal input of subc hannel n (output circuit set signal) 3. n = 1 to 4 figure 9-83. signal output operation: duri ng software control (when octle0 register?s otmen1, otmen0 bits = arbitrary, swfen bit = 1, and odele0 register?s odlen2 to odlen0 bits = 0) f clk alven bit note to2n timer output note alven bit of octle0 register remarks 1. f clk : base clock 2. n = 1 to 4
chapter 9 timer/counter function 364 user?s manual u15195ej5v0ud figure 9-84. signal output operation: during delay output operation (when octle0 register?s otmen1, otmen0 bits = 0, alven = 0, swfen bit = 0) f clk to2n timer output odelen2 to odelen0 bits note s/t 5 2 note odelen2 to odelen0 bits of octle0 register remarks 1. f clk : base clock 2. n = 1 to 4
chapter 9 timer/counter function 365 user?s manual u15195ej5v0ud 9.3.6 pwm output operation in timer 2 compare mode (1) operation during pwm output operation of to2n pin in toggle mode 1 in toggle mode 1, the output of to2n (i nternal) is made inactive at the tr igger signal when tm20 = 0, and the output of to2n (internal) is made active triggered by a compare match signal with subchannel 1 (the cvsen0 register). the to2n pin outputs a high level or low leve l according to the to2n (internal) status and the value of the octle0.alven bit. figure 9-85. during normal output operation (when otmen1, otme n0 bits = 01 in octle0 register, odlen2 to odlen0 bits = 000 in odele0 register) f clk match signal with cvsen0 register to2n ( internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 register tm20 = 0 06 05 07 00 02 inactive status inactive status active status active status 04 01 03 06 0008h 0005h 05 07 00 01 02 04 06 00 01 03 05 07 remark n = 1 to 4
chapter 9 timer/counter function 366 user?s manual u15195ej5v0ud (2) operations when output of the to2n pin is controlled by manipulating the octle0.swfen bit in toggle mode 1 (a) when compare match signal of subchannel n is output immediat ely after the swfen bit changes from 1 to 0 figures 9-86 and 9-87 show the waveform of each blo ck at output start/end when the output of the to2n output pin is controlled by manipulating the swfen bit in toggle mode 1. timer 2 of the v850e/ia2 outputs levels according to the value of the alven bit (low level when the alven bit is 0, high level when the alven bit is 1) by fixing the to2n output to the inactive status. when the swfen bit is 0, timer 2 outputs an active le vel or inactive level by making to2n (internal) operate according to the trigger signal. however, if the swfen bit is changed from 1 to 0, forcibly activate the to2n output once. if the swfen bit is changed from 0 to 1, forcibly fi x the to2n output to t he inactive status. if the compare match signal of subchannel n is output immediately after the swfen bit has been changed from 1 to 0, the period from when the swfe n bit changes from 1 to 0 until the compare match signal is output is added to the active period of th e normal to2n output, lengthening the first active period (refer to figure 9-86 ). figure 9-86. when normal out put operation starts/ends (when otmen1, otme n0 bits = 01 in octle0 register, odlen2 to odlen0 bits = 000 in odeld0 register) f clk match signal with cvsen0 register to2n ( internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 register tm20 = 0 06 05 07 00 02 inactive status (fix) inactive status active status inactive status inactive status (fix) 04 01 03 06 0008h 0005h 05 07 00 01 02 04 06 03 05 07 swfen bit 00 01 02 04 03 05 active status remark n = 1 to 4
chapter 9 timer/counter function 367 user?s manual u15195ej5v0ud (b) when the trigger signal of tm20 = 0 is output immediately after the swfen bit is changed from 1 to 0 when the trigger signal of tm20 = 0 is output immedi ately after the swfen bit is changed from 1 to 0, the initial active period is from when the swfen bit is changed from 1 to 0 until the trigger signal of tm20 is output. therefore, a shorter pulse than the ac tive period of the normal to2n output is output. when the swfen bit is changed from 0 to 1, the to2n out put is forcibly fixed to inactive. if this operation is generated while active level is output, the active level output period is shorter (refer to figure 9-87 ). figure 9-87. when normal out put operation starts/ends (when otmen1, otme n0 bits = 01 in octle0 register, odlen2 to odlen0 bits = 000 in odeld0 register) f clk match signal with cvse0 register to2n ( internal) to2n output (alven bit = 0) to2n output (alven bit = 1) tm20 cvse00 register cvsen0 r egister tm20 = 0 02 inactive status (fixed) inactive status active status active status inactive status inactive status (fixed) 04 03 06 0008h 0005h 05 07 00 01 02 04 06 03 05 07 swfen bit 00 01 02 04 03 05 06 07 00 active status remark n = 1 to 4
chapter 9 timer/counter function 368 user?s manual u15195ej5v0ud 9.4 timer 3 9.4.1 features (timer 3) timer 3 (tm3) is a 16-bit timer/counter t hat can perform the following operations. ? interval timer function ? pwm output ? external signal cycle measurement ? to3 output buffer set to off by intp4 input 9.4.2 function overview (timer 3) ? 16-bit timer/counter (tm3): 1 channel ? capture/compare registers: 2 ? count clock division selectable by prescaler (set the frequency of the count clock to 16 mhz or less) ? base clock (f clk ): 2 types (set f clk to 32 mhz or less) f xx and f xx /2 can be selected ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). base clock (f clk ) division ratio f xx selected f xx /2 selected 1/2 f xx /2 f xx /4 1/4 f xx /4 f xx /8 1/8 f xx /8 f xx /16 1/16 f xx /16 f xx /32 1/32 f xx /32 f xx /64 1/64 f xx /64 f xx /128 1/128 f xx /128 f xx /256 1/256 f xx /256 f xx /512 ? interrupt request sources ? capture/compare match interrupt requests: 2 sources in case of capture register: intcc3n generated by intp3n input in case of compare register: intcc3n generated by cc3n match signal ? overflow interrupt request: 1 source inttm3 generated upon overflow of tm3 register ? timer/counter count clock sources: 2 types (selection of external pulse in put, internal system clock cycle) ? one of two operation modes when th e timer/counter overflows can be sele cted: free-running mode or overflow stop mode ? the timer/counter can be cleared by matc h of timer/counter and compare register ? external pulse output (to3): 1 ? to3 output buffer set to off by intp4 input (high-impedance state) remarks 1. f xx : internal system clock 2. n = 0, 1
chapter 9 timer/counter function 369 user?s manual u15195ej5v0ud 9.4.3 function added to v850e/ia2 timer 3 (tm3) of the v850e/ia2 has an added function to control to3 output by usi ng the intp4 pin. this additional function can be used to forcibly stop to3 output, if any abnormality is detected, by inputting a signal to the intp4 pin. this to3 output stop function can also be used even when the clock supply is stopped. 9.4.4 basic configuration table 9-13. timer 3 configuration list count clock timer note 1 note 2 register read/write generated interrupt signal capture trigger timer output s/r tm3 read inttm3 ? ? cc30 read/write intcc30 intp30 to3 (s) timer 3 f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cc31 read/write intc31 intp31 to3 (r) notes 1. when f xx is selected as the base clock (f clk ) of tm3 2. when f xx /2 is selected as the base clock (f clk ) of tm3 remark f xx : internal system clock s/r: set/reset figure 9-88 shows the block diagram of timer 3. figure 9-88. block di agram of timer 3 r note q sq tm3 (16-bit) edge detection noise elimination timer 3 output control register (to3c) cc30 cc31 intp31 intp4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f xx /2 ti3/tclr3/intp30 inttm3 intcc30 intcc31 to3 clear & start clear & start f clk selector selector selector f xx note reset priority remarks 1. ti3 input and tclr3 input connected to port immediately before edge detection 2. f clk : base clock (32 mhz (max.)) f xx : internal system clock
chapter 9 timer/counter function 370 user?s manual u15195ej5v0ud (1) timer 3 (tm3) tm3 functions as a 16-bit free-running timer or as an event counter for an external signal. besides being mainly used for cycle measurement, tm3 can be used as pulse output. tm3 is read-only, in 16-bit units. cautions 1. the tm3 register can only be read. if writing is performed to the tm3 register, the subsequent operation is undefined. 2. if the tm3cae bit of the tmc30 regist er is cleared (0), a reset is performed asynchronously. 3. continuous reading of tm3 is prohibited. if tm3 is continuously read, the second read value may differ from the actual value. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm3 fffff680h 0000h address after reset 0 tm3 performs the count-up operations of an internal count clock or external count clock. timer starting and stopping are controlled by the tm3ce bit of timer control register 30 (tmc30). the internal or external count clock is selected by the eti bit of timer control register 31 (tmc31). (a) selection of the external count clock tm3 operates as an event counter. when the eti bit of timer control register 31 (tmc31) is set (1), tm3 counts the valid edges of the external clock input (ti3), synchronized with the internal count clock. the valid edge is specified by valid edge selection r egister (sesc). caution when using the intp30, ti3, and tc lr3 pins as ti3 andtclr3, either mask the interrupt signal to intp30 or set cc3 n in compare mode (n = 0 or 1). (b) selection of the internal count clock tm3 operates as a free-running timer. when an internal clock is specified as a count clock by timer control register 31 (tmc31), tm3 is counted up for each input clock cycle specified by the cs2 to cs0 bits of the tmc30 register. division by the prescaler can be selected for the count clock from among f clk /2, f clk /4, f clk /8, f clk /16, f clk /32, f clk /64, f clk /128 and f clk /256 by the tmc30 register (f clk : base clock). an overflow interrupt can be generated if the timer overflows. also, the timer can be stopped following an overflow by setting the ost bit of the tmc31 register to 1. caution the count clock cannot be ch anged while the timer is operating. the conditions when the tm3 regist er becomes 0000h are shown below. (i) asynchronous reset ? tm3cae bit of tmc30 register = 0 ? reset input (ii) synchronous reset ? tm3ce bit of tmc30 register = 0 ? the cc30 register is used as a compare regi ster, and the tm3 and cc30 registers match when clearing the tm3 register is enabled ( cclr bit of the tmc31 register = 1)
chapter 9 timer/counter function 371 user?s manual u15195ej5v0ud (2) capture/compare registers 30 and 31 (cc30 and cc31) these capture/compare registers 30 and 31 are 16-bit registers. they can be used as capture registers or compar e registers according to the cms1 and cms0 bit specifications of timer control register 31 (tmc31). these registers can be read/written in 16-bit units ( however, write operations can only be performed in compare mode). caution continuous reading of cc3 n is prohibited. if cc3n is c ontinuously read, the second read value may differ from the actual value. if cc3n must be read twice, be sure to read another register between the first and the second read operation. correct usage example in correct usage example cc30 read cc30 read cc31 read cc30 read cc30 read cc31 read cc31 read cc31 read cc31 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cc30 fffff682h fffff684h 0000h 0000h address after reset 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 address after reset 0 (a) setting these registers to capture regi sters (cms1 and cms0 of tmc31 = 0) when these registers are set to capt ure registers, the valid edges of t he corresponding external interrupt signals intp30 and intp31 are detected as capture triggers. the timer tm3 is synchronized with the capture trigger, and the value of tm3 is latched in the cc30 and cc 31 registers (capture operation). the valid edge of the intp30 pin is specified (rising, falling, or both edges) according to the ies301 and ies300 bits of the sesc register, and the valid edge of the intp31 pin is specified according to the ies311 and ies310 bits of the sesc register. the capture operation is per formed asynchronously to the count clo ck. the latched value is held in the capture register until the next c apture operation is performed. when the tm3cae bit of timer control regi ster 30 (tmc30) is 0, 0000h is read. if these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of the intp30 and intp31 signals. caution if the capture operation and the tm3 re gister count prohibit setting (tm3ce bit of tmc30 register = 0) timings conflict, th e captured data becomes undefined, and no intcc3n interrupt is gene rated (n = 0, 1).
chapter 9 timer/counter function 372 user?s manual u15195ej5v0ud (b) setting these registers to compare regi sters (cms1 and cms0 of tmc31 = 1) when these registers are set to compare registers, the tm3 and register values are compared for each count clock, and an interrupt is generated by a match. if the cclr bit of timer control register 31 (tmc31) is set (1), the tm3 value is cleared (0) at t he same time as a match with the cc30 register (it is not cleared (0) by a match with the cc31 register). a compare register is equipped with a set/reset outpu t function. the corresponding timer output (to3) is set or reset, synchronized with the generation of a match signal. the interrupt selection source differs accord ing to the function of the selected register. cautions 1. to write to capture/compare re gisters 30 and 31 (cc30, cc31), always set the tm3cae bit to 1 first. when the tm3cae bi t is 0, even if writing to registers cc30 and cc31, the data that is written will be invalid b ecause the reset is asynchronous. 2. perform a write operation to capture/com pare registers 30 and 31 after setting them to compare registers according to the tmc30 or tmc31 register setting. if they are set to capture registers (cms1 and cms0 bi ts of tmc31 register = 0), no data is written even if a write operation is performed to cc30 and cc31. 3. when these registers ar e set to compare registers, intp30 and intp31 cannot be used as external interrupt input pins.
chapter 9 timer/counter function 373 user?s manual u15195ej5v0ud 9.4.5 control registers (1) timer 3 clock selection register (prm03) the prm03 register is used to select the base clock (f clk ) of timer 3 (tm3). this register can be read/written in 8-bit or 1-bit units. cautions 1. always set this regist er before using the timer. 2. set f clk to 32 mhz or less. 7 0 prm03 6 0 5 0 4 0 3 0 2 0 1 0 0 prm3 address fffff690h after reset 00h bit position bit name function 0 prm3 specifies the base clock (f clk ) of timer 3 (tm3). 0: f xx /2 (when f xx > 32 mhz) 1: f xx (when f xx 32 mhz) remark f xx : internal system clock
chapter 9 timer/counter function 374 user?s manual u15195ej5v0ud (2) timer control register 30 (tmc30) the tmc30 register controls the operation of tm3. this register can be read/written in 8-bit or 1-bit units. cautions 1. the tm3cae bit and other bits cannot be set at the same time. be sure to set the tm3cae bit and then set the other bits and th e other registers of tm3. when using an external pin related to the timer function when using timer 3, be sure to set (1) the cae bit after setting the external pi n to the control mode. 2. if occurrence of an overfl ow contends with writing to th e tmc30 register, the value of the tm3ovf bit is the value wr itten to the tmc30 register. (1/2) <7> tm3ovf tmc30 6 cs2 5 cs1 4 cs0 3 0 2 0 <1> tm3ce <0> tm3cae address fffff686h after reset 00h bit position bit name function 7 tm3ovf flag that indicates tm3 overflow. 0: no overflow 1: overflow the tm3ovf bit becomes 1 when tm3 change s from ffffh to 0000h. an overflow interrupt request (inttm3) is generated at the same time. however, if cc30 is set to the compare mode (cms0 bit of the tmc31 register = 1) and match clear during comparison of tm3 and cc30 is enabled (cclr bit of tmc31 register = 1), and tm3 is cleared to 0000h following match at ffffh, tm3 is considered to have been cleared and the tm3ovf bit does not become 1, nor is the inttm3 interrupt generated. the tm3ovf bit holds a ?1? until 0 is written to it or an asynchronous reset is applied while the tm3cae bit = 0. interrupts by overflow and the tm3ovf bit are independent, and even if the tm3ovf bit is manipulated, this does not affect the interrupt request flag for inttm3 (tm3if0). if an overflow occurs while the tm3ovf bit is being read, the value of the flag changes and the value is returned at the next read.
chapter 9 timer/counter function 375 user?s manual u15195ej5v0ud (2/2) bit position bit name function selects the internal count clock for tm3. cs2 cs1 cs0 count clock 0 0 0 f clk /2 0 0 1 f clk /4 0 1 0 f clk /8 0 1 1 f clk /16 1 0 0 f clk /32 1 0 1 f clk /64 1 1 0 f clk /128 1 1 1 f clk /256 6 to 4 cs2 to cs0 caution do not change the cs2 to cs0 bits during timer operation. if they are to be changed, they must be changed after setting the tm3ce bit to 0. if the cs2 to cs0 bits are overwritten during timer operation, the operation is not guaranteed. remark f clk : base clock 1 tm3ce controls the operation of tm3. 0: count disabled (timer stopped at 0000h and does not operate) 1: count operation performed. caution if tm3ce = 0, the external pulse output (to3) becomes inactive level (the active level of to3 output is set with the alv bit of the tmc31 register). 0 tm3cae controls the internal count clock. 0: entire tm3 unit asynchronously reset. stop base clock supply to tm3 unit. 1: base clock (f clk ) supplied to tm3 unit. cautions 1. when tm3cae = 0 is set, the tm3 unit can be reset asynchronously. 2. when tm3cae = 0, the tm3 unit is in a reset state. to operate tm3, first set tm3cae = 1. 3. when the tm3cae bit is changed from 1 to 0, all the registers of the tm3 unit are initialized. when again setting tm3cae = 1, be sure to then again set all the registers of the tm3 unit.
chapter 9 timer/counter function 376 user?s manual u15195ej5v0ud (3) timer control register 31 (tmc31) the tmc31 register controls the operation of tm3. this register can be read/written in 8-bit or 1-bit units. cautions 1. do not change the bits of the tmc31 register during timer operation. if they are to be changed, they must be changed after setting th e tm3ce bit of the tmc30 register to 0. if the tmc31 register is overwritten dur ing timer operation, the operation is not guaranteed. 2. if the ent1 bit and the alv bit are ch anged simultaneously, a glitch (spike-shaped noise) may be generated in the to3 pin outpu t. either design a circuit that will not malfunction even if a glitch is generated, or make sure that the ent1 bit and the alv bit do not change at the same time. 3. to3 output remains uncha nged by external interrupt signa ls (intp30, intp31). when using the to3 signal, set the capture/compare register to the compare register (cms1, cms0 bits of tmc31 register = 1). remark a reset takes precedence for the flip-flop of the to3 output.
chapter 9 timer/counter function 377 user?s manual u15195ej5v0ud 7 ost tmc31 6 ent1 5 alv 4 eti 3 cclr 2 eclr 1 cms1 0 cms0 address fffff688h after reset 20h bit position bit name function 7 ost sets the operation when tm3 overflows. 0: count operation continues after overflow (free-running mode) 1: after overflow, timer holds 0000h and stops count operation (overflow stop mode). at this time, the tm3ce bit of tmc30 remains 1. the count operation is resumed by again writing 1 to the tm3ce bit. 6 ent1 enables/disables output of external pulse output (to3). 0: disable external pulse output. output of inactive level of alv bit to to3 pin is fixed. to3 pin level remains unchanged even if match signal from corresponding compare register is generated. 1: enable external pulse output. compar e register match causes to3 output to change. however, in capture mode, to3 output does not change. an alv bit inactive level is output from when time r output is enabled until a match signal is generated. caution if either cc30 or cc31 is specified as a capture register, the ent1 bit must be set to 0. 5 alv specifies active level of external pulse output (to3). 0: active level is low level. 1: active level is high level. caution the initial value of the alv bit is ?1?. 4 eti switches count clock between ex ternal clock and internal clock. 0: specifies input clock (internal). the count clock can be selected with bits cs2 to cs0 of tmc30. 1: specifies external clock (ti3). va lid edge can be selected with bits tes31, tes30 of sesc. 3 cclr enables/disables tm3 clea ring during compare operation. 0: clearing disabled. 1: clearing enabled (tm3 is cleared when cc30 and tm3 match during compare operation). 2 eclr enables tm3 clearing by external clear input (tclr3). 0: clearing by tclr3 disabled. 1: clearing by tclr3 enabled (cou nting resumes after clearing). 1 cms1 selects operation mode of capture/compare register (cc31). 0: register operates as capture register. 1: register operates as compare register. 0 cms0 selects operation mode of capture/compare register (cc30). 0: register operates as capture register. 1: register operates as compare register.
chapter 9 timer/counter function 378 user?s manual u15195ej5v0ud (4) valid edge select ion register (sesc) this register specifies the valid edge of external in terrupt requests (ti3, tclr3, intp30, intp31) from an external pin. the rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. this register can be read/written in 8-bit or 1-bit units. caution do not change the bits of the sesc regi ster during timer operation. if they are to be changed, they must be changed after setting th e tm3ce bit of the tmc30 register to 0. if the sesc register is overwritte n during timer operation, the oper ation is not guaranteed. 7 tes31 sesc 6 tes30 5 ces31 4 ces30 3 ies311 2 ies310 1 ies301 0 ies300 address fffff689h after reset 00h ti3 tclr3 intp31 intp30 bit position bit name function 7, 6 tes31, tes30 specifies the valid edge of intp30, intp31 pins, tclr3, and ti3 pins. xesn1 xesn0 operation 5, 4 ces31, ces30 0 0 falling edge 0 1 rising edge 3, 2 ies311, ies310 1 0 setting prohibited 1 1 both rising and falling edges 1, 0 ies301, ies300 remark n = 3, 30, 31
chapter 9 timer/counter function 379 user?s manual u15195ej5v0ud (5) timer 3 output control register (to3c) to3c is a register that cont rols output of the to3 pin. this register can be read/written in 8-bit or 1-bit units. caution the to3 output stop status can be canceled by writing 0 to the to3sp bit of this register. 7 0 to3c 6 0 5 0 4 0 3 0 2 0 1 0 <0> to3sp address fffff6a0h after reset 00h bit position bit name function 0 to3sp validates or invalidates output stop control of the to3 pin by intp4 pin input. 0: invalidates intp4 pin input (to3 output (the output buffer of the to3 pin is on)). 1: validates intp4 pin input (to3 output is stopped by the valid edge of the intp4 pin (the output buffer of the to3 pin is off and the to3 pin goes into a high-impedance state)). the following table indicates the relationship between the setting of each register and the status of the to3, p27, and intp31 pins. table 9-14. relationship between setting of each regi ster and status of to3, p27, and intp31 pins to3/p27/intp31 pmc27 bit pfc27 bit pm27 bit to3sp bit operation mode of pin output buffer status pin function 0 0 output port mode on output port 0 1 input port mode off input port 1 0 intp31 input mode off intp31 1 1 0 on to3 1 1 1 to3 output mode on/off note to3/hi-z note note if the to3sp bit is set to 1 in to3 output mode (pmc27 bit = 1 and pfc27 bit = 1), the output buffer of the to3 pin is turned off and the to3 pin goes into a high-i mpedance state if the spec ified valid interrupt edge is generated on the intp4 pin. to avoid turning off the output drive by valid edge input to the intp4 pin, be sure to clear the to3sp bit to 0. the valid edge of the intp4 pin is specified by bit 0 (es40) and bit 1 (es41) of the intm2 register. specifying the valid edge of the intp4 pin (changing t he es40 and es41 bits) is prohibited while timer 3 is operating. remark : don?t care (does not have to be set)
chapter 9 timer/counter function 380 user?s manual u15195ej5v0ud 9.4.6 operation (1) count operation timer 3 can function as a 16-bit free-running timer or as an external signal event counter. the setting for the type of operation is specified by timer c ontrol register 3n (tmc3n) (n = 0, 1). when it operates as a free-running timer, if the cc30 or cc31 register and the tm3 count value match, an interrupt signal is generated and the timer output signal (to3) can be set or reset. also, a capture operation that holds the tm3 count value in the cc30 or cc31 r egister is performed, synchronized with the valid edge that was detected from the external interrupt request inpu t pin as an external trigger. the capture value is held until the next captur e trigger is generated. caution when using the intp30, ti3, and tclr3 pi ns as ti3 and tclr3, either mask the interrupt signal to intp30 or set the cc3n regist er to compare mode (n = 0 or 1). figure 9-89. basic operation of timer 3 0001h 0000h 0002h 0003h fbfeh fbffh 0001h 0002h 0000h tm3 count clock ? count disabled tm3ce 0 ? count start tm3ce 1 ? count start tm3ce 1
chapter 9 timer/counter function 381 user?s manual u15195ej5v0ud (2) overflow when the tm3 register has counted the count clock from ffffh to 0000h, the tm3ovf bit of the tmc30 register is set (1), and an overflow interrupt (inttm3) is generated at the same ti me. however, if the cc30 register is set to compare mode (cms0 bit = 1) an d to the value ffffh when match clearing is enabled (cclr bit = 1), then the tm3 register is considered to be cleared and the tm3ovf bit is not set (1) when the tm3 register changes from ffffh to 0000h. also, t he overflow interrupt (inttm3) is not generated . when the tm3 register is changed fr om ffffh to 0000h because the tm3c e bit changes from 1 to 0, the tm3 register is considered to be cleared, but the tm3ovf bit is not set (1) and no inttm3 interrupt is generated. also, timer operation can be stopped after an overflow by setting the ost bit of the tmc31 register to 1. when the timer is stopped due to an overflow, the count o peration is not restarted un til the tm3ce bit of the tmc30 register is set (1). operation is not affected even if the tm3c e bit is set (1) during a count operation. figure 9-90. operation after overflow (when ost = 1) overflow count start overflow ffffh ffffh tm3 0 inttm3 ost 1 tm3ce 1 tm3ce 1
chapter 9 timer/counter function 382 user?s manual u15195ej5v0ud (3) capture operation the tm3 register has two capture/comp are registers. these are the cc30 register and the cc31 register. a capture operation or a compare oper ation is performed according to the settings of both the cms1 and cms0 bits of the tmc31 register. if the cms1 and cms0 bits of the tmc31 register ar e set to 0, the register operates as a capture register. a capture operation that c aptures and holds the tm3 count value asyn chronously relative to the count clock is performed synchronized with an external trigger. the valid edge that is detected from an external interrupt request input pin (intp30 or intp31) is used as an ex ternal trigger (capture trigger). the tm3 count value during counting is captured and held in the capture regi ster, synchronized with that capture trigger signal. the capture register value is held until the next capt ure trigger is generated. also, an interrupt request (intcc30 or intcc31) is generated by intp30 or intp31 signal input. the valid edge of the capture trigger is se t by valid edge selection register (sesc). if both the rising and falling edges are set as capture tr iggers, the input pulse width from an external source can be measured. also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. figure 9-91. capture operation example tm3 0 tm3ce intp31 cc31 (capture register) n n (capture trigger) (capture trigger) remarks 1. when the tm3ce bit is 0, no capture operat ion is performed even if intp31 is input. 2. valid edge of intp31: rising edge
chapter 9 timer/counter function 383 user?s manual u15195ej5v0ud figure 9-92. tm3 capture operation e xample (when both edges are specified) tm3 ? count start tm3ce 1 ? overflow tm3ovf 1 d0 d1 d2 d0 d1 d2 interrupt request (intp31) (tm3 count values) capture register (cc31) remark d0 to d2: tm3 count values
chapter 9 timer/counter function 384 user?s manual u15195ej5v0ud (4) compare operation the tm3 register has two capture/comp are registers. these are the cc30 register and the cc31 register. a capture operation or a compare oper ation is performed according to the settings of both the cms1 and cms0 bits of the tmc31 register. if 1 is set in the cms1 and cms0 bits of the tmc31 register, the register operates as a compare register. a compare operation that compares t he value that was set in the compar e register and the tm3 count value is performed. if the tm3 count value matches the value of the compar e register, which had been set in advance, a match signal is sent to the output contro ller. the match signal causes the timer output pin (to3) to change and an interrupt request signal (intcc30, intcc3 1) to be generated at the same time. if the cc30 or cc31 register is set to 0000h, ?0000h? after the tm3 register counts up from ffffh to 0000h is judged as a match. in this case, the value of the tm3 register is cleared to 0 at the next count timing, but 0000h is not judged as a match at that time. 0000h wh en the tm3 register begins counting is not judged as a match either. if match clearing is enabled (cclr bit = 1) for the cc30 register, the tm3 register is cleared when a match with the tm3 register occurs during a compare operation. figure 9-93. compare op eration example (1/2) (a) if cclr bit = 1 and cc30 register is value other than 0000h 0001h tm3 count up 0000h n n n ? 1 compare register (cc30) match detection (intcc30) to3 (output) remarks 1. the match is detected immediately after the count up, and the match detection signal is generated. 2. n 0000h
chapter 9 timer/counter function 385 user?s manual u15195ej5v0ud figure 9-93. compare op eration example (2/2) (b) if cclr bit = 1 and cc30 register is 0000h 0001h tm3 count up 0000h 0000h 0000h ffffh compare register (cc30) inttm3 match detection (intcc30) to3 (output) remark the match is detected immediately after the count up, and the match detection signal is generated.
chapter 9 timer/counter function 386 user?s manual u15195ej5v0ud (5) external pulse output timer 3 has one timer output pin (to3). an external pulse output (to3) is generated when a ma tch of the two compare registers (cc30 and cc31) and the tm3 register is detected. if a match is detected when the tm3 count value and the cc30 value are compared, the output level of the to3 pin is set. also, if a match is detected when t he tm3 count value and the cc31 value are compared, the output level of the to3 pin is reset. the output level of the to 3 pin can be specified by the tmc31 register. table 9-15. to3 output control to3 output ent1 alv external pulse output output level 0 0 disable high level 0 1 disable low level 1 0 enable when the cc30 register is matched: low level when the cc31 register is matched: high level 1 1 enable when the cc30 register is matched: high level when the cc31 register is matched: low level figure 9-94. tm3 compare operation example (set/reset output mode) 0 cc30 cc30 cc31 cc31 cc31 tm3 count value count start tm3ce 1 clear & start clear & start interrupt request (intcc31) interrupt request (intcc30) to3 pin ent1 1 alv 0
chapter 9 timer/counter function 387 user?s manual u15195ej5v0ud (6) to3 output control function by intp4 pin output of the to3 pin can be forcib ly stopped by inputting a signal to the intp4 pin if an abnormality is detected in the power system of a motor. if the to3 output mode is set (pmc27 = 1 and pfc27 = 1) and if the specif ied valid edge is generated on the intp4 pin after the to3sp bit of the timer 3 output cont rol register (to3c) has been set to 1, the output buffer of the to3 pin can be turned off (the to3 pin goes into a high-impedance state). to resume output of the to3 pin (output buffer = on) after output of the to3 pi n has been stopped (output buffer = off) by the valid edge of the intp4 pin, rewrite the to3sp bit from ?1? to ?0?. the valid edge of the intp4 pin can be specified by t he es40 and es41 bits of the external interrupt mode register 2 (intm2). figure 9-95. example of operation of to3 output control function by intp4 pin (in to3 output mode (pmc27 bit = 1 and pfc27 bit = 1)) to3c register intp4 edge detection to3 pin output buffer = on (output data) output buffer = off (high impedance) output buffer = on (output data) (when rising edge is specified) 0000h 0001h 0000h note note note analog delay
chapter 9 timer/counter function 388 user?s manual u15195ej5v0ud 9.4.7 application examples (1) interval timer by setting the tmc30 and tmc31 registers as shown in figure 9-96, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the va lue that was set in advance in the cc30 register as the interval. when the counter value of the tm3 register matches the setting value of the cc30 register, the tm3 register is cleared (0000h) and an interrupt request signal (intcc 30) is generated at the same time that the count operation resumes. figure 9-96. contents of register settings when timer 3 is used as interval timer supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 1 0/1 0/1 1 ost ent alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as compare register clear tm3 register due to match with cc30 register continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary
chapter 9 timer/counter function 389 user?s manual u15195ej5v0ud figure 9-97. interval time r operation timing example 0000h 0001h p 0000h 0001h pp p p p p 0000h 0001h count start clear clear interval time interval time interval time t count clock tm3 register cc30 register intcc30 interrupt remark p: setting value of cc30 register (0000h to ffffh) t: count clock cycle interval time = (p + 1) t
chapter 9 timer/counter function 390 user?s manual u15195ej5v0ud (2) pwm output by setting the tmc30 and tmc31 registers as shown in figure 9-98, timer 3 can output a pwm of the frequency determined by the setting of the cs2 to cs0 bits of the tmc30 register wit h the values that were set in advance in the cc30 and cc31 registers as the intervals. when the counter value of the tm3 register matches th e setting value of the cc30 register, the to3 output becomes active. then, when the counter value of th e tm3 register matches the setting value of the cc31 register, the to3 output becomes inactive. the tm3 r egister continues counting, and when an overflow occurs, clears the count value to 0000h and contin ues counting. this enables a pwm of the frequency determined by the setting of the cs2 to cs0 bits of the tmc30 register to be output. when the setting value of the cc30 register and the setting value of the cc31 register are the same, the to3 output remains inactive and does not change. the active level of to3 output can be set by the alv bit of the tmc31 register. figure 9-98. contents of register settings when timer 3 is used for pwm output supply input clocks to internal units enable count operation 0 1 0/1 0/1 0 0/1 1 1 ost ent1 alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as compare register use cc31 register as compare register disable clearing of tm3 register due to match with cc30 register enable external pulse output (to3) continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary
chapter 9 timer/counter function 391 user?s manual u15195ej5v0ud figure 9-99. pwm output operation timing example 0000h 0001h p ppp p p qqq q q qpq 0000h ffffh 0001h count start clear count clock tm3 register cc30 register cc31 register intcc30 interrupt intcc31 interrupt to3 (output) t remarks 1. p: setting value of cc 30 register (0000h to ffffh) q: setting value of cc 31 register (0000h to ffffh) p q t: count clock cycle pwm cycle = 65536 t q ? p 65536 2. in this example, the active level of to3 output is set to high level. duty =
chapter 9 timer/counter function 392 user?s manual u15195ej5v0ud (3) cycle measurement by setting the tmc30 and tmc31 registers as shown in figure 9-100, timer 3 can measure the cycle of signals input to the intp30 pin or intp31 pin. the valid edge of the intp30 pin is selected according to the ies301 and ies300 bi ts of the sesc register, and the valid edge of the intp31 pin is selected a ccording to the ies311 and ies310 bits of the sesc register. either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. if the cc30 register is set to a capture register and tm3 is started, the valid edge input of the intp30 pin is set as the trigger for capturing the tm3 register value in the cc30 register. when this value is captured, an intcc30 interrupt is generated. similarly, if the cc31 register is set to a capture register and tm3 is started, the vali d edge input of the intp31 pin is set as the trigger for capturing the tm3 r egister value in the cc31 register. when this value is captured, an intcc31 interrupt is generated. the cycle of signals input to the intp30 pin is calculated by obtaining the difference between the tm3 register?s count value (dx) that was captured in the cc30 register accordi ng to the x-th valid edge input of the intp30 pin and the tm3 register?s count value (d(x+1)) th at was captured in the cc30 register according to the (x+1)-th valid edge input of the intp30 pin and mult iplying the value of this difference by the cycle of the clock control signal. the cycle of signals input to the intp31 pin is calculated by obtaining the difference between the tm3 register?s count value (dx) that was captured in the cc31 register accordi ng to the x-th valid edge input of the intp31 pin and the tm3 register?s count value (d(x+1)) th at was captured in the cc31 register according to the (x+1)-th valid edge input of the intp31 pin and mult iplying the value of this difference by the cycle of the clock control signal. figure 9-100. contents of register settings when timer 3 is used for cycle measurement supply input clocks to internal units enable count operation 0 0/1 0/1 0/1 0/1 0/1 0 0 ost ent1 alv eti cclr cms1 cms0 0/1 0/1 0/1 0/1 0 0 1 1 tm3ovf tmc30 tmc31 cs2 cs1 cs0 tm3ce tm3cae use cc30 register as capture register (when measuring the cycle of intp30 input) use cc31 register as capture register (when measuring the cycle of intp31 input) continue counting after tm3 register overflows eclr remark 0/1: set to 0 or 1 as necessary
chapter 9 timer/counter function 393 user?s manual u15195ej5v0ud figure 9-101. cycle measurement operation timing example t 0001h 0000h 0001h 0000h ffffh d0 d1 d2 d3 d3 d2 d1 d0 (d1 ? d0) t (d3 ? d2) t {(10000h ? d1) + d2} t note count clock tm3 register intp30 (input) cc30 register intcc30 interrupt inttm3 interrupt no overflow overflow occurs no overflow count start clear note when an overflow occurs once. remarks 1. d0 to d3: tm3 register count values t: count clock cycle 2. in this example, the valid edge of intp30 input has been set to both edges (rising and falling).
chapter 9 timer/counter function 394 user?s manual u15195ej5v0ud 9.4.8 cautions various cautions concerning timer 3 are shown below. (1) if a conflict occurs between the reading of the cc30 register and a capture operati on when the cc30 register is used in capture mode, an external trigger (intp30) valid edge is detected and an external interrupt request signal (intcc30) is generated, but the timer value is not stored in the cc30 register. (2) if a conflict occurs between the reading of the cc31 register and a capture operati on when the cc31 register is used in capture mode, an external trigger (intp31) valid edge is detected and an external interrupt request signal (intcc31) is generated, but the timer value is not stored in the cc31 register. (3) the following bits and registers must not be rewr itten during operation (tmc30 register tm3ce = 1). ? cs2 to cs0 bits of tmc30 register ? tmc31 register ? sesc register (4) the tm3cae bit of the tmc30 register is a tm3 re set signal. to use tm3, first set (1) the tm3cae bit. (5) the analog noise e limination time + two count clock cycles are requ ired to detect a valid edge of the external interrupt input (intp30 or intp31) and external clo ck input (ti3). therefore, edge detection will not be performed normally for changes that are less than the anal og noise elimination time + two count clock cycles. for the analog noise elimination, refer to 12.5 noise eliminator . (6) the operation of an external interr upt output (intcc30 or in tcc31) is automatically determined according to the operating state of th e capture/compare registers 30, 31 (cc3 0, cc31). when the capture/compare register is used for a capture mode, the external trigger (intp30, intp31) is used for valid edge detection. when the capture/compare register is used for a compar e mode, the external inte rrupt output is used for a match interrupt indicating a match with the tm3 register. (7) if the ent1 and alv bits of the tmc31 register are cha nged at the same time, a glitch (spike shaped noise) may be generated in the to3 pin output. either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ent1 and alv bits do not change at the same time.
chapter 9 timer/counter function 395 user?s manual u15195ej5v0ud 9.5 timer 4 9.5.1 features (timer 4) timer 4 (tm4) functions as a 16-bit interval timer. 9.5.2 function overview (timer 4) ? 16-bit interval timer: 1 channel ? compare register: 1 ? count clock selected from divisions of internal system cl ock (set the frequency of the count clock to 16 mhz or less) ? base clock (f clk ): 1 type (set f clk to 32 mhz or less) f xx /2 ? prescaler division ratio the following division ratios can be selected according to the base clock (f clk ). division ratio base clock (f clk ) 1/2 f xx /4 1/4 f xx /8 1/8 f xx /16 1/16 f xx /32 1/32 f xx /64 1/64 f xx /128 1/128 f xx /256 1/256 f xx /512 ? interrupt request source: 1 ? compare match interrupt intcm4 generated by cm4 match signal ? timer clear the tm4 register can be cleared by a cm4 register match. remark f xx : internal system clock
chapter 9 timer/counter function 396 user?s manual u15195ej5v0ud 9.5.3 basic configuration table 9-16. timer 4 configuration list timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tm4 read ? ? ? ? timer 4 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cm4 read/write intcm4 ? ? ? remark f xx : internal system clock s/r: set/reset figure 9-102 shows the block diagram of timer 4. figure 9-102. block di agram of timer 4 tm4 (16-bit) cm4 intcm4 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f xx /2 clear & start f clk remark f clk : base clock (32 mhz (max.)) f xx : internal system clock
chapter 9 timer/counter function 397 user?s manual u15195ej5v0ud (1) timer 4 (tm4) tm4 is a 16-bit timer. it is mainly used as an interval timer for software. starting and stopping tm4 is controlled by the tm4c e0 bit of timer control register 4 (tmc4). division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the cs2 to cs0 bits of the tmc4 register (f xx : internal system clock). tm4 is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 tm4 fffff540h 0000h address after reset 0 the conditions under which the tm4 regi ster becomes 0000h are shown below. ? reset input ? tm4cae0 bit = 0 ? tm4ce0 bit = 0 ? match of tm4 register and cm4 register ? overflow cautions 1. if the tm4cae0 bit of the tmc4 re gister is cleared (0), a reset is performed asynchronously. 2. if the tm4ce0 bit of the tmc4 register is cleared (0), a reset is performed, synchronized with the internal clock. sim ilarly, a synchronized reset is performed after a match with the cm4 register and after an overflow. 3. the count clock must not be changed during a ti mer operation. if it is to be overwritten, it should be overwritten after the tm4ce0 bit is cleared (0). 4. up to 4 internal system clocks are required after a value is set in the tm4ce0 bit until the set value is transferred to internal unit s. when a count operation begins, the count cycle from 0000h to 0001h differs from subsequent count cycles. 5. after a compare match is generated, the timer is cleared at the next count clock. therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated.
chapter 9 timer/counter function 398 user?s manual u15195ej5v0ud (2) compare register 4 (cm4) cm4 and the tm4 register count value are compared, an d an interrupt request signal (intcm4) is generated when a match occurs. tm4 is clea red, synchronized with this match. if the tm4cae0 bit of the tmc4 register is set to 0, a reset is performed asynchronously, and the registers are initialized. the cm4 register has a master/slave configuration. when a write operation to a cm4 register is performed, data is first written to the master regi ster and then the master register data is transferred to the slave register. in a compare operation, the slave regi ster value is compared with the coun t value of the tm4 register. when a read operation to the cm4 register is pe rformed, data on the master side is read out. cm4 can be read/written in 16-bit units. cautions 1. a write operation to the cm4 register requires 4 internal system clocks until the value that was set in the cm4 regi ster is transferred to internal units. when writing continuously to the cm4 register , be sure to reserve a time interval of at least 4 internal system clocks. 2. the cm4 register can be overwritten onl y once in a single tm4 register cycle (from 0000h until an intcm4 interrupt is generated due to a matc h of the tm4 register and cm4 register). if this cannot be secured by the application, make sure that the cm4 register is not overwritte n during timer operation. 3. note that an intcm4 interrupt will be generated after an over flow if a value less than the counter value is written in the cm4 register during tm4 re gister operation (figure 9-103). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 cm4 fffff542h 0000h address after reset 0
chapter 9 timer/counter function 399 user?s manual u15195ej5v0ud figure 9-103. example of ti ming during tm4 operation (a) when tm4 < cm4 tm4 tm4cae0 tm4ce0 cm4 intcm4 mn n n remark m = tm4 value when overwritten n = cm4 value after overwrite m < n (b) when tm4 > cm4 tm4 tm4cae0 tm4ce0 cm4 intcm4 m ffffh n n n remark m = tm4 value when overwritten n = cm4 value after overwrite m > n
chapter 9 timer/counter function 400 user?s manual u15195ej5v0ud 9.5.4 control register (1) timer control register 4 (tmc4) the tmc4 register controls the operation of timer 4. this register can be read/written in 8-bit or 1-bit units. caution the tm4cae0 bit and other bits cannot be set at the same time. be sure to set the tm4cae0 bit and then set the other bi ts and the other registers of tm4. 7 0 tmc4 6 cs2 5 cs1 4 cs0 3 0 2 0 <1> tm4ce0 <0> tm4cae0 address fffff544h after reset 00h bit position bit name function selects the tm4 count clock. cs2 cs1 cs0 count clock 0 0 0 f xx /4 0 0 1 f xx /8 0 1 0 f xx /16 0 1 1 f xx /32 1 0 0 f xx /64 1 0 1 f xx /128 1 1 0 f xx /256 1 1 1 f xx /512 6 to 4 cs2 to cs0 caution do not change the cs2 to cs0 bits during timer operation. if they are to be changed, they must be changed after setting the tm4ce0 bit to 0. if the cs2 to cs0 bits are overwritten during timer operation, the operation is not guaranteed. 1 tm4ce0 controls the operation of tm4. 0: count disabled (timer stopped at 0000h and does not operate) 1: count operation performed caution the tm4ce0 bit is not cleared even if a match is detected by the compare operation. to stop the count operation, clear the tm4ce0 bit. 0 tm4cae0 controls the internal count clock. 0: entire tm4 unit asynchr onously reset. base clock (f clk ) supply to tm4 unit stopped. 1: base clock (f clk ) supplied to tm4 unit. cautions 1. when tm4cae0 = 0 is set, the tm4 unit can be reset asynchronously. 2. when tm4cae0 = 0, the tm4 unit is in a reset state. to operate tm4, first set tm4cae0 = 1. 3. when the tm4cae0 bit is changed from 1 to 0, all the registers of the tm4 unit are initialized. when again setting tm4cae0 = 1, be sure to then set all the registers of the tm4 unit again.
chapter 9 timer/counter function 401 user?s manual u15195ej5v0ud 9.5.5 operation (1) compare operation tm4 can be used for a compare operation in which the va lue that was set in the compare register (cm4) is compared with the tm4 count value. if a match is detected by the compare operation, an in terrupt (intcm4) is generated. the generation of the interrupt causes tm4 to be cleared (0) at the next count timing. this function enables timer 4 to be used as an interval timer. cm4 can also be set to 0. in this case, when an ov erflow occurs and tm4 becomes 0, a match is detected and intcm4 is generated. although the tm4 value is cl eared (0) at the next count timing, intcm4 is not generated by this match. figure 9-104. tm4 compare operation example (1/2) (a) when cm4 is set to n (non-zero) 1 tm4 count clock 0 n cm4 n tm4 clear match detection (intcm4) count up clear remark interval time = (n + 1) count clock cycle n = 1 to 65536 (ffffh)
chapter 9 timer/counter function 402 user?s manual u15195ej5v0ud figure 9-104. tm4 compare operation example (2/2) (b) when cm4 is set to 0 1 0 0 0 ffffh overflow tm4 count clock cm4 tm4 clear match detection (intcm4) count up clear remark interval time = (ffffh + 2) count clock cycle
chapter 9 timer/counter function 403 user?s manual u15195ej5v0ud 9.5.6 application example (1) interval timer this section explains an example in which timer 4 is used as an interval timer with 16-bit precision. interrupt requests (intcm4) are out put at equal intervals (refer to figure 9-104 tm4 compare operation example ). the setting procedure is shown below. <1> set (1) the tm4cae0 bit. <2> set each register. ? select the count clock using the cs2 to cs0 bits of the tmc4 register. ? set the compare value in the cm4 register. <3> start counting by setting (1) the tm4ce0 bit. <4> if the tm4 register and cm4 register values match, the intcm4 interrupt is generated. <5> intcm4 interrupts are generated thereafter at equal intervals. 9.5.7 cautions various cautions concerning timer 4 are shown below. (1) to operate tm4, first set (1) the tm4cae0 bit of the tmc4 register. (2) up to 4 internal system clocks are required after a va lue is set in the tm4ce0 bit of the tmc4 register until the set value is transferred to internal units. when a count operation begins, the count cycle from 0000h to 0001h differs from subsequent count cycles. (3) to initialize the tm4 register stat us and start counting again, clear (0) the tm4ce0 bit and then set (1) the tm4ce0 bit after an interval of 4 internal system clocks has elapsed. (4) up to 4 internal system clocks ar e required until the value t hat was set in the cm4 register is transferred to internal units. when writing continuous ly to the cm4 register, be sure to se cure a time interval of at least 4 internal system clocks. (5) the cm4 register can be overwritten only once during a timer/counter oper ation (from 0000h until the intcm4 interrupt is generated due to a match of the tm 4 register and cm4 registe r). if this cannot be secured, make sure that the cm4 register is not overwritten during a ti mer/counter operation. (6) the count clock must not be changed during a timer oper ation. if it is to be overwritten, it should be overwritten after the tm4ce0 bit is cleared (0). if t he count clock is overwritten during a timer operation, operation cannot be guaranteed. (7) an intcm4 interrupt will be generated after an overflow if a value less than the counter value is written in the cm4 register during tm4 register operation.
chapter 9 timer/counter function 404 user?s manual u15195ej5v0ud 9.6 timer connection function 9.6.1 overview the v850e/ia2 provides a function to connect timer 1 and timer 2. figure 9-105. block diagram of timer connection function timer 2 timer 1 cvse10/ cvpe10 cvse20/ cvpe20 capture 0 capture 1 tmic0 tmic1 tmic2 tmic3 tmic0 register intcm1 intcm0 intcm101 intcm100 timer connection selector
chapter 9 timer/counter function 405 user?s manual u15195ej5v0ud 9.6.2 control register (1) timer connection selection register 0 (tmic0) the tmic0 register enables/disables input of the in tcm100 and intcm101 signals to the cvsen0/cvpen0 registers (n = 1, 2). this register can be read/written in 8-bit or 1-bit units. 7 0 tmic0 6 0 5 0 4 0 3 tmic3 2 tmic2 1 tmic1 0 tmic0 address fffff620h after reset 00h bit position bit name function 3 tmic3 enables/disables input of intc m101 signal to cvse20/cvpe20 registers. 0: intcm101 signal not input to cvse20/cvpe20 registers. 1: intcm101 signal input to cvse20/cvpe20 registers. 2 tmic2 enables/disables input of intc m100 signal to cvse20/cvpe20 registers. 0: intcm100 signal not input to cvse20/cvpe20 registers. 1: intcm100 signal input to cvse20/cvpe20 registers. 1 tmic1 enables/disables input of intc m101 signal to cvse10/cvpe10 registers. 0: intcm101 signal not input to cvse10/cvpe10 registers. 1: intcm101 signal input to cvse10/cvpe10 registers. 0 tmic0 enables/disables input of intc m100 signal to cvse10/cvpe10 registers. 0: intcm100 signal not input to cvse10/cvpe10 registers. 1: intcm100 signal input to cvse10/cvpe10 registers.
user?s manual u15195ej5v0ud 406 chapter 10 serial interface function 10.1 features the serial interface function provides two types of serial interfaces combining a total of four transmit/receive channels. three of these channel s can be used simultaneously. the two interface formats are as follows. (1) asynchronous serial interfaces (uart0, uart1): 2 channels (2) clocked serial interfaces (csi0, csi1): 2 channels uart0, uart1, in which one byte of serial data is transmitted/received following a start bit, support full-duplex communication. in the uart1 interface, one higher bit is added to 8 bits of transmit/receive data, enabling communication using 9-bit data. csi0 and csi1 perform data transfer according to three types of signals: serial clocks (sck0, sck1), serial inputs (si0, si1), and serial outputs (so0, so1) (3-wire serial i/o).
chapter 10 serial interface function user?s manual u15195ej5v0ud 407 10.1.1 selecting uart1 or csi1 mode uart1 and csi1 of the v850e/ia2 share pins, and therefore these interfaces cannot be used at the same time. select uart1 or csi1 in advance by using the port 3 mode control register (pmc3) and port 3 function control register (pfc3) (refer to 12.3.4 port 3 ). caution uart1 or csi1 transmissi on/reception operations are not guaran teed if the mode is switched between uart1 and csi1 during tr ansmission or reception. figure 10-1. selecting mode of uart1 or csi1 7 0 pmc3 6 0 5 0 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address fffff446h after reset 00h 7 0 pfc3 6 0 5 0 4 pfc34 3 pfc33 2 pfc32 1 0 0 0 address fffff466h after reset 00h pfc3n pmc3n operation mode 0 0 port i/o mode 0 1 uart1 mode 1 0 port i/o mode 1 1 csi1 mode remark n = 2 to 4
chapter 10 serial interface function user?s manual u15195ej5v0ud 408 10.2 asynchronous serial interface 0 (uart0) 10.2.1 features ? transfer rate: 300 bps to 1,250 kbps (using a dedicated baud rate generator and an internal system clock of 40 mhz) ? full-duplex communications on-chip receive buffer register 0 (rxb0) on-chip transmit buffer register 0 (txb0) ? two-pin configuration note txd0: transmit data output pin rxd0: receive data input pin ? reception error detection functions ? parity error ? framing error ? overrun error ? interrupt sources: 3 types ? reception error interrupt (intser0): interrupt is generated according to the logical or of the three types of reception errors ? reception completion interrupt (intsr0): interrupt is generated when receive data is transferred from the receive shift register to receive buffer register 0 after serial transfer is completed during a reception enabled state ? transmission completion interrupt (intst0): interr upt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed ? the character length of transmit/receive data is specified by to the asim0 register ? character length: 7 or 8 bits ? parity functions: odd, even, 0, or none ? transmission stop bits: 1 or 2 bits ? on-chip dedicated baud rate generator note the sck and cts pins are not available for uart0.
chapter 10 serial interface function user?s manual u15195ej5v0ud 409 10.2.2 configuration uart0 is controlled by asynchronous serial interface m ode register 0 (asim0), asynchronous serial interface status register 0 (asis0), and asynchro nous serial interface transmission status register 0 (asif0). receive data is maintained in receive buffer register 0 (rxb0), and transmi t data is written to transmit buffer register 0 (txb0). figure 10-2 shows the configuration of a synchronous serial interface 0 (uart0). (1) asynchronous serial interfa ce mode register 0 (asim0) the asim0 register is an 8-bit register for specifying the operation of the asynch ronous serial interface. (2) asynchronous serial interfa ce status register 0 (asis0) the asis0 register consists of a set of flags that indicate the error contents when a reception error occurs. the various reception error flags are set (1) when a re ception error occurs and are reset (0) when the asis0 register is read. (3) asynchronous serial interface tran smission status register 0 (asif0) the asif0 register is an 8-bit regist er that indicates the status when a transmit operation is performed. this register consists of a transmit buffer data flag, which indicates the hold status of txb0 data, and the transmit shift register data flag, which indi cates whether transmission is in progress. (4) reception control parity check the receive operation is controlled according to the c ontents set in the asim0 register. a check for parity errors is also performed during a re ceive operation, and if an error is detected, a value corresponding to the error contents is set in the asis0 register. (5) receive shift register this is a shift register that converts the serial data t hat was input to the rxd0 pin to parallel data. one byte of data is received, and if a stop bit is detected, the receive data is transferred to receive buffer register 0 (rxb0). this register cannot be directly manipulated. (6) receive buffer register 0 (rxb0) this is an 8-bit buffer register for holding receive data. when 7 characters are received, 0 is stored in the msb. during a reception enabled state, re ceive data is transferred from the receive shift register to the rxb0 register, synchronized with the end of t he shift-in processing of one frame. also, the reception completion interrupt request (intsr0) is generated by the trans fer of data to the rxb0 register. (7) transmit shift register this is a shift register that converts the parallel data that was transferred from transmit buffer register 0 (txb0) to serial data. when one byte of data is transferred from the txb0 regi ster, the shift register data is output from the txd0 pin. the transmission completion interrupt request (intst0) is generated synchronized with the completion of transmission of one frame. this register cannot be directly manipulated.
chapter 10 serial interface function user?s manual u15195ej5v0ud 410 (8) transmit buffer register 0 (txb0) txb0 is an 8-bit buffer for transmit data. a transmit oper ation is started by writing transmit data to txb0. (9) addition of transmission control parity a transmit operation is controlled by adding a start bit, par ity bit, or stop bit to the dat a that is written to the txb0 register, according to the contents that were set in the asim0 register. figure 10-2. asynchronous seri al interface 0 block diagram parity framing overrun internal bus asynchronous serial interface mode register 0 (asim0) receive buffer register 0 (rxb0) receive shift register reception control parity check transmit buffer register 0 (txb0) transmit shift register addition of transmission control parity brg0 intser0 intsr0 intst0 rxd0 txd0 remark for the configuration of baud rate generator 0, see figure 10-13 .
chapter 10 serial interface function user?s manual u15195ej5v0ud 411 10.2.3 control registers (1) asynchronous serial interfa ce mode register 0 (asim0) the asim0 register is an 8-bit register t hat controls the uart0 transfer operation. this register can be read/written in 8-bit or 1-bit units. cautions 1. when using uart0, be sure to set the external pins related to uart0 functions to the control made before setting cl ock select register 0 (cksr0) and the baud rate generator control register (brgc0), and then set the uartcae0 bit to 1. then set the other bits. 2. set the uartcae0 and rxe0 bits to 1 while a high level is input to the rxd0 pin. if these bits are set to 1 while the pin is at low level, reception is started. (1/3) <7> uartcae0 asim0 <6> txe0 <5> rxe0 4 ps1 3 ps0 2 cl 1 sl 0 isrm address fffffa00h after reset 01h bit position bit name function 7 uartcae0 controls the operating clock. 0: stops clock supply to uart0. 1: supplies clock to uart0. cautions 1. if uartcae0 = 0, uart0 is asynchronously reset note . 2. if uartcae0 = 0, uart0 is reset. to operate uart0, first set uartcae0 to 1. 3. if the uartcae0 bit is cleared from 1 to 0, all the registers of uart0 are initialized. to set uartcae0 to 1 again, be sure to re-set the registers of uart0. the output of the txd0 pin goes high when tr ansmission is disabled, regardless of the setting of the uartcae0 bit. 6 txe0 enables/disables transmission. 0: disables transmission 1: enables transmission cautions 1. set the txe0 bit to 1 after setting the uartcae0 bit to 1 at startup. set the uartcae0 bit to 0 after setting the txe0 bit to 0 to stop. 2. to initialize the transmission unit, clear (0) the txe0 bit, and after letting 2 clock cycles (base clock) elapse, set (1) the txe0 bit again. if the txe0 bit is not set again, initialization may not be successful. (for details about the base clock, refer to 10.2.6 (1) (a) base clock (clock).) note the asis0, asif0, and rxb0 registers are reset.
chapter 10 serial interface function user?s manual u15195ej5v0ud 412 (2/3) bit position bit name function 5 rxe0 enables/disables reception. 0: disables reception note 1: enables reception cautions 1. set the rxe0 bit to 1 after setting the uartcae0 bit to 1 at startup. set the uartcae0 bit to 0 after setting the rxe0 bit to 0 to stop. 2. to initialize the reception unit status, clear (0) the rxe0 bit, and after letting 2 clock cycles (base clock) elapse, set (1) the rxe0 bit again. if the rxe0 bit is not set again, initialization may not be successful. (for details about the base clock, refer to 10.2.6 (1) (a) base clock (clock).) controls parity bit. ps1 ps0 transmit operation receive operation 0 0 don?t output parity bit receive with no parity 0 1 output 0 parity receive as 0 parity 1 0 output odd parity judge as odd parity 1 1 output even parity judge as even parity cautions 1. to overwrite the ps1 and ps0 bits, first clear (0) the txe0 and rxe0 bits. 2. if ?0 parity? is selected for reception, no parity judgment is performed. therefore, no error interrupt is generated because the pe bit of the asis0 register is not set. 4, 3 ps1, ps0 ? even parity if the transmit data contains an odd number of bits with the value ?1?, the parity bit is set (1). if it contains an even number of bits with the value ?1?, the parity bit is cleared (0). this controls the num ber of bits with the value ?1? contained in the transmit data and the parity bit so that it is an even number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. ? odd parity in contrast to even parity, odd parity c ontrols the number of bits with the value ?1? contained in the transmit data and the parity bit so that it is an odd number. during reception, the number of bits wi th the value ?1? contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. note when reception is disabled, the receive shift register does not detect a start bit. no shift-in processing or transfer processing to receive buffer register 0 (rxb0) is performed, and t he contents of the rxb0 register are retained. when reception is enabled, the reception shift operat ion starts, synchronized with the detection of the start bit, and when the reception of one frame is comp leted, the contents of t he receive shift register are transferred to the rxb0 register. a reception completion interrupt (intsr0) is also generated in synchronization with the transfer to the rxb0 register.
chapter 10 serial interface function user?s manual u15195ej5v0ud 413 (3/3) bit position bit name function 4, 3 ps1, ps0 ? 0 parity during transmission, the parity bit is cleared (0) regardless of the transmit data. during reception, no parity error is gener ated because no parity bit is checked. ? no parity no parity bit is added to transmit data. during reception, the receive data is considered to have no parity bit. no parity error is generated because there is no parity bit. 2 cl specifies character length of 1 frame of transmit/receive data. 0: 7 bits 1: 8 bits caution to overwrite the cl bit, first clear (0) the txe0 and rxe0 bits. 1 sl specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits cautions 1. to overwrite the sl bit, first clear (0) the txe0 bit. 2. since reception is always done with a stop bit length of 1, the sl bit setting does not affect receive operations. 0 isrm enables/disables generation of reception completion interrupt requests when an error occurs. 0: generate a reception error interrupt request (intser0) as an interrupt when an error occurs. in this case, no reception completi on interrupt request (intsr0) is generated. 1: generate a reception completion interrupt request (intsr0) as an interrupt when an error occurs. in this case, no reception error inte rrupt request (intser0) is generated. caution to overwrite the isrm bit, first clear (0) the rxe0 bit.
chapter 10 serial interface function user?s manual u15195ej5v0ud 414 (2) asynchronous serial interfa ce status register 0 (asis0) the asis0 register, which consists of 3-bit error fl ags (pe, fe and ove), indicates the error status when uart0 reception is complete. the asis0 register is cleared to 00h by a read oper ation. when a reception error occurs, receive buffer register 0 (rxb0) should be read and the error flag sh ould be cleared after the asis0 register is read. this register is read-only, in 8-bit units. cautions 1. when the uartcae0 bit or rxe0 bit of th e asim0 register is set to 0, or when the asis0 register is read, the pe, fe, and ove bits of the asis0 register are cleared (0). 2. manipulation using a bit manipu lation instruction is prohibited. 7 6 5 4 3 2 1 0 address after reset asis0 0 0 0 0 0 pe fe ove fffffa03h 00h bit position bit name function 2 pe this is a status flag that indicates a parity error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both set to 0, or after the asis0 register is read 1: when the receive data parity does not match the parity bit after receive completion caution the operation of the pe bit differs according to the settings of the ps1 and ps0 bits of the asim0 register. 1 fe this is a status flag that indicates a framing error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both set to 0, or after the asis0 register is read 1: when no stop bit was detected after receive completion caution for receive data stop bits, only the first bit is checked regardless of the stop bit length. 0 ove this is a status flag that indicates an overrun error. 0: when the asim0 register?s uartcae0 and rxe0 bits are both 0, or after the asis0 register is read. 1: when uart0 completed the next receive operation before reading the receive data in the rxb0 register. caution when an overrun error occurs, the next receive data value is not written to the rxb0 register and the data is discarded.
chapter 10 serial interface function user?s manual u15195ej5v0ud 415 (3) asynchronous serial interface tran smission status register 0 (asif0) the asif0 register, which consists of 2-bit stat us flags, indicates the status during transmission. by writing the next data to the txb0 register after data is transferred from the txb0 register to the transmit shift register, transmit operations can be performed conti nuously without suspension even during an interrupt interval. when transmission is performed continuously, data should be written after referencing the txbf0 bit of the asif0 register to prevent writ ing to the txb0 register by mistake. this register is read-only, in 8-bit or 1-bit units. 7 6 5 4 3 2 <1> <0> address after reset asif0 0 0 0 0 0 0 txbf0 txsf0 fffffa05h 00h bit position bit name function 1 txbf0 this is a transmit buffer data flag. 0: data to be transferred next to txb0 register does not exist (when the asim0 register?s uartcae0 or txe0 bits is 0, or when data has been transferred to the transmit shift register) 1: data to be transferred next exists in txb0 register (data exists in txb0 register when the txb0 register has been written to) caution when transmission is performed continuously, data should be written to the txb0 register after confirming that this flag is 0. if writing to txb0 register is performed when this flag is 1, transmit data cannot be guaranteed . 0 txsf0 this is a transmit shift register data fl ag. it indicates the transmission status of uart0. 0: initial status or a waiting trans mission (when the asim0 register?s uartcae0 or txe0 bits is set to 0, or when following transmission completion, the next data transfer from the txb0 register is not performed) 1: transmission in progress (when data has been transferred from the txb0 register) caution when the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt (intst0). if initialization is performed when this flag is 1, transmit data cannot be guaranteed.
chapter 10 serial interface function user?s manual u15195ej5v0ud 416 (4) receive buffer register (rxb0) the rxb0 register is an 8-bit buffer register for stor ing parallel data that had been converted by the receive shift register. when reception is enabled (rxe0 bit = 1 in the asim0 re gister), receive data is tr ansferred from the receive shift register to the rxb0 register, synchronized with t he completion of the shift-in processing of one frame. also, a reception completion interrupt request (intsr0) is generated by the transfer to the rxb0 register. for information about the timing for generat ing this interrupt request, refer to 10.2.5 (4) receive operation . if reception is disabled (rxe0 bit = 0 in the asim0 regi ster), the contents of the r xb0 register are retained, and no processing is performed for transferring data to the rxb0 register even when the shift-in processing of one frame is completed. also, no intsr0 signal is generated. when 7 bits is specified for the data length, bits 6 to 0 of the rxb0 register are transferred for the receive data and the msb (bit 7) is always 0. however, if an overrun error (ove bit of asis0 register = 1) occurs, the receive data at that time is not transferred to the rxb0 register. except when a reset is input, the rxb0 register bec omes ffh even when uartcae0 bit = 0 in the asim0 register. this register is read-only, in 8-bit units. 7 6 5 4 3 2 1 0 address after reset rxb0 rxb7 rxb6 rxb5 rxb4 rxb3 rxb2 rxb1 rxb0 fffffa02h ffh bit position bit name function 7 to 0 rxb7 to rxb0 stores receive data. 0 can be read for rxb7 when 7-bit or character data is received.
chapter 10 serial interface function user?s manual u15195ej5v0ud 417 (5) transmit buffer register 0 (txb0) the txb0 register is an 8-bit buffe r register for setting transmit data. when transmission is enabled (txe0 bit = 1 in the asim0 register), the transmit operation is started by writing data to txb0 register. when transmission is disabled (txe0 bit = 0 in the asim0 register), even if data is written to txb0 register, the value is ignored. the txb0 register data is transferred to the transmit shift register, and a transmission completion interrupt request (intst0) is generated, synch ronized with the completion of the transmission of one frame from the transmit shift register. for information about the ti ming for generating this interrupt request, refer to 10.2.5 (2) transmit operation . when txbf0 bit = 1 in the asif0 register, writ ing must not be performed to txb0 register. this register can be read or written in 8-bit units. 7 6 5 4 3 2 1 0 address after reset txb0 txb7 txb6 txb5 txb4 txb3 txb2 txb1 txb0 fffffa04h ffh bit position bit name function 7 to 0 txb7 to txb0 writes transmit data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 418 10.2.4 interrupt requests the following three types of interrupt requests are generated from uart0. ? reception completion interrupt (intsr0) ? transmission completion interrupt (intst0) ? reception error interrupt (intser0) the default priorities among these thre e types of interrupt requests is, from high to low, reception completion interrupt, transmission completion inte rrupt, and reception error interrupt. table 10-1. generated inte rrupts and default priorities interrupt priority reception completion 1 transmission completion 2 reception error 3 (1) reception completion interrupt (intsr0) when reception is enabled, an intsr0 signal is generated when data is shifted in to the receive shift register and transferred to receive buffer register 0 (rxb0). an intsr0 signal can be generated in place of a recept ion error interrupt (intser0) according to the isrm bit of the asim0 register even w hen a reception error has occurred. when reception is disabled, no intsr0 signal is generated. (2) transmission completion interrupt (intst0) an intst0 signal is generated when one frame of transmi t data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. (3) reception error interrupt (intser0) when reception is enabled, an intser0 signal is generat ed according to the logical or of the three types of reception errors explained for the asis0 register. whether an intser0 signal or an intsr0 signal is generated when an error occurs can be specified using the isrm bit of the asim0 register. when reception is disabled, no intser0 signal is generated.
chapter 10 serial interface function user?s manual u15195ej5v0ud 419 10.2.5 operation (1) data format full-duplex serial data transmission and reception can be performed. the transmit/receive data format consis ts of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in figure 10-3. the character bit length within one data frame, the ty pe of parity, and the st op bit length are specified according to asynchronous serial interface mode register 0 (asim0). also, data is transferred with lsb first. figure 10-3. asynchronous serial interface transmit/receive data format 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bits character bits ? start bit 1 bit ? character bits 7 bits or 8 bits ? parity bit even parity, odd parity, 0 parity, or no parity ? stop bits 1 bit or 2 bits
chapter 10 serial interface function user?s manual u15195ej5v0ud 420 (2) transmit operation when the uartcae0 bit is set to 1 in the asim0 regi ster, a high level is output from the txd0 pin. then, when the txe0 bit is set to 1 in the asim0 r egister, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register 0 (txb0). (a) transmission enabled state this state is set by the txe0 bit in the asim0 register. ? txe0 = 1: transmission enabled state ? txe0 = 0: transmission disabled state since uart0 does not have a cts (transmission enab led signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) starting a transmit operation in the transmission enabled state, a transmit operation is started by writing transmit data to transmit buffer register 0 (txb0). when a transmit operation is started, the data in the txb0 register is transferred to transmit shift register. then, the transm it shift register outputs data to the txd0 pin (the transmit data is transferred sequentially starting with the start bit). the start bit, parity bit, and stop bits are added automatically. (c) transmission interrupt request when the transmit shift register becomes empty, a transmission comple tion interrupt request (intst0) is generated. the timing for generating the intst0 signal differs according to the specification of the stop bit length. the intst0 signal is generated at t he same time that the last stop bit is output. if the data to be transmitted next has not been written to the txb0 regi ster, the transmit operation is suspended. caution normally, when the transm it shift register becomes empt y, a transmission completion interrupt (intst0) is generate d. however, no intst0 signal is generated if the transmit shift register becomes empty due to the input of reset.
chapter 10 serial interface function user?s manual u15195ej5v0ud 421 figure 10-4. asynchronous serial interf ace transmission comple tion interrupt timing start stop d0 d1 d2 d6 d7 parity parity txd0 (output) intst0 (output) start d0 d1 d2 d6 d7 txd0 (output) intst0 (output) (a) stop bit length: 1 (b) stop bit length: 2 stop
chapter 10 serial interface function user?s manual u15195ej5v0ud 422 (3) continuous transmission operation uart0 can write the next transmit data to the txb0 register at the timing that the transmit shift register starts the shift operation. this enables an efficient transmi ssion rate to be realized by continuously transmitting data even during the servicing of the transmission completi on interrupt (intst0) after the transmission of one data frame. in addition, reading the t xsf0 bit of the asif0 register afte r the generation of an intst0 signal enables the txb0 register to be efficiently written twic e (2 bytes) without waiting for the transmission of 1 data frame. when continuous transmission is performed, data should be written after referencing the asif0 register to confirm the transmission status and whether or not data can be written to the txb0 register. caution the txbf0 and txsf0 bits of the asif0 register change ?10? ?11? ?01? during continuous transmission. the refore, do not confirm the status based on the combination of the txbf0 and txsf0 bits. judge the status based only on the txbf0 bi t when performing continuous transmission. txbf0 whether or not writing to txb0 register is enabled 0 writing is enabled 1 writing is not enabled caution when transmission is perfo rmed continuously, write the first tr ansmit data (first byte) to the txb0 register and confirm that the txbf0 bit is 0, and then write the next transmit data (second byte) to txb0 register. if writing to the txb0 register is performed when the txbf0 bit is 1, transmit data cannot be guaranteed. the communication status can be confirmed with the txsf0 bit. txsf0 transmission status 0 transmission is completed. 1 under transmission. cautions 1. when initializing the transmission uni t when continuous tran smission is completed, confirm that the txbf0 bit is 0 after the occurrence of the tr ansmission completion interrupt, and then execute initialization. if initialization is performed when the txbf0 bit is 1, transmit data cannot be guaranteed. 2. while transmission is bein g performed continuously, an o verrun error may occur if the next transmission is comple ted before the intst0 inte rrupt servicing following the transmission of 1 data frame is executed. an overrun error can be detected by embedding a program that can count the num ber of transmit da ta and referencing txsf0 bit.
chapter 10 serial interface function user?s manual u15195ej5v0ud 423 figure 10-5. continuous transmission processing flow set registers interrupt occurrence wait for interrupt required number of transfers performed? write the first byte of the transmit data to txb0 register write transmit data to txb0 register when reading asif0 register, txbf0 = 0? when reading asif0 register, txsf0 = 1? when reading asif0 register, txsf0 = 0? no no no no yes yes yes yes end of transmission processing write the second byte of the transmit data to the txb0 register.
chapter 10 serial interface function user?s manual u15195ej5v0ud 424 (a) starting procedure the procedure to start continuous transmission is shown below. figure 10-6. continuous tr ansmission starting procedure txd0 (output) data (1) data (2) <5> <1> <2> <4> intst0 (output) txb0 register ffh ffh data (1) data (2) data (3) data (1) data (2) data (3) <3> asif0 register (txbf0, txsf0 bits) 00 11 note 11 01 01 11 01 11 txs0 register start bit stop bit stop bit start bit 10 note refer to 10.2.7 cautions (2) . asif0 register transmission starting procedure internal operation txbf0 txsf0 ? set transmission mode <1> start transmission unit 0 0 ? write data (1) 1 0 <2> generate start bit ? read asif0 register (confirm that txbf0 bit = 0) start data (1) transmission 1 0 0 0 1 note 1 1 1 ? write data (2) <> 1 1 <3> intst0 interrupt occurs ? read asif0 register (confirm that txbf0 bit = 0) 0 0 1 1 ? write data (3) <4> generate start bit start data (2) transmission <> 1 1 <5> intst0 interrupt occurs ? read asif0 register (confirm that txbf0 bit = 0) 0 0 1 1 ? write data (4) 1 1 note refer to 10.2.7 cautions (2) .
chapter 10 serial interface function user?s manual u15195ej5v0ud 425 (b) ending procedure the procedure for ending continuous transmission is shown below. figure 10-7. continuous transmission end procedure txd0 (output) data (m ? 1) data (m) <11> <7> <6> <8> <10> intst0 (output) txb0 register data (m ? 1) data (m ? 1) data (m) ffh data (m) <9> asif0 register (txbf0, txsf0 bits) uartcae0 bit or txe0 bit 11 01 11 01 00 transmit shift register start bit start bit stop bit stop bit asif0 register transmission end procedure internal operation txbf0 txsf0 <6> transmission of data (m ? 2) is in progress 1 1 <7> intst0 interrupt occurs ? read asif0 register (confirm that txbf0 bit = 0) 0 0 1 1 ? write data (m) <8> generate start bit start data (m ? 1) transmission <> 1 1 <9> intst0 interrupt occurs ? read asif0 register (confirm that txsf0 bit = 1) there is no write data <10> generate start bit start data (m) transmission <> 0 0 1 1 <11> generate intst0 interrupt ? read asif0 register (confirm that txsf0 bit = 0) ? clear (0) the uartcae0 bit or txe0 bit initialize internal circuits 0 0 0 0
chapter 10 serial interface function user?s manual u15195ej5v0ud 426 (4) receive operation the awaiting reception state is set by setting the uart cae0 bit to 1 in the asim0 register and then setting the rxe0 bit to 1 in the asim0 register. to start recept ion, start sampling at the falling edge of the rxd0 pin upon detection of the falling edge. if the rxd0 pin is at low level at the sampling point of a start bit, the start bit is recognized. when the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. a reception completion interrupt (intsr0) is generated each time the reception of one frame of data is comple ted. normally, the receive data is transferred from receive buffer register 0 (rxb0) to me mory by this interrupt servicing. (a) reception enabled state the receive operation is set to the reception enabled state by setting the rxe0 bit in the asim0 register to 1. ? rxe0 bit = 1: reception enabled state ? rxe0 bit = 0: reception disabled state in reception disabled state, the rece ption hardware stands by in the initial state. at this time, the contents of receive buffer register 0 (rxb0) are retained, and no reception completion interrupt or reception error interrupt is generated. (b) starting a receive operation a receive operation is started by the detection of a start bit. the rxd0 pin is sampled using the serial clock from baud rate generator 0 (brg0). (c) reception completion interrupt when rxe0 = 1 in the asim0 register and the reception of one frame of data is completed (the stop bit is detected), a reception completion in terrupt (intsr0) is generated and the receive data in the receive shift register is transferred to the rxb0 register at the same time. also, if an overrun error (ove bit of asis0 register = 1) occurs, the receive data at that time is not transferred to receive buffer register 0 (rxb0), and eit her an intsr0 signal or a reception error interrupt (intser0) is generated according to the is rm bit setting in the asim0 register. even if a parity error (pe bit of asis0 register = 1) or framing error (fe bit of asis0 register = 1) occurs during a reception operation, the re ceive operation continues until stop bit is received, and after reception is completed, either an intsr0 signal or an in tser0 signal is generated according to the isrm bit setting in the asim0 register (the receive data in the receive shift register is transferred to the rxb0 register). if the rxe0 bit is cleared (0) during a receive operatio n, the receive operation is immediately stopped. the contents of receive buffer regist er 0 (rxb0) and of the asynchronous serial interface status register (asis0) at this time do not change, and no intsr0 or intser0 signal is generated. no intsr0 or intser0 signal is generat ed when rxe0 = 0 (reception is disabled).
chapter 10 serial interface function user?s manual u15195ej5v0ud 427 figure 10-8. asynchronous serial interf ace reception completion interrupt timing start d0 d1 d2 d6 d7 rxd0 (input) intsr0 (output) rxb0 register parity stop cautions 1. be sure to read recei ve buffer register 0 (rxb0) even when a reception error occurs. if the rxb0 register is not read , an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. reception is always performed assuming a stop bit length of 1. a second stop bit is ignored. (5) reception error the three types of errors that can occur during a re ceive operation are a parity error, framing error, and overrun error. as a result of dat a reception, the various flags of t he asis0 register are set (1), and a reception error interrupt (intser0) or a reception completion interrupt (intsr0) is generated at the same time. the isrm bit of the asim0 register specifies whether an intser0 or intsr0 signal is generated. the type of error that occurred during reception c an be detected by reading th e contents of the asis0 register during the intser0 or intsr0 interrupt servicing. the contents of the asis0 r egister are cleared (0) by reading the asis0 register. table 10-2. reception error causes error flag reception error cause pe parity error the parity specificat ion during transmission did not match the parity of the reception data fe framing error no stop bit was detected ove overrun error the reception of the next data was completed before data was read from receive buffer register 0 (rxb0)
chapter 10 serial interface function user?s manual u15195ej5v0ud 428 (a) separation of rece ption error interrupt a reception error interrupt can be separated from the intsr0 signal and generated as the intser0 signal by clearing the isrm bit of the asim0 register to 0. figure 10-9. when reception error interrupt is separated from intsr0 signal (isrm bit = 0) (a) no error occurs during reception (b) an e rror occurs during reception intsr0 signal (output) (reception completion interrupt) intser0 signal (output) (reception error interrupt) intsr0 signal (output) (reception completion interrupt) intser0 signal (output) (reception error interrupt) intsr0 signal does not occur figure 10-10. when reception error interrupt is included in intsr0 signal (isrm bit = 1) (a) no error occurs during reception (b) an erro r occurs during reception intsr0 signal (output) (reception completion interrupt) intser0 signal (output) (reception error interrupt) intsr0 signal (output) (reception completion interrupt) intser0 signal (output) (reception error interrupt) intser0 signal does not occur
chapter 10 serial interface function user?s manual u15195ej5v0ud 429 (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used on the transmission and reception sides. (a) even parity (i) during transmission the parity bit is controlled so t hat the number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) odd parity (i) during transmission in contrast to even parity, the parity bit is contro lled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 (ii) during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated.
chapter 10 serial interface function user?s manual u15195ej5v0ud 430 (7) receive data noise filter the rxd0 signal is sampled at the rising edge of the prescaler output base clock (f clk ). if the same sampling value is obtained twice, the match detector output c hanges, and this output is sampled as input data. therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see figure 10-12 ). refer to 10.2.6 (1) (a) base clock (clock) regarding the base clock. also, since the circuit is configured as shown in figur e 10-11, internal processing during a receive operation is delayed by up to 2 clocks accord ing to the external signal status. figure 10-11. noise filter circuit rxd0 f clk q clock in ld_en q in internal signal a internal signal b match detector figure 10-12. timing of rx d0 signal judged as noise internal signal a clock rxd0 (input) internal signal b match mismatch (judged as noise) mismatch (judged as noise) match
chapter 10 serial interface function user?s manual u15195ej5v0ud 431 10.2.6 dedicated baud ra te generator 0 (brg0) a dedicated baud rate generator, which consists of a s ource clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by uart0. the dedicated baud ra te generator output can be selected as the serial clock for each channel. separate 8-bit counters exist fo r transmission and for reception. (1) baud rate generator 0 (brg0) configuration figure 10-13. configuration of baud rate generator 0 (brg0) f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 clock (f clk ) selector uartcae0 8-bit counter match detector baud rate brgc0: mdl7 to mdl0 1/2 uartcae0 and txe0 (or rxe0) cksr0: tps3 to tps0 f xx remark f xx : internal system clock (a) base clock (clock) when the uartcae0 bit = 1 in the asim0 register, t he clock selected according to the tps3 to tps0 bits of the cksr0 register is supplied to the transmi ssion/reception unit. this clock is called the base clock (f clk ). when uartcae0 = 0, f clk is fixed to low level.
chapter 10 serial interface function user?s manual u15195ej5v0ud 432 (2) serial clock generation a serial clock can be generated according to the settings of the cksr0 and brgc0 registers. the base clock to the 8-bit counter is selected by the tps3 to tps0 bits of the cksr0 register. the 8-bit counter divisor value can be set by t he mdl7 to mdl0 bits of the brgc0 register. (a) clock select register 0 (cksr0) the cksr0 register is an 8-bit regist er for selecting the base clock (f clk ) using the tps3 to tps0 bits. the clock selected by the tps3 to t ps0 bits becomes the base clock (f clk ) of the transmission/ reception module. this register can be read or written in 8-bit units. cautions 1. the maximum allowabl e frequency of the base clock (f clk ) is 20 mhz. therefore, when the system clock?s freque ncy is 40 mhz, tps3 to t ps0 bits cannot be set to 0000b. at 40 mhz, set the tps3 to tps0 bits to a value other than 0000b, and set the uartcae0 bit of the asim0 register to 1. 2. set the uartcae0 bit of the asim0 register to 0 before rewriting the tps3 to tps0 bits. 7 6 5 4 3 2 1 0 address after reset cksr0 0 0 0 0 tps3 tps2 tps1 tps0 fffffa06h 00h bit position bit name function specifies the base clock (f clk ) tps3 tps2 tps1 tps0 base clock (f clk ) 0 0 0 0 f xx 0 0 0 1 f xx /2 0 0 1 0 f xx /4 0 0 1 1 f xx /8 0 1 0 0 f xx /16 0 1 0 1 f xx /32 0 1 1 0 f xx /64 0 1 1 1 f xx /128 1 0 0 0 f xx /256 1 0 0 1 f xx /512 1 0 1 0 f xx /1,024 1 0 1 1 f xx /2,048 1 1 arbitrary arbitrary setting prohibited 3 to 0 tps3 to tps0 remark f xx : internal system clock
chapter 10 serial interface function user?s manual u15195ej5v0ud 433 (b) baud rate generator c ontrol register 0 (brgc0) the brgc0 register is an 8-bit regist er that controls the baud rate (serial transfer speed) of uart0. this register can be read or written in 8-bit units. caution if the mdl7 to mdl0 bits are to be ov erwritten, the txe0 and rxe0 bits should be set to 0 in the asim0 register first. 7 6 5 4 3 2 1 0 address after reset brgc0 mdl7 mdl6 mdl5 mdl4 mdl3 mdl2 mdl1 mdl0 fffffa07h ffh bit position bit name function specifies the 8-bit counter?s division value. mdl7 mdl6 mdl5 mdl4 mdl3 mdl2 mdl1 mdl0 division value (k) serial clock 0 0 0 0 0 ? setting prohibited 0 0 0 0 1 0 0 0 8 f clk /8 0 0 0 0 1 0 0 1 9 f clk /9 0 0 0 0 1 0 1 0 10 f clk /10 1 1 1 1 1 0 1 0 250 f clk /250 1 1 1 1 1 0 1 1 251 f clk /251 1 1 1 1 1 1 0 0 252 f clk /252 1 1 1 1 1 1 0 1 253 f clk /253 1 1 1 1 1 1 1 0 254 f clk /254 1 1 1 1 1 1 1 1 255 f clk /255 7 to 0 mdl7 to mdl0 remarks 1. f clk : frequency [hz] of base clock selected by tps3 to tps0 bits of cksr0 register 2. k: value set by mdl7 to mdl0 bits (k = 8, 9, 10, ..., 255) 3. the baud rate is the output clock fo r the 8-bit counter divided by 2 4. : don?t care ... ? ? ? ? ? ? ? ? ?
chapter 10 serial interface function user?s manual u15195ej5v0ud 434 (c) baud rate the baud rate is the value obtained by the following formula. baud rate = [bps] f clk = frequency [hz] of base clock selected by tps3 to tps0 bits of cksr0 register. k = value set by mdl7 to mdl0 bits of brgc0 register (k = 8, 9, 10, ..., 255) (d) baud rate error the baud rate error is obtained by the following formula. [%] 100 1 rate) baud (normal rate baud desired error) with rate (baud rate baud actual (%) error ? ? ? ? ? ? ? ? ? = cautions 1. make sure that the baud rate erro r during transmission does not exceed the allowable error of the reception destination. 2. make sure that the baud rate error duri ng reception is within th e allowable baud rate range during reception, which is describ ed in (4) allowable baud rate during reception. example: base clock frequency = 20 mhz = 20,000,000 hz setting of mdl7 to mdl0 bits in brgc0 register = 01000001b (k = 65) target baud rate = 153,600 bps baud rate = 20m/(2 65) = 20,000,000/(2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] f clk 2 k tar g et
chapter 10 serial interface function user?s manual u15195ej5v0ud 435 (3) baud rate setting example table 10-3. baud rate generator setting data f xx = 40 mhz f xx = 33 mhz f xx = 10 mhz baud rate (bps) f clk k err f clk k err f clk k err 300 f xx /2 10 65 0.16 f xx /2 8 215 ?0.07 f xx /2 7 130 0.16 600 f xx /2 9 65 0.16 f xx /2 7 215 ?0.07 f xx /2 6 130 0.16 1200 f xx /2 8 65 0.16 f xx /2 6 215 ?0.07 f xx /2 5 130 0.16 2400 f xx /2 7 65 0.16 f xx /2 5 215 ?0.07 f xx /2 4 130 0.16 4800 f xx /2 6 65 0.16 f xx /2 4 215 ?0.07 f xx /2 3 130 0.16 9600 f xx /2 5 65 0.16 f xx /2 3 215 ?0.07 f xx /2 2 130 0.16 19200 f xx /2 4 65 0.16 f xx /2 2 215 ?0.07 f xx /2 1 130 0.16 31250 f xx /2 3 80 0 f xx /2 2 132 0 f xx /2 1 80 0 38400 f xx /2 3 65 0.16 f xx /2 1 215 ?0.07 f xx /2 0 130 0.16 76800 f xx /2 2 65 0.16 f xx /2 1 107 0.39 f xx /2 0 65 0.16 153600 f xx /2 1 65 0.16 f xx /2 1 54 ?0.54 f xx /2 0 33 ?1.36 312500 f xx /2 1 32 0 f xx /2 1 26 1.54 f xx /2 0 16 0 625000 f xx /2 1 16 0 f xx /2 1 13 1.54 f xx /2 0 8 0 1250000 f xx /2 1 8 0 f xx /2 1 8 ? 17.5 ? ? ? caution the maximum allowable frequency of the base clock (f clk ) is 20 mhz. remarks f xx : internal system clock frequency f clk : base clock frequency k: setting values of mdl7 to mdl0 bits in brgc0 register err: baud rate error [%]
chapter 10 serial interface function user?s manual u15195ej5v0ud 436 (4) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 10-14. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uart0 transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 10-14, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the brgc 0 register. if all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uart0 baud rate k: brgc0 register setting value fl: 1-bit data length when the latch timing margin is 2 base clocks, the minimum allowable transfer rate (flmin) is as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? =
chapter 10 serial interface function user?s manual u15195ej5v0ud 437 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate the allowable baud rate error of uart0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. table 10-4. maximum and mini mum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ?3.61% 20 +4.26% ?4.31% 50 +4.56% ?4.58% 100 +4.66% ?4.67% 255 +4.72% ?4.73% remarks 1. the reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). the higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: brgc0 register setting value 22k 21k + 2 20k 21k ? 2
chapter 10 serial interface function user?s manual u15195ej5v0ud 438 (5) transfer rate durin g continuous transmission during continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. however, on the re ception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. figure 10-15. transfer rate during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame bit 0 fl fl fl fl fl fl flstp start bit of second byte start bit representing the 1-bit data length by fl, the stop bit length by flstp, and the base clock frequency by f clk yields the following equation. flstp = fl + 2/f clk therefore, the transfer rate duri ng continuous transmission is as follows. (when stop bit length = 1) transfer rate = 11 fl + (2/f clk ) 10.2.7 cautions cautions to be observed when using uart0 are shown below. (1) when the supply of clocks to uart 0 is stopped (for example, in idle or software stop mode), operation stops with each register retaining the value it had imme diately before the supply of clocks was stopped. the txd0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. however, operation is not gua ranteed after the supply of clocks is rest arted. therefore, after the supply of clocks is restarted, the circuits should be initialized by setting uartcae0 = 0, rxe0 = 0, and txe0 = 0 in the asim0 register. (2) uart0 has a 2-stage buffer configuration consisting of transmit buffer register 0 (txb0) and the transmit shift register, and has status flags (the t xbf0 and txsf0 bits of the asif0 regist er) that indicate the status of each buffer. when the txbf 0 and txsf0 bits are read at the same time during continuous transmission, the read values change ?10? ?11? ?01?. judge the timing for writing the next data to the txb0 register by reading only the txbf0 bit when performing continuous transmission.
chapter 10 serial interface function user?s manual u15195ej5v0ud 439 10.3 asynchronous serial interface 1 (uart1) 10.3.1 features ? clocked (synchronous) mode/asynchronous mode can be selected ? operation clock synchronous mode: baud rate generator/external clock selectable asynchronous mode: baud rate generator ? transfer rate 300 bps to 153,600 bps (in asynchronous mode, f xx = 40 mhz) 4800 bps to 1000000 bps (in synchronous mode) ? full-duplex communications (lsb first) on-chip receive buffer register 1 (rxb1) ? three-pin configuration txd1: transmit data output pin rxd1: receive data input pin asck1: synchronous serial clock i/o ? reception error detection function ? parity error ? framing error ? overrun error ? interrupt sources: 2 types ? reception completion interrupt (intsr1): interrupt is generated when receive data is transferred from the shift register to receive buffer register 1 (rxb1) after serial transfer is completed during a reception enabled state. ? transmission completion interrupt (intst1): interrupt is generated when the serial transmission of trans- mit data (8/7 bits) from the shift register is completed. ? the character length of transmit/receive data is specified by the asim10 r egister (extension bits are specified by the asim11 register) ? character length: 7 or 8 bits 9 bits (when extension bit is added) ? parity functions: odd, even, 0, or no parity ? transmission stop bits: 1 or 2 bits ? communication mode: 1-frame transfer or 2-frame continuous transfer enabled ? on-chip dedicated baud rate generator remark f xx : internal system clock
chapter 10 serial interface function user?s manual u15195ej5v0ud 440 10.3.2 configuration uart1 is controlled by asynchronous serial interface mode register 10 and 11 (asim10 and asim11) and asynchronous serial interface status r egister 1 (asis1). receive data is hel d in the receive buffer registers (rxb1 and rxbl1), and transmit data is held in the transmit shift registers (txs1 and txsl1). figure 10-16 shows the configuration of as ynchronous serial interface 1 (uart1). (1) asynchronous serial inte rface mode registers 10, 11 (asim10, asim11) the asim10 and asim11 registers are 8- bit registers that specify the oper ation of the asynchronous serial interface. (2) asynchronous serial interface status register 1 (asis1) the asis1 register consists of a transmission status flag (sot1), recept ion status flag (sir1), a bit (rb8) that indicates the 9th bit when extension bit addition is enabled, and 3-bit error flags (pe1, fe1, ove1) that indicate the error status at reception end. (3) reception control parity check the receive operation is controlled according to t he contents set in the asim 10 and asim11 registers. a check for parity errors is also performed during rece ive operation, and if an e rror is detected, a value corresponding to the error contents is set in the asis1 register. (4) 2-frame continuous reception buffer register (rxb1)/recei ve buffer register (rxbl1) rxb1 is a 16-bit (during 2-frame cont inuous reception, 9-bit extension da ta reception) buffer register that holds receive data. during 7 or 8 bit char acter reception, 0 is stored in the msb. for 16-bit access to this register, specify rxb1, and for access to the lower 8 bits, specify rxbl1. in the reception enabled state, receive data is transferr ed from the receive shift register to the reception buffer in synchronization with the completion of shift-in processing of one frame. a reception completion interrupt request (intsr1) is generated upon transfer to the reception buffer (when 2- frame continuous reception is s pecified, reception buffer transmission of the second frame). (5) 2-frame continuous transmission shift regist er (txs1)/transmit shi ft registers (txsl1) txs1 is a 9-bit/2-frame continuous transmission processi ng shift register. transmission is started by writing data to this register. a transmission completion interrupt request (intst1) is generat ed in synchronization with the end of transmission of 1 frame or 2 frames including the txs1 data. for 16-bit access to this register, specify txs1, and for access to the lower 8 bits, specify txsl1. (6) addition of transmission control parity a transmission operation is controlled by adding a start bit, par ity bit, or stop bit to the data that is written to the txs1 or txsl1 register, according to the contents set in the asim 10, asim11 registers. (7) selector the selector selects the serial clock source.
chapter 10 serial interface function user?s manual u15195ej5v0ud 441 figure 10-16. block diagram of asynchronous serial interface 1 transmit shift registers (txs1, txsl1) asynchronous serial interface mode registers 10, 11 (asim10, asim11) asynchronous serial interface status registers 1 (asis1) transmission control parity addition reception buffers 1, l1 (rxb1, rxbl1) pe1 fe1 ove1 receive shift register rxd1 txd1 mod bit asck1 reception control parity check selector selector selector intst1 intsr1 sot1 flag brg1 sir1 flag internal bus 1 16 1 16 remark the txd1, rxd1, and asck1 pins function alte rnately as the so1, si1, and sck1 pins.
chapter 10 serial interface function user?s manual u15195ej5v0ud 442 10.3.3 control registers because uart1 shares its pins with csi1, the uart 1 mode must be preset by using the pmc3 and rfc3 registers (refer to 10.1.1 selecting uart1 or csi1 mode ). (1) asynchronous serial interface mode register 10 (asim10) the asim10 register is an 8-bit register t hat controls the uart 1 transfer operation. this register can be read/written in 8-bit or 1-bit units. cautions 1. if any bits other than the rxe1 bit of the asim10 register are changed during uart1 transmission or reception, the uart 1 operation cannot be guaranteed. 2. set bits other than the rxe1 bit of the asim10 register when the uart1 operation is stopped (when rxe1 = 0 and tr ansmission is completed). change the port 3 mode control register (pmc3) after setting the comm unication mode in the bits other than the rxe1 bit of the asim10 register. 3. in the case of serial clock output in the clocked (synchr onous) mode, ensure that nodes do not output to one another causing conflict.
chapter 10 serial interface function user?s manual u15195ej5v0ud 443 7 1 asim10 <6> rxe1 5 ps1 4 ps0 3 cl 2 sl 1 0 0 scls address fffffa28h after reset 81h bit position bit name function 6 rxe1 enables/disables reception. 0: disables reception 1: enables reception specify parity bit length ps1 ps0 operation 0 0 no parity, extension bit operation 0 1 0 parity transmit side transmission with parity bit = 0 receive side no parity error generated during reception 1 0 odd parity 1 1 even parity 5, 4 ps1, ps0 3 cl specifies character length of transmit data (1 frame). 0: 7 bits 1: 8 bits 2 sl specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits specifies serial clock source. operation scls in asynchronous mode in synchronous mode 0 external clock input 1 internal baud rate generator 0 scls
chapter 10 serial interface function user?s manual u15195ej5v0ud 444 (2) asynchronous serial interface mode register 11 (asim11) the asim11 register is an 8-bit register that controls the ua rt1 transfer mode. this register can be read/written in 8-bit or 1-bit units 7 0 asim11 6 0 5 0 4 0 3 mod 2 umst 1 umsr 0 ebs address fffffa2ah after reset 00h bit position bit name function 3 mod specifies operation mode (asynchronous/synchronous mode) 0: asynchronous mode 1: synchronous mode 2 umst specifies number of conti nuous frame transmissions. 0: 1-frame data transmission 1: 2-frame continuous data transmission 1 umsr specifies number of cont inuous frame receptions. 0: 1-frame data reception 1: 2-frame continuous data reception 0 ebs specifies extension bit operation for tr ansmit/receive data when no parity is specified (ps0 = ps1 = 0). 0: disables extension bit addition 1: enables extension bit addition when the extension bit is specified, 1 dat a bit is added on top of the 8 bits of transmit/receive data, enabling 9-bit data communication. extension bit specification is valid only w hen no parity (asim10 register?s ps0 bit = ps1 bit = 0) and 1-frame data transmissi on (umst = 0) are specified. when 0 parity, odd parity, or even parity are sp ecified, or when 2-frame continuous data transmission (umst bit = 1) is specified, the ebs bit setting becomes invalid and extension bit addition is not performed. extension bit addition (ebs bit = 1) and 2-frame continuous data reception (umsr bit = 1) cannot be set simultaneously.
chapter 10 serial interface function user?s manual u15195ej5v0ud 445 (3) asynchronous serial interface status register 1 (asis1) the asis1 register is a register that is configured of a uart1 transmission status flag (sot1), reception status flag (sir1), a bit (rb8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (pe1, fe1, ove1) that indicate the error status at reception end. the status flag that indicates reception errors always indicates the most re cent error status. in other words, if the same error occurs several times before receive data is read, this flag holds only the status of the error that occurred last. each time the asis1 register is read after a recept ion completion interrupt (intsr1), read the reception buffer (rxb1 or rxbl1). the error flag is cleared wh en the reception buffer (rxb1 or rxbl1) is read. also, clear the error flag by reading the reception bu ffer (rxb1 or rxbl1) when a reception error occurs. this register is read-only, in 8-bit or 1-bit units.
chapter 10 serial interface function user?s manual u15195ej5v0ud 446 <7> sot1 asis1 <6> sir1 5 0 4 rb8 3 0 <2> pe1 <1> fe1 <0> ove1 address fffffa2ch after reset 00h bit position bit name function 7 sot1 status flag indicating transmission status. 0: transmission end timing (when intst1 is generated) 1: indicates transmission status note note the transmission status is the stat us until the specified number of stop bits has been transmitted following writ e operation to the transmit register. during 2-frame continuous transmission, this status is until the stop bit of the 2nd frame has been transmitted. 6 sir1 status flag indicating reception status. 0: reception end timing (when intsr1 is generated) 1: indicates reception status note note the reception status is the status until stop bit detection from the start bit detection timing. 4 rb8 indicates contents of receive data extensi on bit (1 bit) when 9-bit extended format is specified (ebs bit of asim11 register = 1) 2 pe1 status flag indicating parity error 0: processing to read data from reception buffer 1: when transmit parity and receive parity don?t match caution no parity error is generated if no parity is specified or 0 parity is specified by the ps1, ps0 bits of the asim10 register. 1 fe1 status flag indicating framing error 0: processing to read data from reception buffer 1: when stop bit is not detected 0 ove1 status flag indicating overrun error 0: processing to read data from reception buffer 1: when uart1 has completed next reception processing prior to loading receive data from reception buffer since the contents of the receive shift register are transferred to the reception buffer (rxb1, rxbl1) every time 1 frame is received, the next receive data is overwritten to the reception buffer (rxb1, rxbl1) and the previous receive data is discarded.
chapter 10 serial interface function user?s manual u15195ej5v0ud 447 (4) 2-frame continuous reception bu ffer register 1 (rxb1)/receive buffer register l1 (rxbl1) the rxb1 register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (umsr bit of asim11 register = 1), during 9-bit extend ed data reception (ebs bit of asim11 register = 1)). during 7 or 8 bit character reception, 0 is stored in the msb. for 16-bit access to this register, specify rxb1, and for access to the lower 8 bits, specify rxbl1. in the receive enabled status, receive data is transferred from the receive shift register to the reception buffer in synchronization with the end of shift-in processing for 1 frame of data. the reception completion interrupt request (intsr1) is generated upon transfer of data to the reception buffer (when 2-frame reception is specified, re ception buffer transmission of the second frame). in the reception disabled status, transfer processing to the reception buffer is not performed even if shift-in processing for 1 frame of data has been completed, and the contents of the rec eption buffer are held. neither is a reception completion interrupt request generated. the rxb1 register can be read in 16-bit units, and the rxbl1 register can be read in 8-bit units. 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxb1 [2-frame continuous reception buffer register 1] address fffffa20h after reset undefined 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 1 rxb1 0 rxb0 rxbl1 [receive buffer register l1] address fffffa22h after reset undefined bit position bit name function 15 to 0 rxb15 to rxb0 stores receive data. 0 can be read for the rxb1 register when 7 or 8 bit character data is received. when an extension bit is set during 9 bit ch aracter data reception, the extension bit (rxb8) is stored in rb8 of the asis1 register simultaneously with saving to the reception buffer. 0 can be read for the rxb7 bit of the rxbl1 register during 7 bit character data reception.
chapter 10 serial interface function user?s manual u15195ej5v0ud 448 (a) when 2-frame contin uous reception is set 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxb1 7-/8-bit data of 1st frame 7-/8-bit data of 2nd frame (b) when 9-bit extension reception is set 14 rxb14 13 rxb13 12 rxb12 2 rxb2 3 rxb3 4 rxb4 5 rxb5 6 rxb6 7 rxb7 8 rxb8 9 rxb9 10 rxb10 11 rxb11 15 rxb15 1 rxb1 0 rxb0 rxb1 9-bit extended data when 9-bit extension is set, the extension bit (rxb8) is stored in the rb8 bit of the asis1 register simultaneously with saving to the reception buffer.
chapter 10 serial interface function user?s manual u15195ej5v0ud 449 (c) cautions <1> operation upon occurrence of overrun error during 2-frame c ontinuous reception ? during normal operation reception completion interrupt (intsr1) generat ed at end of reception of 2nd frame, no error rxd1 frame 1 frame 2 ? reception of 3rd frame started be fore performing reception processing reception completion interrupt (intsr1) generat ed at end of reception of 2nd frame, no error rxd1 frame 1 frame 2 reception interrupt not generated at end of re ception of 3rd frame, occurrence of error rxd1 frame 3 frame 3 value of ove1 bit of asis1 register becomes 1. ? start of reception of 3rd frame and 4th fr ame before performing reception processing reception completion interrupt (intsr1) generat ed at end of reception of 2nd frame, no error rxd1 frame 1 frame 2 no reception completion interrupt generated at end of reception of 3rd frame, occurrence of error rxd1 frame 3 frame 3 value of ove1 bit of asis1 register becomes 1. reception completion interrupt (intsr1) generat ed at end of reception of 4th frame, no error rxd1 frame 3 frame 4 value of ove1 frame of asi s1 register remains 1. ? start of reception of 3rd frame before perfo rming reception processing, start of reception of 4th frame after reception processing reception completion interrupt (intsr1) generat ed at end of reception of 2nd frame, no error rxd1 frame 1 frame 2 reception completion interrupt not generated at end of reception of 3rd frame, occurrence of error rxd1 frame 3 frame 3 value of ove1 bit of asis1 register becomes 1. value of ove1 flag becomes 0 during reception processing. reception completion interrupt (intsr1) generat ed at end of reception of 4th frame, no error rxd1 frame 3 frame 4 no occurrence of error
chapter 10 serial interface function user?s manual u15195ej5v0ud 450 (5) 2-frame continuous transmission shift register 1 (txs1)/transmit shift register l1 (txsl1) the txs1 register is a 9-bit/2-fra me continuous transmission processing shift register. transmission is started by writing data to this register. a transmission completion interrupt request (intst1) is generat ed in synchronization with the end of transmission of 1 frame or 2 frames including the txs1 data. for 16-bit access to this register, specify txs1, and for access to the lower 8 bits, specify txsl1. the txs1 register is write-only in 16-bit units, and the txsl1 register is write-only in 8-bit units. caution txs1, txsl1 can be read, but since shifting is done in synch ronization with the shift clock, the data that is read cannot be guaranteed. 14 txs14 13 txs13 12 txs12 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 8 txs8 9 txs9 10 txs10 11 txs11 15 txs15 1 txs1 0 txs0 txs1 [2-frame continuous transmission shift register 1] address fffffa24h after reset undefined 2 txs2 3 txs3 4 txs4 5 txs5 6 txs6 7 txs7 1 txs1 0 txs0 txsl1 [transmit shift register l1] address fffffa26h after reset undefined bit position bit name function 15 to 0 txb15 to txb0 write transmit data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 451 10.3.4 interrupt requests the following two types of interrupt re quest are generated from uart1. ? reception completion interrupt (intsr1) ? transmission completion interrupt (intst1) the reception completion interrupt has higher default pr iority than the transmission completion interrupt. table 10-5. default priori ty of generated interrupts interrupt priority reception completion 1 transmission completion 2 (1) reception completion interrupt (intsr1) in the reception enabled state, t he reception completion interrupt (int sr1) is generated when data in the receive shift register undergoes shift-in proce ssing and is transferred to the reception buffer. the reception completion interrupt request (intsr1) is generated fo llowing stop-bit sampling and upon the occurrence of an error. in the reception disabled state, no rec eption completion interrupt is generated. caution a reception completion interrupt (intsr1) is generated when the last bit of receive data (stop bit) is sampled. (2) transmission completion interrupt (intst1) since uart1 does not have a transmit buffer, a trans mission completion interrupt request (intst1) is generated when one frame of dat a containing 7-bit or 8-bit characters or two frames of data containing 9-bit characters are shifted out from the tr ansmit shift register (txs1, txsl1).
chapter 10 serial interface function user?s manual u15195ej5v0ud 452 10.3.5 operation (1) data format full-duplex serial data is transmitted and received. figure 10-17 shows the format of transmit/receive data. one data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). when 2 data frame tr ansfer is set, both frames have the above-described format. specification of the character bit length in one data fr ame, parity selection, and s pecification of the stop bit length is done using asynchronous serial interface mode register 10 (asim10). sp ecification of the number of frames and specification of the extension bit is mode using asynchronous serial interface mode register 11 (asim11). data is transmitted lsb first. figure 10-17. asynchronous serial interface transmit/receive data format (a) 1-frame format 1 frame data stop bit start bit parity/ extension bit d0 d1 d2 d3 d4 d5 d6 d7 (b) 2-frame format higher frame lower frame data d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit parity bit stop bit start bit start bit ... 1 bit character bits ... 7 or 8 bits parity bit ... even parity, odd parity, 0 parity, or no parity stop bit ... 1 or 2 bits caution the extension bit is invalid in the 2-frame c ontinuous mode or when a parity bit is added.
chapter 10 serial interface function user?s manual u15195ej5v0ud 453 table 10-6. asim10, asim11 regist er settings and data format asim10, asim11 register settings data format cl bit ps1 bit ps0 bit sl bit ebs bit d0 to d6 d7 d8 d9 d10 0 0 0 data stop bit ? ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit ? ? 1 0 0 data data stop bit ? ? 1 other than ps1 = ps0 = 0 0 0 data data parity bit stop bit ? 0 0 0 data stop bit stop bit ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit stop bit ? 1 0 0 data data stop bit stop bit ? 1 other than ps1 = ps0 = 0 1 0 data data parity bit stop bit stop bit 0 0 0 data stop bit ? ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit ? ? 1 0 0 data data data stop bit ? 1 other than ps1 = ps0 = 0 0 1 data data parity bit stop bit ? 0 0 0 data stop bit stop bit ? ? 0 other than ps1 = ps0 = 0 data parity bit stop bit stop bit ? 1 0 0 data data data stop bit stop bit 1 other than ps1 = ps0 = 0 1 1 data data parity bit stop bit stop bit
chapter 10 serial interface function user?s manual u15195ej5v0ud 454 (2) transmission operation the transmission operation is started by writing data to 2-frame continuous transmission shift register 1 (txs1)/transmit shift register l1 (txsl1). following data write, the start bit is transmitted from the next shift timing. since the uart1 does not have a cts (transmission enable signal) input pin, use a port when the other party confirms the rec eption enabled status. (a) transmission operation start the transmission operation is started by writing transmit data to 2-frame continuous transmission shift register 1 (txs1)/transmit shift register l1 (txsl1). then data is output in sequence from lsb to the txd1 pin (transmission in sequence from the start bit). a start bit, parity bit, and stop bit(s) are automatically added. (b) transmission interrupt request when the transmit shift register becomes empty upon co mpletion of the transmission of 1 or 2 frames of data, a transmission completion interrupt request (i ntst1) is generated. the intst1 interrupt generation timing differs depending on the specification of the stop bit length. the intst1 interrupt is generated at the same time that the last stop bit is output. the transmission operation remains st opped until the data to be transmitt ed next has been written to the txs1/txsl1 registers. figure 10-18 shows the intst1 interrupt generation timing. cautions 1. normally, the transm ission completion interrupt (int st1) is generated when the transmit shift register becomes empty. ho wever, if the transmit shift register has become empty due to input of reset, no tran smission completion in terrupt (intst1) is generated. 2. no data can be written to the txs1 or txsl1 registers during a transmission operation until intst1 is generated. e ven if data is written, this does not affect the transmission operation.
chapter 10 serial interface function user?s manual u15195ej5v0ud 455 figure 10-18. asynchronous serial interf ace transmission comple tion interrupt timing (a) when stop bit length = 1 bit start parity stop d0 txd1 (output) intst1 interrupt flag in transmission (sot1) d1 d2 d6 d7 (b) when stop bit length = 2 bits start parity stop d0 txd1 (output) intst1 interrupt flag in transmission (sot1) d1 d2 d6 d7 (c) in 2-frame contin uous transmission mode start start stop parity stop d0 txd1 (output) intst1 interrupt flag in transmission (sot1) d1 1st frame 2nd frame d1 d5 d6 d7 parity
chapter 10 serial interface function user?s manual u15195ej5v0ud 456 (3) continuous transmission of 3 or more frames in addition to the 1-frame/2-frame transmission function, uart1 also enables continuous transmission of 3 or more frames, using the method shown below. (a) how to continuously transmit 3 or more fr ames (when the stop bit is 1 bit (sl bit = 0)) three frames can be continuously transmitted by writ ing transmit data to the t xs1/txsl1 register in the period between the generation of the transmission completion interrupt request (intst1) and 4 2/f xx before the output of the last stop bit. the intst1 interrupt becomes high level 2/f xx after being output and returns to low level 2/f xx later. txs1/txsl1 can only be written after the intst1 inte rrupt level has fallen. the time from intst1 interrupt generation to the completion of transmit dat a writing (t) is therefore indicated by the following expression. t = (time of one stop bit) ? (2 2/f xx + 4 2/f xx ) f xx = internal system clock caution 4 2/f xx has a margin of double the clock that can actually be used for operation. example count clock frequency = 32 mhz = 32,000,000 hz target baud rate in synchronous mode = 9,600 bps t = (1/9615.385) ? ( (4 + 8) /32,000,000) = 104.000 ? 0.375 = 103.625 [ s] therefore, be sure to write tr ansmit data to txs1/txsl1 within 103 s of the generation of the intst1 interrupt. note, however, that because writing to txs1/txsl1 ma y be delayed depending on the priority order of the interrupt or the interrupt servicing time, be sure to allow sufficient time for writing transmit data after the intst1 interrupt has been generated. if there is not enough time for continuous transmission due to a delay in writing to txs1/txsl1, a 1-bit high level is transmitted. note also that if the stop bit length is 2 bits (sl = 1), the intst1 interrupt will be generated when the second stop bit is output. figure 10-19. continuous transm ission of 3 or more frames 2/f xx 2/f xx 2/f xx 4 2/f xx txs1/txsl1 write period for 3-frame continuous transmission stop bit intst1 interrupt
chapter 10 serial interface function user?s manual u15195ej5v0ud 457 (4) reception operation the reception wait status is entered by setting the rxe1 bit of t he asim10 register to 1. to start the reception operation, first perform star t bit detection. start bit detection is done by performing sampling of the rxd1 pin. when the reception operatio n is started, serial data is stored in the receive shift register in order at the set baud rate. each time reception of 2 frames or 1 frame of rxb1 or rxbl1 data has been completed, a reception completion interrupt (intsr1) is generated. receive data is transmitted from the reception buffer (rxb1/rxbl1) to memory when this interrupt is serviced. (a) reception enabled status the reception operation is enabled by setting (1) the rxe1 bit of the asim10 register. ? rxe1 = 1: reception enabled status ? rxe1 = 0: reception disabled status in the reception disabled status, the reception hardware is in standby in an initialized state. at this time, no reception completion interrupt is generated, and the contents of the reception buffer are held. (b) start of reception operation the reception operation is started by detection of the start bit. ? in asynchronous mode (mod bit of asim11 register = 0) the rxd1 pin is sampled using the serial clock from the baud rate generator. after 8 serial clocks have been output following detection of the falling edge of the rxd1 pin, the rxd1 pin is again sampled. if a low level is detected at this time, the falling edge of the rxd1 pin is interpreted as a start bit, the operation shifts to reception processi ng, and the rxd1 pin input is sampled from this point on in units of 16 serial clock output. if the high level is detected during sampling after 8 serial clocks from detection of the falling edge of the rxd1 pin, this falling edge is not recognized as a start bit. the serial clock counter that generates the sample timing is initialized and stops, and i nput of the next falling edge is waited for. ? in synchronous mode (mod bit of asim11 register = 1) the rxd1 pin is sampled using the serial clock from the baud rate generator or at the rising edge of serial clock input/output. if the rxd1 pin is low level at this time, this is inte rpreted as a start bit and reception processing starts. if reception data is interrupted at the fixed low le vel during reception, recept ion of this receive data (including error detection) is completed and reception completion interrupt is generated. however, even if the rxd line is fixed at low leve l, the next reception operation is not started (start bit detection is not performed). be sure to set the high level when restarting the rec eption operation. if the high level is not set, the start bit detection position becomes undefined, and corre ct reception operation cannot be performed.
chapter 10 serial interface function user?s manual u15195ej5v0ud 458 (c) reception completion interrupt request when reception of one frame of data has been complete d (stop bit detection) when the rxe1 bit of the asim10 register = 1, the receive data in the shift re gister is transferred to rxb1/rxbl1 and a reception completion interrupt request (intsr1) is generated after 1 frame or 2 frames of data have been transferred to rxb1/rxbl1. a reception completion interrupt is also generated upon detection of an error. when the rxe1 bit = 0 (reception disabled), no reception completion interrupt is generated.
chapter 10 serial interface function user?s manual u15195ej5v0ud 459 figure 10-20. asynchronous serial interface reception completion interrupt timing (a) when stop bit length = 1 bit d0 d1 d2 d6 d7 8 serial clocks 8 serial clocks start stop rxd1 (input) intsr1 interrupt flag in reception (sir1) parity (b) when stop bit length = 2 bits d0 d1 d2 d6 d7 start parity stop rxd1 (input) intsr1 interrupt flag in reception (sir1) 8 serial clocks 8 serial clocks (c) in 2-frame contin uous transmission mode d0 d1 d1 d5 d6 d7 start start parity stop parity stop rxd1 (input) intsr1 interrupt flag in reception (sir1) 1st frame 2nd frame 8 serial clocks 8 serial clocks cautions 1. even if a reception error occurs, be sure to read 2-frame continuous reception buffer register 1 (rxb1)/receive buffer register 1 (rxb l1). if the rxb1 or rxbl1 register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely. 2. reception is always performed with a stop bit length of 1 bit. a second stop bit is ignored.
chapter 10 serial interface function user?s manual u15195ej5v0ud 460 (5) reception errors the flags for the three types of errors: parity errors , framing errors, and overrun errors, are affected in synchronization with reception operation. as a result of data reception, the pe1, fe1, and ove1 flags of the asis1 register are set (1) and a reception completion interrupt request (intsr1) is generated at the same time. the contents of error that occurr ed during reception can be detected by reading the contents of the pe1, fe1, and ove1 flags of the asis1 register during the intsr1 interrupt servicing. the contents of the asis1 r egister are reset (0) by reading the asis1 register (if the next receive data contains an error, the corresponding error flag is set (1)). table 10-7. reception error causes error flag reception error causes pe1 parity error the parity specific ation during transmission did not match the parity of the reception data fe1 framing error no stop bit was detected ove1 overrun error the reception of the next data was completed before data was read from the reception buffer (6) parity types and co rresponding operation a parity bit is used to detect a bit error in communication data. normally, the same type of parity bit is used at the transmission and reception sides. (a) even parity <1> during transmission the parity bit is controlled so that number of bits with the value ?1? within the transmit data including the parity bit is even. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 1 ? if the number of bits with the value ?1? within the transmit data is even: 0 <2> during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is odd.
chapter 10 serial interface function user?s manual u15195ej5v0ud 461 (b) odd parity <1> during transmission in contrast to even parity, the parity bit is controlled so that the number of bits with the value ?1? within the transmit data including the parity bit is odd. the parity bit value is as follows. ? if the number of bits with the value ?1? within the transmit data is odd: 0 ? if the number of bits with the value ?1? within the transmit data is even: 1 <2> during reception the number of bits with the value ?1? within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity during transmission, the parity bit is set to ?0? regardless of the transmit data. during reception, no parity bit check is performed. therefore, no parity error is generated regardless of whether the parity bit is ?0? or ?1?. (d) no parity no parity bit is added to the transmit data. during reception, the receive operation is performed as if there were no parity bit. since there is no parity bit, no parity error is generated.
chapter 10 serial interface function user?s manual u15195ej5v0ud 462 10.3.6 synchronous mode the synchronous mode can be se t with the asck1 pin, which is the serial clock i/o pin. the synchronous mode is set with the mod bit of the asim11 register, and the serial clock to be used for synchronization is selected with the scls bit of the asim10 register. in the synchronous mode, external clock input is selected when the value of the scls bit is 0 (default), and the serial clock output is selected in the case of all other se ttings. therefore, when performing settings, make sure that outputs between connection nodes do not conflict. in the synchronous mode, the falling edge of the serial clock is used as the transmission timing, and the rising edge as the reception timing, but tr ansmit data is output with a delay of 1 system cl ock (serial clock) (in the external clock synchronous mode, the maximum delay is 2.5 system clocks). figure 10-21. transmission/recep tion timing in sy nchronous mode d0 d1 d2 d3 d4 d5 d6 d7 parity start stop d0 d1 d2 d3 d4 d5 d6 d7 parity start stop asck1 output data (txd1) input data (rxd1) on the data output side, the data changes at the falling edge of the serial clock output. on the data input side, the data is latched at the rising edge of the serial clock output. serial clock output continues as long as the setting is not canceled.
chapter 10 serial interface function user?s manual u15195ej5v0ud 463 figure 10-22. transmission/reception ti ming chart for sync hronous mode (1/3) (a) in 1-frame transm ission/reception mode serial clock transmission register write signal flag in transmission (sot1) transmission completion interrupt (intst1) reception completion interrupt (intsr1) reception buffer (rxb1) reception buffer (rxbl1) flag in reception (sir1) transmit data stop bit undefined (hold previous value) undefined (hold previous value) 005ah 5ah
chapter 10 serial interface function user?s manual u15195ej5v0ud 464 figure 10-22. transmission/reception ti ming chart for sync hronous mode (2/3) (b) in 2-frame continuous transmission/reception mode serial clock transmission register write signal flag in transmission (sot1) transmission completion interrupt (intst1) reception completion interrupt (intsr1) reception buffer (rxbl1) reception buffer (rxbl1) flag in reception (sir1) transmit data stop bit stop bit undefined (hold previous value) undefined (hold previous value) 5a5ah 5ah 5a15h 15h
chapter 10 serial interface function user?s manual u15195ej5v0ud 465 figure 10-22. transmission/reception ti ming chart for sync hronous mode (3/3) (c) transmission/reception timing and transmit data ti ming during serial clock output note serial clock (output) system clock transmit data transmission timing reception timing note the transmit data is delayed by 1 system clock in relation to the serial clock. (d) transmission/reception timi ng and transmit data timing using external serial clock note external serial clock system clock transmit data transmission timing reception timing note since, during external serial cl ock synchronization, synchronization is done with the internal system clock when feeding the external serial clock to the in ternal circuit, a delay ranging from 1 system clock to a maximum of 2.5 system clocks results.
chapter 10 serial interface function user?s manual u15195ej5v0ud 466 figure 10-23. reception completion interrupt a nd error interrupt generation timing during synchronous mode reception (a) during normal operation (in 1-frame reception mode) start receive data flag in reception (sir1) reception completion interrupt (intsr1) error interrupt stop (b) in 2-frame cont inuous reception mode start start receive data flag in reception (sir1) reception completion interrupt (intsr1) error interrupt stop stop (1) (2) (3) (1) if the start bit of the second frame is not detect ed, no reception completion interrupt is generated. (2) if an error occurs in the first frame, an error interrupt is generated following detection of the stop bit of the first frame (at the calculated position). (3) if an error occurs in the second frame, an error interrupt is generated simultaneously with a reception completion interrupt. if an error occurs in the first frame, no error inte rrupt is generated even if an error occurs in the second frame.
chapter 10 serial interface function user?s manual u15195ej5v0ud 467 10.3.7 dedicated baud rate generator 1 (brg1) (1) configuration of baud ra te generator 1 (brg1) for uart1, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (f xx ) for each channel. the serial clock source is specified by register asim10. if dedicated baud rate generator output is specifi ed, brg1 is selected as the clock source. since the same serial clock can be shared for transmission and reception for one channel, baud rate is the same for the transmission/reception. figure 10-24. block diagram of baud rate generator 1 (brg1) bgcs1, bgcs0 prscm1 match detector 1/2 uart1 8-bit timer counter f xx /2 f xx /4 f xx /8 f xx /16 selector remark f xx : internal system clock
chapter 10 serial interface function user?s manual u15195ej5v0ud 468 (2) dedicated baud rate generator 1 (brg1) brg1 is configured of an 8-bit timer counter for baud ra te signal generation, a prescaler mode register that controls the generation of the baud rate signal (prsm1), a prescaler compare register that sets the value of the 8-bit timer counter (prscm1), and a prescaler. (a) input clock the internal system clock (f xx ) is input to brg1. (b) prescaler mode register 1 (prsm1) the prsm1 register controls generatio n of the uart1 baud rate signal. these registers can be read/written in 8-bit or 1-bit units. cautions 1. do not change the values of th e bgcs1 and bgcs0 bits during transmission/ reception operations. 2. set prsm1 bits other than the uartce1 bit prior to setting th e uartce1 bit to 1. <7> uartce1 prsm1 6 0 5 0 4 0 3 0 2 0 1 bgcs1 0 bgcs0 address fffffa2eh after reset 00h bit position bit name function 7 uartce1 enables baud rate counter operation. 0: stops baud rate counter operation and fixes baud rate output signal to 0. 1: enables baud rate counter operation and starts baud rate output. selects count clock to baud rate counter. bgcs1 bgcs0 count clock selection 0 0 f xx /2 0 1 f xx /4 1 0 f xx /8 1 1 f xx /16 1, 0 bgcs1, bgcs0 remark f xx : internal system clock
chapter 10 serial interface function user?s manual u15195ej5v0ud 469 (c) prescaler compare register 1 (prscm1) prscm1 is an 8-bit compare register that sets the value of the 8-bit timer counter. this register can be read/written in 8-bit units. cautions 1. the internal timer c ounter is cleared by writing to the prscm1 regist er. therefore, do not overwrite the prscm1 register during a transmission operation. 2. perform prscm1 register settings prior to setting the uartce1 bit to 1. if the contents of the prscm1 register are ov erwritten when the value of the uartce1 bit is 1, the cycle of the baud rate signal is not guaranteed. 3. set the baud rate in the asynchronous mode to 153600 bps or lower. set the baud rate in the synchronous mode to 1000000 bps or lower. 7 prscm7 prscm1 6 prscm6 5 prscm5 4 prscm4 3 prscm3 2 prscm2 1 prscm1 0 prscm0 address fffffa30h after reset 00h (d) baud rate generation first, when the uartce1 bit of the pr sm1 register is overwritten by 1, the 8-bit timer counter for baud rate signal generation starts counting up with th e clock selected by bits bgcs1 and bgcs0 of the prsm1 register. the count value of the 8-bit time r counter is compared with the value of the prscm1 register, and if these values match, a timer count clock pulse of 1 cycle is output to the output controller for the baud rate. the output controller for the baud rate reverses the b aud rate signal in synchronization with the rising edge of the timer count clock when this pulse is ?1?. (e) cycle of baud rate signal the cycle of the baud rate signal is calculated as follows. ? when setting value of prscm1 register is 00h (cycle of signal selected by bits bgcs1, bgcs0 of prsm1 register) 256 2 ? in cases other than above (cycle of signal selected by bits bgcs1, bgcs0 of prsm1 register) (setting value of prscm1 register) 2
chapter 10 serial interface function user?s manual u15195ej5v0ud 470 (f) baud rate setting value the formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> formula for calculating baud rate in asynchronous mode baud rate = [bps] f xx = internal system clock frequency [hz] = cpu clock/2 [hz] m: setting value of prscm1 register (1 m 256 note ) k: value set by bits bgcs1, bgcs0 of prsm1 register (k = 0, 1, 2, 3) note the setting of m = 256 is performed by writing 00h to the prscm1 register. <2> formula for calculating the ba ud rate in synchronous mode baud rate = [bps] f xx = internal system clock frequency [hz] = cpu clock/2 [hz] m: setting value of prscm1 register (1 m 256 note ) k: value set by bits bgcs1, bgcs0 of prsm1 register (k = 0, 1, 2, 3) note the setting of m = 256 is performed by writing 00h to the prscm1 register. <3> formula for calculating error error [%] = 100 example (9,520 ? 9,600)/9,600 100 = ? 0.833 [%] remark actual baud rate: baud rate with error target baud rate: normal baud rate f xx 2 m 2 k 16 f xx 2 m 2 k actual baud rate ? target baud rate desired baud rate
chapter 10 serial interface function user?s manual u15195ej5v0ud 471 <4> baud rate setting example in an actual system, the output of a prescaler module , etc. is connected to t he input clock. table 10- 8 shows the baud rate generator setting data at this time. table 10-8. baud rate gene rator setting data (brg = f xx /2) (a) when f xx = 32 mhz target baud rate actual baud rate synchronous mode asynchronous mode synchronous mode asynchronous mode bgcsm bit (m = 0, 1) prscm1 register setting value error 4,800 300 4,807.692 300.4808 3 208 0.16 9,600 600 9,615.385 600.9615 3 104 0.16 19,200 1,200 19,230.77 1,201.923 3 52 0.16 38,400 2,400 38,461.54 2,403.846 3 26 0.16 76,800 4,800 76,923.08 4,807.692 3 13 0.16 153,600 9,600 153,846.2 9,615.385 2 13 0.16 166,400 10,400 166,666.7 10,416.67 1 24 0.16 307,200 19,200 307,692.3 19,230.77 1 13 0.16 614,400 38,400 615,384.6 38,461.54 0 13 0.16 not possible 76,800 ? 71,428.57 0 7 ? 6.99 not possible 153,600 ? 166,666.7 0 3 8.51 (b) when f xx = 40 mhz target baud rate actual baud rate synchronous mode asynchronous mode synchronous mode asynchronous mode bgcsm bit (m = 0, 1) prscm1 register setting value error 4,800 300 4,882.813 305.1758 3 256 1.73 9,600 600 9,615.385 600.9615 3 130 0.16 19,200 1,200 19,230.77 1,201.923 3 65 0.16 38,400 2,400 38,461.54 2,403.846 2 65 0.16 76,800 4,800 76,923.08 4,807.692 1 65 0.16 153,600 9,600 153,846.2 9,615.385 0 65 0.16 166,400 10,400 166,666.7 10,416.67 0 60 0.16 307,200 19,200 303,030.3 18,939.39 0 33 ? 1.36 614,400 38,400 625,000 39,062.5 0 16 1.73 not possible 76,800 ? 78,125 0 8 1.73 not possible 153,600 ? 156,250 0 4 1.73
chapter 10 serial interface function user?s manual u15195ej5v0ud 472 (3) allowable baud rate range during reception the degree to which a discrepancy from the transmission destination?s baud rate is allowed during reception is shown below. caution the equations described be low should be used to set the baud rate error during reception so that it always is withi n the allowable error range. figure 10-25. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uart1 transfer rate latch timing start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 10-25, after the start bit is detect ed, the receive data latch timing is determined according to the counter that was set by the prscm1 register. if all data up to the final data (sto p bit) is in time for this latch timing, the data can be received normally. if this is applied to 11-bit reception, the following is theoretically true. fl = (brate) ?1 brate: uart1 baud rate k: prscm1 register setting value fl: 1-bit data length when the latch timing margin is 2 clocks of f xx /2, the minimum allowable transfer rate (flmin) is as follows (f xx : internal system clock). fl k 2 2 k 21 fl k 2 2 k fl 11 min fl + = ? ? =
chapter 10 serial interface function user?s manual u15195ej5v0ud 473 therefore, the transfer destination?s maximum re ceivable baud rate (brmax) is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum allowable transfer rate (flmax) can be obtained as follows. fl k 2 2 k 21 fl k 2 2 k fl 11 max fl 11 10 ? = + ? = 11 fl k 20 2 k 21 max fl ? = therefore, the transfer destination?s minimum receivable baud rate (brmin) is as follows. brmin = (flmax/11) ? 1 = brate (4) transfer rate in 2 -frame continuous reception in 2-frame continuous reception, the ti ming is initialized by detecting the st art bit of the second frame, so the transfer results are not affected. 22k 21k + 2 20k 21k ? 2
chapter 10 serial interface function user?s manual u15195ej5v0ud 474 10.4 clocked serial inte rfaces 0, 1 (csi0, csi1) 10.4.1 features ? high-speed transfer: maximum 5 mbps ? half-duplex communications ? master mode or slave mode can be selected ? transmission data length: 8 bits or 16 bits can be set ? transfer data direction can be swit ched between msb first and lsb first ? eight clock signals can be selected (7 master clocks and 1 slave clock) ? 3-wire type son: serial transmit data output sin: serial receive data input sckn: serial clock i/o ? interrupt sources: 1 type ? transmission/reception completion interrupt (intcsin) ? transmission/reception mode and rece ption-only mode can be specified ? two transmit buffers (sotbfn/sotbfln, sotbn/so tbln) and two receive buffers (sirbn/sirbln, sirben/sirbeln) are provided on chip ? single transfer mode and repeat transfer mode can be specified remark n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 475 10.4.2 configuration csin is controlled via the clocked serial interface mode regi ster (csimn) (n = 0, 1). transmission/reception of data is performed by reading/writing the sion register (n = 0, 1). (1) clocked serial interface mode re gisters 0, 1 (csim0, csim1) the csimn register is an 8-bit register that specifies the operation of csin. (2) clocked serial interface clock selecti on registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register that controls the csin serial transfer operation. (3) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is a 16-bit shift register that converts parallel data into serial data. the sion register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by accessing the buffer register. (4) serial i/o shift registers l0, l1 (siol0, siol1) the sioln register is an 8-bit shift register th at converts parallel data into serial data. the sioln register is used for bot h transmission and reception. data is shifted in (reception) and shifted ou t (transmission) from the msb or lsb side. the actual transmission/reception operations ar e started up by access of the buffer register . (5) clocked serial interface receive bu ffer registers 0, 1 (sirb0, sirb1) the sirbn register is a 16-bit buffer r egister that stores receive data. (6) clocked serial interface receive buffer registers l0 , l1 (sirbl0, sirbl1) the sirbln register is an 8-bit buffer r egister that stores receive data. (7) clocked serial interface read-only receive buffer registers 0, 1 (sirbe0, sirbe1) the sirben register is a 16-bit buffer register that stores receive data. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. (8) clocked serial interface read-only receive buffer registers l0, l1 (sirbel0, sirbel1) the sirbeln register is an 8-bit buffer register that stores receive data. the sirbeln register is the same as the sirbln register. it is used to read the contents of the sirbln register. (9) clocked serial interface transmit bu ffer registers 0, 1 (sotb0, sotb1) the sotbn register is a 16-bit buffer r egister that stores transmit data. (10) clocked serial interface transmit buffe r registers l0, l1 (sotbl0, sotbl1) the sotbln register is an 8-bit buffer register that stores transmit data. (11) clocked serial interface initial transmit buffer regi sters (sotbf0, sotbf1) the sotbfn register is a 16-bit buffer register that stores the initial trans mit data in the repeat transfer mode.
chapter 10 serial interface function user?s manual u15195ej5v0ud 476 (12) clocked serial interface initial transmit buffer regi ster l (sotbfl0, sotbfl1) the sotbfln register is an 8-bit buffer register that st ores initial transmit data in the repeat transfer mode. (13) selector the selector selects the serial clock to be used. (14) serial clock controller controls the serial clock supply to the shift register. also controls the clock output to the sckn pin when the internal clock is used. (15) serial clock counter counts the serial clock output or input during transmi ssion/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) interrupt controller controls the interrupt request timing.
chapter 10 serial interface function user?s manual u15195ej5v0ud 477 figure 10-26. block diagram of clocked serial interface selector transmission control so selection so latch transmit buffer register (sotbn/sotbln) receive buffer register (sirbn/sirbln) shift register (sion/sioln) initial transmit buffer register (sotbfn/sotbfln) interrupt controller clock start/stop control & clock phase control serial clock controller sckn intcsin son sin control signal transmission data control f xx /2 7 f xx /2 6 f xx /2 5 f xx /2 4 f xx /2 3 f xx /2 2 brg3 sckn remarks 1. n = 0, 1 2. f xx : internal system clock 3. the so1, si1, and sck1 pins function altern ately as the txd1, rxd1, and asck1 pins.
chapter 10 serial interface function user?s manual u15195ej5v0ud 478 10.4.3 control registers because csi1 shares its pins with uart1, the csi1 mode must be preset by using the pmc3 and rfc3 registers (refer to 10.1.1 selecting mode of uart1 or csi1 ). (1) clocked serial interface mode re gisters 0, 1 (csim0, csim1) the csimn register controls the csin operation (n = 0, 1). these registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). caution overwriting the trmdn, ccl, dirn, csit, and auto bits of the csimn register can be done only when the csotn bit = 0. if these bits are overwritten at any other time, the operation cannot be guaranteed.
chapter 10 serial interface function user?s manual u15195ej5v0ud 479 <7> csicae0 csim0 <6> trmd0 5 ccl <4> dir0 3 csit 2 auto 1 0 <0> csot0 <7> csicae1 <6> trmd1 5 ccl <4> dir1 3 csit 2 auto 1 0 <0> csot1 address fffff900h after reset 00h csim1 address fffff910h after reset 00h bit position bit name function 7 csicaen enables/disables csin operation. 0: enables csin operation. 1: disables csin operation. the internal csin circuit can be reset asynchronously by setting the csicaen bit to 0. for the sckn and son pin output status when the csicaen bit = 0, refer to 10.4.5 output pins . 6 trmdn specifies transmission/reception mode. 0: receive-only mode 1: transmission/reception mode when the trmdn bit = 0, receive-only transfer is performed and the son pin output is fixed to low level. data reception is started by reading the sirbn register. when the trmdn bit = 1, transmission/recept ion is started by writing data to the sotbn register. 5 ccl specifies data length. 0: 8 bits 1: 16 bits 4 dirn specifies transfer direction mode (msb/lsb). 0: first bit of transfer data is msb 1: first bit of transfer data is lsb 3 csit controls delay of interrupt request signal. 0: no delay 1: delay mode (interrupt request signal is delayed 1/2 cycle). the delay mode (csit bit = 1) is valid only in the master mode (cks2 to csk0 bits of the csicn register are not 11b). in the slave mode (cks2 to cks0 bits are 11b), do not set the delay mode. caution the delay mode (csit bit = 1) is valid only in the master mode (cks2 to csk0 bits of the csicn register are not 111b). in the slave mode (cks2 to cks0 bits are 111b), do not set the delay mode. 2 auto specifies single transfer mode or repeat transfer mode. 0: single transfer mode 1: repeat transfer mode 0 csotn flag indicating transfer status. 0: idle status 1: transfer execution status caution the csotn bit is cleared (0 ) by writing 0 to the csicaen bit. remark n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 480 (2) clocked serial interface clock selecti on registers 0, 1 (csic0, csic1) the csicn register is an 8-bit register that co ntrols the csin transfer operation (n = 0, 1). these registers can be read/written in 8-bit or 1-bit units. caution the csicn register can be overwritten only when the csicaen bi t of the csimn register = 0.
chapter 10 serial interface function user?s manual u15195ej5v0ud 481 7 0 csic0 6 0 5 0 4 ckp 3 dap 2 cks2 1 cks1 0 cks0 7 0 6 0 5 0 4 ckp 3 dap 2 cks2 1 cks1 0 cks0 address fffff901h after reset 00h csic1 address fffff911h after reset 00h bit position bit name function specifies operation mode. ckp dap operation mode 0 0 do7 do6 do5 do4 do3 do2 do1 do0 di7 son (output) sckn (i/o) sin (input) di6 di5 di4 di3 di2 di1 di0 0 1 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) 1 0 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) 1 1 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 son (output) sckn (i/o) sin (input) 4, 3 ckp, dap remark n = 0, 1 specifies serial clock. cks2 cks1 cks0 serial clock mode 0 0 0 f xx /2 7 master mode 0 0 1 f xx /2 6 master mode 0 1 0 f xx /2 5 master mode 0 1 1 f xx /2 4 master mode 1 0 0 f xx /2 3 master mode 1 0 1 f xx /2 2 master mode 1 1 0 clock generated by brg3 master mode 1 1 1 external clock (sckn) slave mode 2 to 0 cks2 to cks0 remark f xx : internal system clock frequency n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 482 (3) clocked serial interface receive bu ffer registers 0, 1 (sirb0, sirb1) the sirbn register is a 16-bit buffer register that stores receive data (n = 0, 1). when the receive-only mode is set (trmdn bit of csimn register = 0), the recepti on operation is started by reading data from the sirbn register. these registers are read-only, in 16-bit units. in addition to reset input, these registers can also be init ialized by clearing (0) the csicaen bit of the csimn register. cautions 1. read the sirbn register only when the 16-bit data length has been set (ccl bit of csimn register = 1). 2. when the single transfer mode has been set (auto bit of csimn register = 0), perform a read operation only in the idle state (csotn bit of csimn re gister = 0). if the sirbn register is read during data transfer, the data cannot be guaranteed. 14 sirb 14 13 sirb 13 12 sirb 12 2 sirb 2 3 sirb 3 4 sirb 4 5 sirb 5 6 sirb 6 7 sirb 7 8 sirb 8 9 sirb 9 10 sirb 10 11 sirb 11 15 sirb 15 1 sirb 1 0 sirb 0 sirb0 address fffff902h after reset 0000h 14 sirb 14 13 sirb 13 12 sirb 12 2 sirb 2 3 sirb 3 4 sirb 4 5 sirb 5 6 sirb 6 7 sirb 7 8 sirb 8 9 sirb 9 10 sirb 10 11 sirb 11 15 sirb 15 1 sirb 1 0 sirb 0 sirb1 address fffff912h after reset 0000h bit position bit name function 15 to 0 sirb15 to sirb0 stores receive data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 483 (4) clocked serial interface receive buffer registers l0 , l1 (sirbl0, sirbl1) the sirbln register is an 8-bit buffer register that stores receive data (n = 0, 1). when the receive-only mode is set (trmdn bit of csimn register = 0), the recepti on operation is started by reading data from the sirbln register. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, these registers can also be init ialized by clearing (0) the csicaen bit of the csimn register. the sirbln register is the same as t he lower bytes of the sirbn register. cautions 1. read the sirbln regi ster only when the 8-bit data le ngth has been set (ccl bit of csimn register = 0). 2. when the single tr ansfer mode is set (auto bit of cs imn register = 0), perform a read operation only in the idle state (csotn bit of cs imn register = 0). if the sirbln register is read during data transfer, th e data cannot be guaranteed. 7 sirb7 sirbl0 6 sirb6 5 sirb5 4 sirb4 3 sirb3 2 sirb2 1 sirb1 0 sirb0 address fffff902h after reset 00h 7 sirb7 sirbl1 6 sirb6 5 sirb5 4 sirb4 3 sirb3 2 sirb2 1 sirb1 0 sirb0 address fffff912h after reset 00h bit position bit name function 7 to 0 sirb7 to sirb0 stores receive data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 484 (5) clocked serial interface read-only receive buffer registers 0, 1 (sirbe0, sirbe1) the sirben register is a 16-bit buffer register that stores receive data (n = 0, 1). these registers are read-only, in 16-bit units. in addition to reset input, this register can also be in itialized by clearing (0) the csicaen bit of the csimn register. the sirben register is the same as the sirbn register. it is used to read the contents of the sirbn register. cautions 1. the receive operation is not started ev en if data is read fr om the sirben register. 2. the sirben register can be read only if th e 16-bit data length is set (ccl bit of csimn register = 1). 14 sirbe 14 13 sirbe 13 12 sirbe 12 2 sirbe 2 3 sirbe 3 4 sirbe 4 5 sirbe 5 6 sirbe 6 7 sirbe 7 8 sirbe 8 9 sirbe 9 10 sirbe 10 11 sirbe 11 15 sirbe 15 1 sirbe 1 0 sirbe 0 14 sirbe 14 13 sirbe 13 12 sirbe 12 2 sirbe 2 3 sirbe 3 4 sirbe 4 5 sirbe 5 6 sirbe 6 7 sirbe 7 8 sirbe 8 9 sirbe 9 10 sirbe 10 11 sirbe 11 15 sirbe 15 1 sirbe 1 0 sirbe 0 sirbe0 address fffff906h after reset 0000h sirbe1 address fffff916h after reset 0000h bit position bit name function 15 to 0 sirbe15 to sirbe0 stores receive data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 485 (6) clocked serial interface read-only receive buffer registers l0, l1 (sirbel0, sirbel1) the sirbeln register is an 8-bit buffer regist er that stores receive data (n = 0, 1). these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be in itialized by clearing (0) the csicaen bit of the csimn register. the sirbeln register is the same as the sirbln register. it is used to read the contents of the sirbln register. cautions 1. the receive operation is not started ev en if data is read fr om the sirbeln register. 2. the sirbeln register can be read only if th e 8-bit data length has been set (ccl bit of csimn register = 0). 7 sirbe7 sirbel0 6 sirbe6 5 sirbe5 4 sirbe4 3 sirbe3 2 sirbe2 1 sirbe1 0 sirbe0 address fffff906h after reset 00h 7 sirbe7 sirbel1 6 sirbe6 5 sirbe5 4 sirbe4 3 sirbe3 2 sirbe2 1 sirbe1 0 sirbe0 address fffff916h after reset 00h bit position bit name function 7 to 0 sirbe7 to sirbe0 stores receive data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 486 (7) clocked serial interface transmit bu ffer registers 0, 1 (sotb0, sotb1) the sotbn register is a 16-bit buffer register that stores transmit data (n = 0, 1). when the transmission/reception mode is set (trmdn bit of csimn register = 1), the transmission operation is started by writing data to the sotbn register. this register can be read/written in 16-bit units. cautions 1. access the sotbn regi ster only when the 16-bit data length is set (ccl bit of csimn register = 1). 2. when the single tr ansfer mode is set (auto bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn re gister = 0). if the sotbn register is accessed during data transfer, th e data cannot be guaranteed. 14 sotb 14 13 sotb 13 12 sotb 12 2 sotb 2 3 sotb 3 4 sotb 4 5 sotb 5 6 sotb 6 7 sotb 7 8 sotb 8 9 sotb 9 10 sotb 10 11 sotb 11 15 sotb 15 1 sotb 1 0 sotb 0 sotb0 address fffff904h after reset 0000h 14 sotb 14 13 sotb 13 12 sotb 12 2 sotb 2 3 sotb 3 4 sotb 4 5 sotb 5 6 sotb 6 7 sotb 7 8 sotb 8 9 sotb 9 10 sotb 10 11 sotb 11 15 sotb 15 1 sotb 1 0 sotb 0 sotb1 address fffff914h after reset 0000h bit position bit name function 15 to 0 sotb15 to sotb0 stores transmit data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 487 (8) clocked serial interface transmit buffe r registers l0, l1 (sotbl0, sotbl1) the sotbln register is an 8-bit buffer regist er that stores transmit data (n = 0, 1). when the transmission/reception mode is set (trmdn bit of csimn register = 1), the transmission operation is started by writing data to the sotbln register. these registers can be read/written in 8-bit or 1-bit units. the sotbln register is the same as t he lower bytes of the sotbn register. cautions 1. access the sotbln register only when the 8-bit data length has been set (ccl bit of csimn register = 0). 2. when the single tr ansfer mode is set (auto bit of csimn register = 0), perform access only in the idle state (csotn bit of csimn re gister = 0). if the sotbln register is accessed during data transfer, the data cannot be guaranteed. 7 sotb7 sotbl0 6 sotb6 5 sotb5 4 sotb4 3 sotb3 2 sotb2 1 sotb1 0 sotb0 address fffff904h after reset 00h 7 sotb7 sotbl1 6 sotb6 5 sotb5 4 sotb4 3 sotb3 2 sotb2 1 sotb1 0 sotb0 address fffff914h after reset 00h bit position bit name function 7 to 0 sotb7 to sotb0 stores transmit data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 488 (9) clocked serial interface initial transmit buffer registers 0, 1 (sotbf0, sotbf1) the sotbfn register is a 16-bit buffer register that stores initial transmis sion data in the repeat transfer mode (n = 0, 1). the transmission operation is not started even if data is writt en to the sotbfn register. these registers can be read/written in 16-bit units. caution access the sotbfn register only when the 16-bit data length has been set (ccl bit of csimn register = 1), and only in the idle stat e (csotn bit of csimn register = 0). if the sotbfn register is accessed during data transfer, the da ta cannot be guaranteed. 14 sotbf 14 13 sotbf 13 12 sotbf 12 2 sotbf 2 3 sotbf 3 4 sotbf 4 5 sotbf 5 6 sotbf 6 7 sotbf 7 8 sotbf 8 9 sotbf 9 10 sotbf 10 11 sotbf 11 15 sotbf 15 1 sotbf 1 0 sotbf 0 14 sotbf 14 13 sotbf 13 12 sotbf 12 2 sotbf 2 3 sotbf 3 4 sotbf 4 5 sotbf 5 6 sotbf 6 7 sotbf 7 8 sotbf 8 9 sotbf 9 10 sotbf 10 11 sotbf 11 15 sotbf 15 1 sotbf 1 0 sotbf 0 sotbf0 address fffff908h after reset 0000h sotbf1 address fffff918h after reset 0000h bit position bit name function 15 to 0 sotbf15 to sotbf0 stores initial transmission data in repeat transfer mode.
chapter 10 serial interface function user?s manual u15195ej5v0ud 489 (10) clocked serial interface in itial transmit buffer registers l0, l1 (sotbfl0 , sotbfl1) the sotbfln register is an 8-bit buffer register that stores initial transm ission data in the repeat transfer mode (n = 0, 1). the transmission operation is not started even if data is written to the sotbfln register. these registers can be read/written in 8-bit or 1-bit units. the sotbfln register is the same as t he lower bytes of the sotbfn register. caution access the sotbfln register only when th e 8-bit data length has been set (ccl bit of csimn register = 0), and only in the idle stat e (csotn bit of csimn register = 0). if the sotbfln register is accessed during data transfer, the data cannot be guaranteed. 7 sotbf7 sotbfl0 6 sotbf6 5 sotbf5 4 sotbf4 3 sotbf3 2 sotbf2 1 sotbf1 0 sotbf0 address fffff908h after reset 00h 7 sotbf7 sotbfl1 6 sotbf6 5 sotbf5 4 sotbf4 3 sotbf3 2 sotbf2 1 sotbf1 0 sotbf0 address fffff918h after reset 00h bit position bit name function 7 to 0 sotbf7 to sotbf0 stores initial transmission data in repeat transfer mode.
chapter 10 serial interface function user?s manual u15195ej5v0ud 490 (11) serial i/o shift registers 0, 1 (sio0, sio1) the sion register is a 16-bit shift register that c onverts parallel data into serial data (n = 0, 1). the transfer operation is not started even if the sion register is read. these registers are read-only, in 16-bit units. in addition to reset input, this register can also be in itialized by clearing (0) the csicaen bit of the csimn register. caution access the sion register only when the 16-bit data le ngth has been set (ccl bit of csimn register = 1), and only in the idle stat e (csotn bit of csimn register = 0). if the sion register is accessed during data tr ansfer, the data cannot be guaranteed. 14 sio14 13 sio13 12 sio12 2 sio2 3 sio3 4 sio4 5 sio5 6 sio6 7 sio7 8 sio8 9 sio9 10 sio10 11 sio11 15 sio15 1 sio1 0 sio0 sio0 address fffff90ah after reset 0000h 14 sio14 13 sio13 12 sio12 2 sio2 3 sio3 4 sio4 5 sio5 6 sio6 7 sio7 8 sio8 9 sio9 10 sio10 11 sio11 15 sio15 1 sio1 0 sio0 sio1 address fffff91ah after reset 0000h bit position bit name function 15 to 0 sio15 to sio0 data is shifted in (reception) or shift ed out (transmission) from the msb or lsb side.
chapter 10 serial interface function user?s manual u15195ej5v0ud 491 (12) serial i/o shift registers l0, l1 (siol0, siol1) the sioln register is an 8-bit shift register that c onverts parallel data into serial data (n = 0, 1). the transfer operation is not started even if the s ioln register is read. these registers are read-only, in 8-bit or 1-bit units. in addition to reset input, this register can also be in itialized by clearing (0) the csicaen bit of the csimn register. the sioln register is the same as t he lower bytes of the sion register. caution access the sioln register only when the 8-bit data length has been set (ccl bit of csimn register = 0), and only in the idle stat e (csotn bit of csimn register = 0). if the sioln register is accessed during data tr ansfer, the data cannot be guaranteed. 7 sio7 siol0 6 sio6 5 sio5 4 sio4 3 sio3 2 sio2 1 sio1 0 sio0 7 sio7 6 sio6 5 sio5 4 sio4 3 sio3 2 sio2 1 sio1 0 sio0 address fffff90ah after reset 00h siol1 address fffff91ah after reset 00h bit position bit name function 7 to 0 sio7 to sio0 data is shifted in (reception) or shift ed out (transmission) from the msb or lsb side.
chapter 10 serial interface function user?s manual u15195ej5v0ud 492 10.4.4 operation (1) single transfer mode (a) usage in the receive-only mode (trmdn bit of csimn register = 0), transfer is started by reading note 1 the receive data buffer register (sirbn/sirbln) (n = 0, 1). in the transmission/reception mode (t rmdn bit of csimn register = 1), transfer is started by writing note 2 to the transmit data buffer register (sotbn/sotbln). in the slave mode, the operation must be enabled bef orehand (csicaen bit of csimn register = 1). when transfer is started, the valu e of the csotn bit of the csimn register becomes 1 (transmission execution status). upon transfer completion, the transmission/reception co mpletion interrupt (intcsin) is set (1), and the csotn bit is cleared (0). the next dat a transfer request is then waited for. notes 1. when the 16-bit data length (ccl bit of csim n register = 1) has been set, read the sirbn register. when the 8-bit data length (ccl bi t of csimn register = 0) has been set, read the sirbln register. 2. when the 16-bit data length (ccl bit of csimn re gister = 1) has been set, write to the sotbn register. when the 8-bit data length (ccl bit of csimn register = 0) has been set, write to the sotbln register. caution when the csotn bit of the csimn register = 1, do not manipulate the csin register.
chapter 10 serial interface function user?s manual u15195ej5v0ud 493 figure 10-27. timing chart in single transfer mode (1/2) (a) in transmission/recepti on mode, data length: 8 bits , transfer direction: msb first, no interrupt delay, single transfer mode, operation mode: ckp bit = 0, dap bit = 0 01010101 10101010 (55h) (aah) aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt 55h (transmit data) write 55h to sotbln register remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 494 figure 10-27. timing chart in single transfer mode (2/2) (b) in transmission/reception mode, da ta length: 8 bits, transfer directi on: msb first, no interrupt delay, single transfer mode, operation mode: ckp bit = 0, dap bit = 1 01010101 10101010 aah aah abh 56h adh 5ah b5h 6ah d5h sckn (i/o) son (output) sin (input) reg_r/w sotbln register sioln register sirbln register csotn bit intcsin interrupt (55h) (aah) 55h (transmit data) write 55h to sotbln register remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 495 (b) clock phase selection the following shows the timing when changing the conditions for clock phase selection (ckp bit of csicn register) and data phase selection (dap bit of csicn register) under the following conditions. ? data length = 8 bits (ccl bit of csimn register = 0) ? first bit of transfer data = msb (dirn bit of csimn register = 0) ? no interrupt request signal delay cont rol (csit bit of csimn register = 0) figure 10-28. timing chart accord ing to clock phase selection (1/2) (a) when ckp bit = 0, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (b) when ckp bit = 1, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 496 figure 10-28. timing chart accord ing to clock phase selection (2/2) (c) when ckp bit = 0, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 (d) when ckp bit = 1, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 do7 do6 do5 do4 do3 do2 do1 sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit di0 do0 remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 497 (c) transmission/reception completion interr upt request signals (intcsi0, intcsi1) intcsin is set (1) upon completion of data transmission/reception. caution the delay mode (csit bit = 1) is valid only in the master m ode (bits cks2 to cks0 of the csicn register are not 111b). the delay mode cannot be set when the slave mode is set (bits cks2 to cks0 = 111b). figure 10-29. timing chart of interrupt re quest signal output in delay mode (1/2) (a) when ckp bit = 0, dap bit = 0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 498 figure 10-29. timing chart of interrupt re quest signal output in delay mode (2/2) (b) when ckp bit = 1, dap bit = 1 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 input clock sckn (i/o) sin (input) son (output) reg_r/w intcsin interrupt csotn bit delay remarks 1. n = 0, 1 2. reg_r/w: internal signal. this signal indica tes that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed .
chapter 10 serial interface function user?s manual u15195ej5v0ud 499 (2) repeat transfer mode (a) usage (receive-only) <1> set the repeat transfer mode (auto bit of csimn r egister = 1) and the receiv e-only mode (trmdn bit of csimn register = 0). <2> read the sirbn register (start transfer with dummy read). <3> wait for the transmission/reception comp letion interrupt request (intcsin). <4> when the transmission/reception completion interrupt request (intcsin) has been set (1), read the sirbn register note (reserve next transfer). <5> repeat steps <3> and <4> (n ? 2) times. (n: number of transfer data) <6> following output of the last transmission/receptio n completion interrupt request (intcsin), read the sirben register and the sion register note . note when transferring n number of data, receive data is loaded by reading the si rbn register from the first data to the (n ? 2)th data. the (n ? 1)th data is loaded by reading the sirben register, and the nth (last) data is loaded by reading the sion register.
chapter 10 serial interface function user?s manual u15195ej5v0ud 500 figure 10-30. repeat transfer (receive-only) timing chart din-1 sckn (i/o) sin (input) son (output) l sioln register sirbln register reg_rd csotn bit intcsin interrupt rq_clr trans_rq din-2 din-1 sirbn (dummy) sirbn (d1) sirbn (d2) sirbn (d3) sirben (d4) sion (d5) < 4 >< 6 > < 4 >< 3 > < 3 > < 4 > < 5 > period during which next transfer can be reserved < 3 > < 2 > < 1 > din-2 din-3 din-4 din-5 din-5 din-3 din-4 remarks 1. n = 0, 1 2. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/ sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), trans fer is continued if the sirbn register can be read within the next transfer re servation period. if the si rbn register cannot be read, transfer ends and the sirbn register does not receive the new value of the sion register. the last data can be obtained by reading the sion register following completion of the transfer.
chapter 10 serial interface function user?s manual u15195ej5v0ud 501 (b) usage (transmission/reception) <1> set the repeat transfer mode (auto bit of csim n register = 1) and the transmission/reception mode (trmdn bit of csimn register = 1) <2> write the first data to the sotbfn register. <3> write the 2nd data to the sotbn register (start transfer). <4> wait for the transmission/reception comp letion interrupt request (intcsin). <5> when the transmission/reception completion interrupt request (intcsin) has been set (1), write the next data to the sotbn register (reserve next trans fer), and read the sirbn register to load the receive data. <6> repeat steps <4> and <5> as long as data to be sent remains. <7> wait for the intcsin interrupt. when the interrupt request signal is set (1), read the sirbn register to load the (n ? 1)th receive data (n: number of transfer data). <8> following the last transmission/reception comple tion interrupt request (intcsin), read the sion register to load the nth (last) receive data.
chapter 10 serial interface function user?s manual u15195ej5v0ud 502 figure 10-31. repeat transfer (t ransmission/reception) timing chart dout-1 dout-1 sckn (i/o) son (output) sin (input) sotbfln register sotbln register sioln register sirbln register reg_wr reg_rd csotn bit intcsin interrupt rq_clr trans_rq dout-2 dout-3 dout-4 dout-5 dout-2 dout-3 dout-4 dout-5 din-1 din-1 sotbfn (d1) sotbn (d2) sotbn (d3) sotbn (d4) sotbn (d5) sirbn (d1) sirbn (d2) < 5 >< 7 >< 8 > < 4 > < 5 > < 4 > < 6 > period during which next transfer can be reserved < 5 > < 4 > < 3 > < 2 > < 1 > sirbn (d3) sirbn (d4) sion (d5) din-2 din-3 din-4 din-5 din-2 din-3 din-4 din-5 remarks 1. n = 0, 1 2. reg_wr: internal signal. this signal indicate s that the transmit data buffer register (sotbn/ sotbln) has been written. reg_rd: internal signal. this signal indicates that the receive data buffer register (sirbn/ sirbln) has been read. rq_clr: internal signal. transfer request clear signal. trans_rq: internal signal. transfer request signal. in the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. following the transmission/reception completion interrupt request (intcsin), trans fer is continued if the sotbn register can be written within the next transfer reservation period. if the sotbn register cannot be written, transfer ends and the si rbn register does not receive the ne w value of the sion register. the last receive data can be obtained by reading the sion register following completion of the transfer.
chapter 10 serial interface function user?s manual u15195ej5v0ud 503 (c) next transfer reservation period in the repeat transfer mode, the next transfer must be prepared with the period shown in figure 10-32. figure 10-32. timing chart of next transfer reservation period (1/2) (a) when data length: 8 bits, operati on mode: ckp bit = 0, dap bit = 0 sckn (i/o) intcsin interrupt reservation period: 7 sckn cycles (b) when data length: 16 bits, opera tion mode: ckp bit = 0, dap bit = 0 sckn (i/o) intcsin interrupt reservation period: 15 sckn cycles remark n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 504 figure 10-32. timing chart of next transfer reservation period (2/2) (c) when data length: 8 bits, opera tion mode: ckp bit = 0, dap bit = 1 sckn (i/o) intcsin interrupt reservation period: 6.5 sckn cycles (d) when data length: 16 bits, opera tion mode: ckp bit = 0, dap bit = 1 sckn (i/o) intcsin interrupt reservation period: 14.5 sckn cycles remark n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 505 (d) cautions to continue repeat transfers, it is necessary to ei ther read the sirbn register or write to the sotbn register during the transfer reservation period. if access is performed to the sirbn register or the sotbn register when the transfer reservation period is over, the following occurs. (i) in case of conflict between transfer request clear and register access since request cancellation has higher priority, t he next transfer request is ignored. therefore, transfer is interrupted, and normal data transfer cannot be performed. figure 10-33. transfer request clear and register access conflict sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period remarks 1. n = 0, 1 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indicate s that the receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 10 serial interface function user?s manual u15195ej5v0ud 506 (ii) in case of conflict between inte rrupt request and register access since continuous transfer has stopped once, executed as a new repeat transfer. in the slave mode, a bit phase erro r transfer error results (refer to figure 10-34 ). in the transmission/reception mode, the value of t he sotbfn register is retransmitted, and illegal data is sent. figure 10-34. interrupt request and register access conflict sckn (i/o) intcsin interrupt rq_clr reg_r/w transfer reservation period 01 234 remarks 1. n = 0, 1 2. rq_clr: internal signal. transfer request clear signal. reg_r/w: internal signal. this signal indi cates that receive data buffer register (sirbn/ sirbln) read or transmit data buffer register (sotbn/sotbln) write was performed.
chapter 10 serial interface function user?s manual u15195ej5v0ud 507 10.4.5 output pins (1) sckn pin when the csin operation is disabled (csicaen bit of cs imn register = 0), the sckn pin output status is as follows (n = 0, 1). table 10-9. sckn pin output status ckp cks2 cks1 cks0 sckn pin output 0 don?t care don?t care don?t care fixed to high level 1 1 1 fixed to high level 1 other than above fixed to low level remarks 1. n = 0, 1 2. when any of the ckp and cks2 to cks0 bits of the csicn register is overwritten, the sckn pin output changes. (2) son pin when the csin operation is disabled (csicaen bit of cs imn register = 0), the son pin output status is as follows (n = 0, 1). table 10-10. son pin output status trmdn dap auto ccl dirn son pin output 0 don?t care don?t care don?t care don?t care fixed to low level 0 don?t care don?t care don?t care so latch value (low level) 0 sotb7 value 0 1 sotb0 value 0 sotb15 value 0 1 1 sotb0 value 0 sotbf7 value 0 1 sotbf0 value 0 sotbf15 value 1 1 1 1 1 sotbf0 value remarks 1. n = 0, 1 2. when any of the trmdn, ccl, dirn, and auto bits of the csimn register or dap bit of the csicn register is overwritten, the son pin output changes. 3. sotbm: bit m of sotbn register (m = 0, 7, 15) 4. sotbfm: bit m of sotbfn register (m = 0, 7, 15)
chapter 10 serial interface function user?s manual u15195ej5v0ud 508 10.4.6 dedicated baud ra te generator 3 (brg3) (1) configuration of baud rate generator 3 (brg3) dedicated baud rate generator output or the internal system clock (f xx ) can be selected for the csi0 and csi1 serial clocks. the serial clock source is specified by registers csic0 and csic1. if dedicated baud rate generator output is specifi ed, brg3 is selected as the clock source. since the same serial clock can be shared for transmiss ion and reception, baud rate is the same for both transmission and reception. figure 10-35. block diagram of baud rate generator 3 (brg3) bgcs1, bgcs0 prscm3 match detector 1/2 csin 8-bit timer counter f xx /4 f xx /8 f xx /16 f xx /32 selector remark f xx : internal system clock n = 0, 1
chapter 10 serial interface function user?s manual u15195ej5v0ud 509 (2) dedicated baud rate generator 3 (brg3) brg3 is configured by an 8-bit timer counter that gener ates the baud rate signal, prescaler mode register 3 (prsm3), which controls baud rate signal generation, prescaler compare register 3 (prscm3), which sets the value of the 8-bit timer counter, and a prescaler. (a) input clock the internal system clock (f xx ) is input to brg3. (b) prescaler mode register 3 (prsm3) the prsm3 register controls generation of the csi0 and csi1 baud rate signals. this register can be read/written in 8-bit or 1-bit units. cautions 1. do not change the value of th e bgcs1, bgcs0 bits during a transmission/ reception operation. 2. set the prsm3 register prior to setting the csicaen bit of the csimn register to 1 (n = 0, 1). 7 0 prsm3 6 0 5 0 4 ce 3 0 2 0 1 bgcs1 0 bgcs0 address fffff920h after reset 00h bit position bit name function 4 ce enables baud rate counter operation. 0: stops baud rate counter operation and fixes baud rate output signal to 0. 1: enables baud rate counter operation and starts baud rate output operation. selects count clock for baud rate counter. bgcs1 bgcs0 count clock selection 0 0 f xx /4 0 1 f xx /8 1 0 f xx /16 1 1 f xx /32 1, 0 bgcs1, bgcs0 remark f xx : internal system clock
chapter 10 serial interface function user?s manual u15195ej5v0ud 510 (c) prescaler compare register 3 (prscm3) prscm3 is an 8-bit compare register that sets the value of the 8-bit timer counter. this register can be read/written in 8-bit units. cautions 1. the internal timer counter is cleare d by writing to the prsm3 register. therefore, do not write to the prscm3 re gister during transmission. 2. set the prscm3 register prior to setting the csicaen bi t of the csimn register to 1 (n = 0, 1). if the contents of the prsc m3 register are overwritten when the value of the csicaen bit is 1, the cycle of th e baud rate signal is not guaranteed. 7 prscm7 prscm3 6 prscm6 5 prscm5 4 prscm4 3 prscm3 2 prscm2 1 prscm1 0 prscm0 address fffff922h after reset 00h (d) baud rate signal cycle the baud rate signal cycle is calculated as follows. ? when setting value of prscm3 register is 00h (cycle of signal selected by bits bgcs1, bgcs0 of prsm3 register) 256 2 ? in cases other than above (cycle of signal selected by bits bgcs1, bgcs2 of prsm3 register) (setting value of prscm3 register) 2
chapter 10 serial interface function user?s manual u15195ej5v0ud 511 (e) baud rate setting value table 10-11. baud rate generator setting data (a) when f xx = 32 mhz bgcs1 bgcs0 prscm register value clock (hz) 0 0 1 4,000,000 0 0 2 2,000,000 0 0 4 1,000,000 0 0 8 500,000 0 0 16 250,000 0 0 40 100,000 0 0 80 50,000 0 0 160 25,000 0 1 200 10,000 1 0 200 5,000 (b) when f xx = 40 mhz bgcs1 bgcs0 prscm register value clock (hz) 0 0 2 2,500,000 0 0 5 1,000,000 0 0 10 500,000 0 0 20 250,000 0 0 50 100,000 0 0 100 50,000 0 0 200 25,000 0 1 250 10,000 1 0 250 5,000 caution set the transfer cl ock so that it does not fall below the minimum value of 200 ns of the sckn cycle (t cysk1 ) prescribed in the elect rical specifications.
512 user?s manual u15195ej5v0ud chapter 11 a/d converter 11.1 features two 10-bit resolution on-chip a/d converters (a/d converter 0 and 1) simultaneous sampling by two circuits is possible. analog input: total of 14 channels for two circuits a/d converter 0: 6 channels a/d converter 1: 8 channels on-chip a/d conversion result registers 0m, 1n (adcr0m, adcr1n) 10 bits 6 registers + 10 bits 8 registers a/d conversion trigger mode a/d trigger mode a/d trigger polling mode timer trigger mode external trigger mode successive approximation technique voltage detection mode remark m = 0 to 5, n = 0 to 7 11.2 configuration a/d converters 0 and 1, which employ a successive ap proximation technique, perform a/d conversion operations using a/d scan mode registers 00, 01, 10, and 11 (adscm00, adscm01, adscm10, and adscm11) and registers adcr0m and adcr1n (m = 0 to 5, n = 0 to 7). (1) input circuit the input circuit selects an analog input (ani0m or ani1n) according to the mode set in the adscm00 or adscm10 register and sends it to the sample and hold circuit (m = 0 to 5, n = 0 to 7). (2) sample and hold circuit the sample and hold circuit individually samples anal og inputs sent sequentially fr om the input circuit and sends them to the comparator. it holds sampled analog inputs during a/d conversion. (3) voltage comparator the voltage comparator compares t he analog input voltage that was i nput with the output voltage of the d/a converter.
chapter 11 a/d converter 513 user?s manual u15195ej5v0ud (4) d/a converter the d/a converter is used to generate the voltage that matches the analog input. the output voltage of the d/ a converter is controlled by the succe ssive approximation register (sar). (5) successive approximation register (sar) the sar is a 10-bit register that c ontrols the output value of the d/a c onverter for comparing with the analog input voltage value. when an a/d conversion ends, t he current contents of the sar (conversion result) are stored in an a/d conversion result register (adcr0m, adcr1n) (m = 0 to 5, n = 0 to 7). when all specified a/d conversions end, an a/d conversion end inte rrupt (intad0, intad1) is also generated. (6) a/d conversion result regi sters 0m, 1n (adcr0m, adcr1n) adcr0m and adcr1n are 10-bit registers that hold a/d conversion results (m = 0 to 5, n = 0 to 7). whenever an a/d conversion ends, the conversion result from the successive approximation register (sar) is loaded. reset input sets these registers to 0000h. (7) controller the controller selects an analog input, generates samp le and hold circuit operation timing, controls conversion triggers, and specifies th e conversion operation time according to the mode set by the adscmn0 or adscmn1 register. (8) ani0m, ani1n pins (m = 0 to 5, n = 0 to 7) the ani0n and ani1n pins are the analog input pins of each channel (total of 14 channels for two circuits) for analog converters 0 and 1. they input analog signals to be a/d converted. caution make sure that the voltag es input to ani0m and ani1n are wit hin the range of the ratings. in particular, if a voltage (inc luding noise) higher than av dd0 and av dd1 or lower than av ss0 and av ss1 (even if within the range of absolute maximum ratings) is in put, the conversion value of that channel is invalid, and the con version values of other channels may also be affected. (9) av ss0 , av ss1 pins the av ss0 and av ss1 pins are the ground voltage pins of a/d converters 0 and 1. even if not using a/d converters 0 and 1, always ensure thes e pins have the same potential as the v ss pin. (10) av dd0 , av dd1 pins the av dd0 and av dd1 pins are the analog power supply pins of a/d converters 0 and 1. these pins are also used as pins that input a refer ence voltage (equivalent to the av ref0 and av ref1 pins of the v850e/ia1). therefore, the signals input to the ani0m and ani1n pi ns are converted into digital signals, based on the voltage applied between av dd0 and av ss0 and between av dd1 and av ss1 (m = 0 to 5, n = 0 to 7). even if not using a/d converters 0 and 1, always ensure these pins have the same potential as the v dd pin.
chapter 11 a/d converter 514 user?s manual u15195ej5v0ud figure 11-1. block diagram of a/d converter 0 or 1 adscmn0 (16) 15 0 adtrgn intadn sample and hold circuit anin0 anin1 anin2 anin3 anin4 anin5 ani16 ani17 itrg0 16 16 16 16 adscmn1 (16) 15 0 adetm0 (16) 15 0 adetm1 (16) 15 0 90 trigger source switching circuit in timer trigger mode (see figure 11-2 ) controller 10 10 sar (10) comparator and d/a converter av ddn av ssn intdetn adcrn0 adcrn1 adcrn2 adcrn3 adcrn4 adcrn5 adcr16 adcr17 internal bus input circuit f xx /2 remark n = 0, 1 f xx : internal system clock cautions 1. noise at an analog input pin (ani 0m, ani1n) or referen ce voltage input pin (av dd0 , av dd1 ) may give rise to an invalid conversion r esult (m = 0 to 5, n = 0 to 7). software processing is needed in order to prevent this invalid conversion result from adversely affecting the system. the following are exam ples of software processing. ? use the average value of the results of multiple a/d conversions as the a/d conversion result. perform a/d conversion several times con secutively and use conver sion results omitting any abnormal conversion resu lts that are obtained. if an a/d conversion result from which it is judged that an abnormality occurred in the system is obtained, be sure to recheck the abnormality occurrence before performing malfunction processing. 2. be sure that voltages outside the range [av ss0 to av dd0 , av ss1 to av dd1 ] are not applied to pins being used as a/d converter 0 and 1 input pins.
chapter 11 a/d converter 515 user?s manual u15195ej5v0ud figure 11-2. block diagram of trigger sour ce switching circuit in timer trigger made itrg13 000 001 01x 100 101 11x 000 001 01x 100 101 11x itrg12 itrg11 00 01 1x adtrg0 intcm003 intcm013 adtrg1 inttm00 inttm01 intcm004 intcm005 1 0 1 0 itrg10 00 01 1x intcm014 intcm015 itrg23 itrg0 itrg1 itrg22 itrg21 itrg20 itrg13 itrg12 itrg11 itrg10 0 0 itrg41 itrg40 0 0 itrg31 itrg30 selector selector selector internal bus selector selector trigger trigger trigger trigger a/d converter 0 a/d converter 1 selector caution for the selection of the tri gger source in timer trigger mode, re fer to table 11-4 timer trigger source selection of a/d converters 0 and 1. remark x: don?t care
chapter 11 a/d converter 516 user?s manual u15195ej5v0ud 11.3 functions added to v850e/ia2 (1) addition of intcm004, intcm005, in tcm014, intcm015 as timer trigger sources the timer trigger source (inttm0n, intcm0n3 to intcm 0n5) is selected using a/d internal trigger selection registers 0 and 1 (itrg0 and itrg1) when the timer tr igger mode is set by a/d scan mode registers 00 and 10 (adscm00 and adscm10). with the v850e/ia2, bit 3 (itrg13) and bit 7 (itrg23) of the itrg0 register, as we ll as the itrg1 register have been added. (2) changing analog input to a to tal of 14 channels for two circuits (3) multiplexing av ref0 and av ref1 with av dd0 and av dd1
chapter 11 a/d converter 517 user?s manual u15195ej5v0ud 11.4 control registers (1) a/d scan mode registers 00 and 10 (adscm00, adscm10) the adscmn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operations. they can be read or written in 16-bit units. when the higher 8 bits of the adscmn0 register are us ed as the adscmn0h register and the lower 8 bits are used as the adscmn0l register, they can be read/written in 8-bit or 1-bit units. however, writing to the adscmn0 register during a/ d conversion initializes conversion and starts the conversion operation from the beginning. caution clear (0) the adcen bit before changing the trigger mode using the adplmn and trg2 to trg0 bits (n = 0, 1). if the changing of th e trigger mode and clearing of the adcen bits are performed simultaneously (sam e instruction), operation is not guaranteed. be sure to perform register access twice. (1/2) <14> ad cs0 13 0 <12> ad ms0 2 anis2 3 anis3 4 sani0 5 sani1 6 sani2 7 sani3 8 trg0 9 trg1 10 trg2 <11> ad plm0 <15> ad ce0 1 anis1 0 anis0 <14> ad cs1 13 0 <12> ad ms1 2 anis2 3 anis3 4 sani0 5 sani1 6 sani2 7 sani3 8 trg0 9 trg1 10 trg2 <11> ad plm1 <15> ad ce1 1 anis1 0 anis0 adscm00 address fffff200h after reset 0000h adscm10 address fffff240h after reset 0000h bit position bit name function 15 adcen specifies enabling or disabling a/d conversion. 0: disable 1: enable 14 adcsn shows status of a/d converte r 0 or 1. this bit is read-only. 0: stopped 1: operating adcsn bit is 0 during the period of 6 f xx /2 immediately after the start of a/d conversion, and then set to 1. this operation is performed each time an analog input pin has been switched for a/d conversion in the scan mode. 12 admsn specifies operation mode of a/d converter 0 or 1. 0: scan mode 1: select mode adplmn: specifies polling mode. trg2 to trg0: specifies trigger mode. adplmn trg2 trg1 trg0 trigger mode 0 0 0 0 a/d trigger mode 0 0 0 1 timer trigger mode 0 1 1 1 external trigger mode 1 0 0 0 a/d trigger polling mode other than above setting prohibited 11 to 8 adplmn, trg2 to trg0 remark n = 0, 1
chapter 11 a/d converter 518 user?s manual u15195ej5v0ud (2/2) bit position bit name function specifies conversion start anal og input pin in scan mode. these bits are ignored in select mode. sani3 sani2 sani1 sani0 scan start analog input pin 0 0 0 0 anin0 0 0 0 1 anin1 0 0 1 0 anin2 0 0 1 1 anin3 0 1 0 0 anin4 0 1 0 1 anin5 0 1 1 0 ani16 0 1 1 1 ani17 other than above setting prohibited 7 to 4 sani3 to sani0 caution always set the conversion star t analog input pin number that is set by bits sani3 to sani0 to a smaller pin number than the conversion end analog input pin number that is set by bits anis3 to anis0. specifies analog input pin in select mode. in scan mode, specifies conversi on termination analog input pin. anis3 anis2 anis1 anis0 in select mode in scan mode 0 0 0 0 anin0 anin0 0 0 0 1 anin1 sani anin1 0 0 1 0 anin2 sani anin2 0 0 1 1 anin3 sani anin3 0 1 0 0 anin4 sani anin4 0 1 0 1 anin5 sani anin5 0 1 1 0 ani16 sani ani16 0 1 1 1 ani17 sani ani17 other than above setting prohibited 3 to 0 anis3 to anis0 remar k sani < aninm where n = 0: m = 1 to 5 where n = 1: m = 1 to 7 remark n = 0, 1
chapter 11 a/d converter 519 user?s manual u15195ej5v0ud (2) a/d scan mode registers 01 and 11 (adscm01, adscm11) the adscmn1 registers are 16-bit registers that set the conversi on time of the a/d converter. they can be read or written in 16-bit units. when the higher 8 bits of the adscmn1 register are us ed as the adscmn1h register, and the lower 8 bits are used as the adscmn1l register, the adscmn1h r egister can be read/writt en in 8-bit units, and the adscmn1l register is read-only, in 8-bit units. caution do not write to the adscm n1 registers during an a/d conver sion operation. if a write is performed, the conversion operation is su spended and subseque ntly terminates. 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 fr0 9 fr1 10 fr2 11 0 15 0 1 0 0 0 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 fr0 9 fr1 10 fr2 11 0 15 0 1 0 0 0 adscm01 address fffff202h after reset 0000h adscm11 address fffff242h after reset 0000h bit position bit name function specifies conversion time. conversion time ( s) note fr2 fr1 fr0 conversion clocks f xx = 40 mhz f xx = 33 mhz 0 0 0 344 8.60 ? 0 0 1 248 6.20 7.51 0 1 0 176 ? 5.33 0 1 1 128 ? ? 1 0 0 104 ? ? 1 0 1 80 ? ? 1 1 0 56 ? ? 1 1 1 setting prohibited ? 10 to 8 fr2 to fr0 note this is the time from sampling until conversion end. sampling time = (conversion clocks ? 8)/6 f xx caution be sure to secure the conversi on time within a range of 5 to 10 s. conversion time = f xx conversion clocks remark f xx : internal system clock
chapter 11 a/d converter 520 user?s manual u15195ej5v0ud (3) a/d voltage detection mode re gisters 0 and 1 (adetm0, adetm1) the adetmn registers are 16-bit re gisters that set the voltage detecti on mode. in the voltage detection mode, the analog input pin for which voltage detection is being perform ed and a reference voltage value are compared and an interrupt is set in response to the comparison result. these registers can be read or written in 16-bit units. when the higher 8 bits of the adetmn register are used as the adetmnh register, and the lower 8 bits are used as the adetmnl register, they can be read/written in 8-bit or 1-bit units. caution do not write to an adetmn register duri ng an a/d conversion operation. if a write is performed, conversion is suspended and it subsequently terminates. address fffff204h after reset 0000h <14> adet lh0 13 det ani3 12 det ani2 2 det cmp2 3 det cmp3 4 det cmp4 5 det cmp5 6 det cmp6 7 det cmp7 8 det cmp8 9 det cmp9 10 det ani0 11 det ani1 <15> adet en0 1 det cmp1 0 det cmp0 adetm0 address fffff244h after reset 0000h <14> adet lh1 13 det ani3 12 det ani2 2 det cmp2 3 det cmp3 4 det cmp4 5 det cmp5 6 det cmp6 7 det cmp7 8 det cmp8 9 det cmp9 10 det ani0 11 det ani1 <15> adet en1 1 det cmp1 0 det cmp0 adetm1 bit position bit name function 15 adetenn specifies voltage detection mode. 0: operates in normal mode 1: operates in voltage detection mode 14 adetlhn sets voltage comparison detection. 0: generates intdetn interrupt if reference voltage value > analog input pin voltage. 1: generates intdetn interrupt if reference voltage value < analog input pin voltage. selects analog input pin to compare to reference voltage value set by detcmp9 to detcmp0 when in voltage detection mode. detani3 detani2 detani1 detani0 voltage detection analog input pin 0 0 0 0 anin0 0 0 0 1 anin1 0 0 1 0 anin2 0 0 1 1 anin3 0 1 0 0 anin4 0 1 0 1 anin5 0 1 1 0 ani16 0 1 1 1 ani17 1 setting prohibited 13 to 10 detani3 to detani0 remark : don?t care 9 to 0 detcmp9 to detcmp0 sets reference voltage value to compare with analog input pin selected by detani3 to detani0. remark n = 0, 1
chapter 11 a/d converter 521 user?s manual u15195ej5v0ud (4) a/d conversion result registers 00 to 05 and 10 to 17 (adcr00 to adcr05, adcr10 to adcr17) the adcr0m and adcr1n registers are 10-bit registers th at hold the results of a/d conversions (m = 0 to 5, n = 0 to 7). a/d converter 0 has six 10-bit register s for six channels and a/d converter 1 has eight 10-bit registers for eight channels. in all, fourteen 10-bit registers are available. these registers are read-only, in 16-bit units. when reading 10 bits of data of an a/d conversion result from the a dcr0m or adcr1n register, only the lower 10 bits are valid and the higher 6 bits are always read as 0. 14 0 13 0 12 0 2 adcrm2 3 adcrm3 4 adcrm4 5 adcrm5 6 adcrm6 7 adcrm7 8 adcrm8 9 adcrm9 10 0 11 0 15 0 1 adcrm1 0 adcrm0 adcr0m (m = 0 to 5) address see table 11-1 after reset 0000h adcr1n (n = 0 to 7) address see table 11-2 after reset 0000h 14 0 13 0 12 0 2 adcrn2 3 adcrn3 4 adcrn4 5 adcrn5 6 adcrn6 7 adcrn7 8 adcrn8 9 adcrn9 10 0 11 0 15 0 1 adcrn1 0 adcrn0 table 11-1. correspondence be tween adcr0m (m = 0 to 5) register names and addresses register name address adcr00 fffff210h adcr01 fffff212h adcr02 fffff214h adcr03 fffff216h adcr04 fffff218h adcr05 fffff21ah table 11-2. correspondence be tween adcr1n (n = 0 to 7) register names and addresses register name address adcr10 fffff250h adcr11 fffff252h adcr12 fffff254h adcr13 fffff256h adcr14 fffff258h adcr15 fffff25ah adcr16 fffff25ch adcr17 fffff25eh
chapter 11 a/d converter 522 user?s manual u15195ej5v0ud the correspondence between the analog input pins and the adcr0m and adcr1n registers is shown below. table 11-3. correspondence between analog input pins and adcr0m and adcr1n registers a/d converter analog input pin a/d conversion result register ani00 adcr00 ani01 adcr01 ani02 adcr02 ani03 adcr03 ani04 adcr04 a/d converter 0 ani05 adcr05 ani10 adcr10 ani11 adcr11 ani12 adcr12 ani13 adcr13 ani14 adcr14 ani15 adcr15 ani16 adcr16 a/d converter 1 ani17 adcr17
chapter 11 a/d converter 523 user?s manual u15195ej5v0ud the relationship between the analog voltage input to an analog input pin (ani0m or ani1n) and the value of the a/d conversion result register (adcr0m or adcr1n) is as follows (m = 0 to 5, n = 0 to 7): v in adcr = int ( 1,024 + 0.5) av dd or, av dd av dd (adcr ? 0.5) v in < (adcr + 0.5) 1,024 1,024 int ( ): function that returns integer of value in ( ) v in : analog input voltage av dd : av dd0 or av dd1 pin voltage adcr: value of a/d conversion resu lt register (adcr0m or adcr1n) figure 11-3 illustrates the relationship between the analog input voltages and a/d conversion results. figure 11-3. relationship between analog input voltages and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ddm 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion result (adcrx) remark m = 0, 1 x = 00 to 05, 10 to 17
chapter 11 a/d converter 524 user?s manual u15195ej5v0ud (5) a/d internal trigger selection registers 0, 1 (itrg0, itrg1) the itrgn register switches the trigger source in timer trigger mode. the timer trigger source of a/d converters 0 and 1 can be se t using the itrgn register. this register can be read or written in 8-bit or 1-bit units. 7 itrg23 itrg0 6 itrg22 5 itrg21 4 itrg20 3 itrg13 2 itrg12 1 itrg11 0 itrg10 address fffff280h after reset 00h 7 0 itrg1 6 0 5 itrg41 4 itrg40 3 0 2 0 1 itrg31 0 itrg30 address fffff288h after reset 00h bit position bit name function 7 to 0 (itrg0) 5, 4, 1, 0 (itrg1) itrg23 to itrg20, itrg13 to itrg10 (itrg0) itrg41, itrg40, itrg31, itrg30 (itrg1) specifies timer trigger source of a/d converters 0 and 1 (refer to table 11-4 timer trigger source selection of a/d converters 0 and 1 ).
chapter 11 a/d converter 525 user?s manual u15195ej5v0ud table 11-4. timer trigger source select ion of a/d converters 0 and 1 (1/3) itrgm3 itrgm2 itrgm1 itrg41 itrg40 itrg31 itrg30 itrg20 itrg10 trigger source of a/d converter n 0 0 0 0 selects intcm003 0 0 0 1 selects intcm013 0 0 1 0 selects inttm00 0 0 1 1 selects inttm01 0 1 0 0 selects intcm003, inttm00 0 1 0 1 selects intcm013, inttm00 0 1 1 0 selects intcm003, inttm01 0 1 1 1 selects intcm013, inttm01 1 0 0 0 0 selects intcm004 1 0 0 0 1 selects intcm005 1 0 0 1 selects intcm004, intcm005 1 0 1 0 0 selects intcm014 1 0 1 0 1 selects intcm015 1 0 1 1 selects intcm014, intcm015 1 1 0 0 0 0 0 0 selects intcm003, inttm00, intcm004, intcm014 1 1 0 0 0 0 0 1 selects intcm013, inttm00, intcm004, intcm014 1 1 0 0 0 0 1 0 selects intcm003, inttm01, intcm004, intcm014 1 1 0 0 0 0 1 1 selects intcm013, inttm01, intcm004, intcm014 1 1 0 0 0 1 0 0 selects intcm003, inttm00, intcm005, intcm014 1 1 0 0 0 1 0 1 selects intcm013, inttm00, intcm005, intcm014 1 1 0 0 0 1 1 0 selects intcm003, inttm01, intcm005, intcm014 1 1 0 0 0 1 1 1 selects intcm013, inttm01, intcm005, intcm014 1 1 0 0 1 0 0 selects intcm003, inttm00, intcm004, intcm005, intcm014 1 1 0 0 1 0 1 selects intcm013, inttm00, intcm004, intcm005, intcm014 1 1 0 0 1 1 0 selects intcm003, inttm01, intcm004, intcm005, intcm014 remarks 1. n = 0, 1 where n = 0: m = 1 where n = 1: m = 2 2. : don?t care
chapter 11 a/d converter 526 user?s manual u15195ej5v0ud table 11-4. timer trigger source select ion of a/d converters 0 and 1 (2/3) itrgm3 itrgm2 itrgm1 itrg41 itrg40 itrg31 itrg30 itrg20 itrg10 trigger source of a/d converter n 1 1 0 0 1 1 1 selects intcm013, inttm01, intcm004, intcm005, intcm014 1 1 0 1 0 0 0 0 selects intcm003, inttm00, intcm004, intcm015 1 1 0 1 0 0 0 1 selects intcm013, inttm00, intcm004, intcm015 1 1 0 1 0 0 1 0 selects intcm003, inttm01, intcm004, intcm015 1 1 0 1 0 0 1 1 selects intcm013, inttm01, intcm004, intcm015 1 1 0 1 0 1 0 0 selects intcm003, inttm00, intcm005, intcm015 1 1 0 1 0 1 0 1 selects intcm013, inttm00, intcm005, intcm015 1 1 0 1 0 1 1 0 selects intcm003, inttm01, intcm005, intcm015 1 1 0 1 0 1 1 1 selects intcm013, inttm01, intcm005, intcm015 1 1 0 1 1 0 0 selects intcm003, inttm00, intcm004, intcm005, intcm015 1 1 0 1 1 0 1 selects intcm013, inttm00, intcm004, intcm005, intcm015 1 1 0 1 1 1 0 selects intcm003, inttm01, intcm004, intcm005, intcm015 1 1 0 1 1 1 1 selects intcm013, inttm01, intcm004, intcm005, intcm015 1 1 1 0 0 0 0 selects intcm003, inttm00, intcm004, intcm014, intcm015 1 1 1 0 0 0 1 selects intcm013, inttm00, intcm004, intcm014, intcm015 1 1 1 0 0 1 0 selects intcm003, inttm01, intcm004, intcm014, intcm015 1 1 1 0 0 1 1 selects intcm013, inttm01, intcm004, intcm014, intcm015 1 1 1 0 1 0 0 selects intcm003, inttm00, intcm005, intcm014, intcm015 1 1 1 0 1 0 1 selects intcm013, inttm00, intcm005, intcm014, intcm015 1 1 1 0 1 1 0 selects intcm003, inttm01, intcm005, intcm014, intcm015 remarks 1. n = 0, 1 where n = 0: m = 1 where n = 1: m = 2 2. : don?t care
chapter 11 a/d converter 527 user?s manual u15195ej5v0ud table 11-4. timer trigger source select ion of a/d converters 0 and 1 (3/3) itrgm3 itrgm2 itrgm1 itrg41 itrg40 itrg31 itrg30 itrg20 itrg10 trigger source of a/d converter n 1 1 1 0 1 1 1 selects intcm013, inttm01, intcm005, intcm014, intcm015 1 1 1 1 0 0 selects intcm003, inttm00, intcm004, intcm005, intcm014, intcm015 1 1 1 1 0 1 selects intcm013, inttm00, intcm004, intcm005, intcm014, intcm015 1 1 1 1 1 0 selects intcm003, inttm01, intcm004, intcm005, intcm014, intcm015 1 1 1 1 1 1 selects intcm013, inttm01, intcm004, intcm005, intcm014, intcm015 remarks 1. n = 0, 1 where n = 0: m = 1 where n = 1: m = 2 2. : don?t care
chapter 11 a/d converter 528 user?s manual u15195ej5v0ud 11.5 interrupt requests a/d converters 0 and 1 generate two kinds of interrupts. a/d conversion end interrupts (intad0, intad1) voltage detection interrupts (intdet0, intdet1) (1) a/d conversion end in terrupts (intad0, intad1) in the a/d conversion enabled status , an a/d conversion end interrupt is generated when a specified number of a/d conversions have been completed. a/d converter a/d conversion end interrupt signal 0 generates intad0 1 generates intad1 (2) voltage detection interrupt (intdet0, intdet1) in the voltage detection mode (adeten0 or adeten1 bit of adetm0 or adetm1 = 1), the value of the adcr0m or adcr1n register of the relevant analog input pin is compared with the reference voltage set in the detcmp9 to detcmp0 bits of the adetm0 or ad etm1 register and a voltag e detection interrupt is generated in response to the value of the adetlh0 or adetlh1 bit of the adetm0 or adetm1 register (m = 0 to 5, n = 0 to 7). a/d converter voltage detection interrupt signal 0 generates intdet0 1 generates intdet1
chapter 11 a/d converter 529 user?s manual u15195ej5v0ud 11.6 a/d converter operation 11.6.1 a/d converter basic operation a/d conversion is performed us ing the following procedure. (1) set the analog input selection and the operation mode and trigger mode specifications using the adscm00 or adscm10 register note 1 . setting (1) the adce0 or adce1 bit of the adscm00 or adscm10 register when in a/d trigger mode or a/d trigger polling mode starts a/d conversion. in timer trigger mode or external trigger mode, the status becomes trigger standby note 2 . (2) when a/d conversion starts, compare the analog in put with the voltage generat ed by the d/a converter. (3) when 10-bit comparison ends, store the conversion result in the adcr0m or adcr1n register. when the specified number of a/d conversion s have ended, generate the a/d conv ersion end interrupt (intad0, intad1) (m = 0 to 5, n = 0 to 7). notes 1. if the contents of the adscm00 or adscm10 re gister are changed during an a/d conversion operation, the a/d conversion oper ation preceding the change stops an d a conversion result is not stored in the adcr0m or adcr1n register. the co nversion operation is initialized and conversion starts from the beginning. 2. in timer trigger mode or external trigger mode, ther e is a transition to trigger standby status when the adce0 or adce1 bit of the adscm00 or adscm10 register is set to 1. an a/d conversion operation is activated by a trigger signal and there is a retu rn to trigger standby stat us when the a/d conversion operation ends. the timer trigger is selected by the itrg0 and it rg1 registers.
chapter 11 a/d converter 530 user?s manual u15195ej5v0ud 11.6.2 operation modes and trigger modes diverse conversion operations can be specified for a/d c onverters 0 and 1 by specif ying the operation mode and trigger mode. the operation mode and trigger mode are set using the adscm00 or adscm10 register. the relationship between the operation mode and the trigger mode is shown below. setting trigger mode operation mode adscm00 adscm10 select xx010000xxxxxxxxb xx010000xxxxxxxxb ad trigger scan xx000000xxxxxxxxb xx000000xxxxxxxxb select xx011000xxxxxxxxb xx011000xxxxxxxxb ad trigger polling scan xx001000xxxxxxxxb xx001000xxxxxxxxb select xx010001xxxxxxxxb xx010001xxxxxxxxb timer trigger scan xx000001xxxxxxxxb xx000001xxxxxxxxb select xx010111xxxxxxxxb xx010111xxxxxxxxb external trigger scan xx000111xxxxxxxxb xx000111xxxxxxxxb (1) trigger modes four trigger modes that serve as the start timing of a/d conversion processing are available: a/d trigger mode, a/d trigger polling mode, timer tr igger mode, and external trigger mode. these trigger modes are set using the adscm00 and adscm10 registers. (a) a/d trigger mode a/d trigger mode, which starts the conversion timi ng for the analog input set for the ani0m or ani1n pin (m = 0 to 5, n = 0 to 7), is a mode in which a/d conv ersion is started by setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1. in this mode, it is necessary to set the adce0 or adce1 bit to 1 as an a/d conversion restart operation after the intad0 or intad1 interrupt (adcs0, adcs1 = 0). (b) a/d trigger polling mode a/d trigger polling mode, which starts the conversi on timing of the analog input set for the ani0m or ani1n pin (m = 0 to 5, n = 0 to 7), is a mode in wh ich a/d conversion is started by setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1. in this mode, it is not necessary to set the adce0 or adce1 bit to 1 as an a/d conversion restar t operation after the intad0 or intad1 interrupt (adcs0, adcs1 = 1). the specified analog input is converted serially until the adce0 or adce1 bit is set to 0. the intad0 or intad1 interrupt occurs each time a conversion ends. (c) timer trigger mode timer trigger mode, which starts the conversion timing of the analog input set for the ani0m or ani1n pin (m = 0 to 5, n = 0 to 7), is a mode governed by the tr igger specified by the a/d internal trigger selection registers 0 and 1 (itrg0, itrg1). (d) external trigger mode external trigger mode, which starts the conversion timing of the analog input set using the ani0m and ani1n pins, is a mode specified using the adtrg0 or adtrg1 pin (m = 0 to 5, n = 0 to 7).
chapter 11 a/d converter 531 user?s manual u15195ej5v0ud (2) operation modes the two operation modes, which are the modes that se t the ani00 to ani05 and ani10 to ani17 pins, are select mode and scan mode. these modes are set using the adscm00 and adscm10 registers. (a) select mode in select mode, one analog input specified by the ad scm00 or adscm10 register is a/d converted. the conversion result is stored in the adcr0m or adcr1n register corresponding to the analog input (ani0m or ani1n) (m = 0 to 5, n = 0 to 7). figure 11-4. example of select mode op eration timing (ani01): for a/d converter 0 ani01 (input) a/d conversion data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 5 (ani01) data 6 (ani01) data 7 (ani01) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani01) data 2 (ani01) data 3 (ani01) data 4 (ani01) data 6 (ani01) adcr01 register intad0 interrupt conversion start (adscm0 register setting) adce0 bit set adce0 bit set adce0 bit set adce0 bit set adce0 bit set conversion start (adscm0 register setting) ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adcr0m register analog input
chapter 11 a/d converter 532 user?s manual u15195ej5v0ud (b) scan mode in scan mode, pins from the a/d conversion star t analog input pin to the a/d conversion termination analog input pin specified by the adscm00 or adsc m10 register are sequentially selected and a/d converted. the a/d conversion result is stored in the adcr0m or adcr1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). when the specified analog input conversion ends, the a/d conversion end interrupt (intad0 or intad1) is generated. figure 11-5. example of scan mode operation timing: for a/d converter 0 (4-channel scan (ani00 to ani03)) ani00 (input) ani01 (input) ani02 (input) ani03 (input) a/d conversion data 1 (ani00) data 2 (ani01) data 3 (ani02) data 4 (ani03) data 5 (ani00) data 6 (ani01) data 1 data 2 data 3 data 4 data 5 data 6 data 1 (ani00) adcr00 data 2 (ani01) adcr01 data 3 (ani02) adcr02 data 4 (ani03) adcr03 data 5 (ani00) adcr00 adcr0n register intad0 interrupt conversion start (adscm00 register setting) conversion start (adscm00 register setting) data 1 (ani00) ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adcr0m register analog input
chapter 11 a/d converter 533 user?s manual u15195ej5v0ud 11.7 operation in a/d trigger mode setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1 starts a/d conversion. 11.7.1 operation in select mode one analog input specified by the adscm00 or adscm10 r egister is a/d converted at a time and the result is stored in the adcr0m or adcr1n register. analog i nputs correspond one-to-one with the adcr0m or adcr1n register (m = 0 to 5, n = 0 to 7). the a/d conversion end interrupt (i ntad0, intad1) is generated at the end of each a/d conversion, which terminates a/d conversion (adcs0, adcs1 bit = 0). analog input a/d conversion result register anix adcrx remark x = 00 to 05, 10 to 17 to restart a/d conversion, write 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register. this is optimal for an application that reads a result for each a/d conversion. figure 11-6. example of select mode (a/d tri gger select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) generate intad0 interrupt
chapter 11 a/d converter 534 user?s manual u15195ej5v0ud 11.7.2 operation in scan mode pins from the conversion start analog input pin to th e conversion termination analog input pin specified by adscm00 or adscm10 register are sequentially selected and a/d converted. an a/d conv ersion result is stored in the adcr0m or adcr1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). when conversion ends for all analog inputs up to the conversion termination analog input pin, the a/d conversi on end interrupt (intad0, intad1) is generated, which terminates a/d conversion (adcs 0 or adcs1 bit of adscm0 or adscm1 register = 0). analog input a/d conversion result register anix note 1 adcrx | | anix note 2 adcrx notes 1. set using the sani3 to sani0 bits of the adscm00 or adscm10 register. be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to note 2. 2. set using the anis3 to anis0 bits of the adscm00 or adscm10 register. remark x = 00 to 05, 10 to 17 to restart a/d conversion, write 1 in the adce0 or adce 1 bit of the adscm00 or adscm10 register. this is optimal for an application that regular ly monitors multiple analog inputs. figure 11-7. example of scan mode (a/d trigger scan) operation (ani02 to ani05): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) a/d conversion of ani03 (5) store conversion result in adcr03 (6) a/d conversion of ani04 (7) store conversion result in adcr04 (8) a/d conversion of ani05 (9) store conversion result in adcr05 (10) generate intad0 interrupt
chapter 11 a/d converter 535 user?s manual u15195ej5v0ud 11.8 operation in a/d trigger polling mode setting the adce0 or adce1 bit of the adscm00 or adscm10 register to 1 starts a/d conversion. both select mode and scan mode are available in a/d trig ger polling mode. since the adcs0 or adcs1 bit of the adscm00 or adscm10 register remains 1 after the intad0 or intad1 interrupt in this mode, it is not necessary to write 1 in the adce0 or adce1 bit as an a/d conversion restart operation. 11.8.1 operation in select mode the analog input specified in the adscm00 or adscm10 re gister is a/d converted. the conversion result is stored in the adcr0m or adcr1n register (m = 0 to 5, n = 0 to 7). one analog input is a/d conv erted at a time and the result is stored in one adcr0m or adcr1n register. analog inputs correspond one-to-one with the adcr0m or adcr1n register. an a/d conversion end interrupt (intad0 or intad1) is generated at the end of ea ch a/d conversion. a/d conversion operations are repeat ed until the adce0 or adce1 bit = 0 (adcs0, adcs1 bit = 1). analog input a/d conversion result register anix adcrx remark x = 00 to 05, 10 to 17 in a/d trigger polling mode, it is not necessary to wr ite 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register as an a/d conversion restart operation note . this is optimal for applications that regularly read a/d conversion values. note in a/d trigger polling mode, the fact that the adce 0 or adce1 bit of the adscm00 or adscm10 register is 0 means that a/d conversion does not stop as long as the adcs0 or adcs1 bit is not 0. therefore, if the adcr0m or adcr1n register is not read befor e the next a/d conversion, it is overwritten. figure 11-8. example of select mode (a/d trigger polling select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) generate intad0 interrupt (5) return to (2)
chapter 11 a/d converter 536 user?s manual u15195ej5v0ud 11.8.2 operation in scan mode pins from the conversion start analog input pin to the conversion termination analog input pin specified by the adscm00 or adscm10 register are sequentially selected and a/d converted. t he a/d conversion result is stored in the adcr0m or adcr1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). when conversion ends for all analog inputs up to the conversion termination analog input pin, the a/d conversi on end interrupt (intad0, intad1) is generated. a/d conversion repeats until t he adce0 or adce1 bit = 0 (adcs0, adcs1 bit = 1). analog input a/d conversion result register anix note 1 adcrx | | anix note 2 adcrx notes 1. set using the sani3 to sani0 bits of the adscm00 or adscm10 register. be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to note 2. 2. set using the anis3 to anis0 of the adscm00 or adscm10 register. remark x = 00 to 05, 10 to 17 it is not necessary to write 1 in the adce0 or adce1 bit of the adscm00 or adscm10 register as an a/d conversion restart operation in a/d trigger polling mode note . this is optimal for applications that regularly read a/d conversion values. note in a/d trigger polling mode, the fact that the adce 0 or adce1 bit of the adscm00 or adscm10 register is 0 means that a/d conversion operation does not stop as long as the adcs0 or adcs1 bit is not 0. therefore, if the adcr0m or adcr1n r egister is not read before the next a/d conversion, it is overwritten. figure 11-9. example of scan mode (a/d tr igger polling scan) oper ation (ani02 to ani05): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adscm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) a/d conversion of ani02 (3) store conversion result in adcr02 (4) a/d conversion of ani03 (5) store conversion result in adcr03 (6) a/d conversion of ani04 (7) store conversion result in adcr04 (8) a/d conversion of ani05 (9) store conversion result in adcr05 (10) generate intad0 interrupt (11) return to (2)
chapter 11 a/d converter 537 user?s manual u15195ej5v0ud 11.9 operation in timer trigger mode a/d converters 0 and 1 have a total of 14 channels of a nalog inputs (ani00 to ani05 and ani10 to ani17). for these channels, an interrupt signal specified by a/d inter nal trigger selection registers 0 and 1 (itrg0, intrg1) can be set as a conversion trigger. the eight interrupt signals that can be selected as trigger s are the tm0n timer 0 register underflow interrupt signals (inttm00 and inttm01) and the cm003 to cm005 and cm013 to cm015 match interrupt signals (intcm003 to intcm005 and intcm013 to intcm015) (n = 0, 1). 11.9.1 operation in select mode taking the interrupt signal specified by a/d internal tri gger selection registers 0 and 1 (itrg0, itrg1) as a trigger, one analog input (ani00 to ani05, ani10 to ani17) s pecified by the adscm00 or adscm10 register is a/d converted once. the conversion result is stored in the adcr0m or adcr1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). the a/d conversion end interrupt (intad0 or intad1) is generated at the end of each a/d conversion, which terminates a/d conversion (adcs0, adcs1 = 0). this is optimal for applications that read a/d c onversion values synchronized to a timer trigger. trigger analog input a/d conversion result register interrupt specified by itrg0, itrg1 register anix adcrx remark n = 00 to 05, 10 to 17 after the end of a/d conversion, a/d converter 0 or 1 cha nges to the trigger wait status (adce0, adce1 = 1). a/d conversion is performed again when the interrupt signal sp ecified by the itrg0 or it rg1register is generated. figure 11-10. example of timer trigger select mode operation (ani04): for a/d converter 0 (a) when selecting inttm00 by itrg0, itrg1 register ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 inttm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) inttm00 interrupt generation (3) a/d conversion of ani04 (4) store conversion result in adcr04 (5) intad0 interrupt generation
chapter 11 a/d converter 538 user?s manual u15195ej5v0ud 11.9.2 operation in scan mode using the interrupt signal specified by a/d internal trigge r selection registers 0 and 1 (itrg0, itrg1) as a trigger, pins from the conversion start analog input pin to the co nversion termination analog input pin specified by the adscm00 or adscm10 register are sequentially selected and a/d converted. conversi on results are stored in the adcr0m or adcr1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). when all of the specified a/d conversions are complete, the a/d conversion end interrupt (intad0 or intad1) is generated, which terminates a/d conversion (adcs0, adcs1 = 0). this is optimal for applications that regularly monitor mu ltiple analog inputs in synchronization with a timer trigger. trigger analog input a/d conversion result register anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 ani16 adcr16 interrupt specified by itrg0, itrg1 register ani17 adcr17 remark n = 0, 1 after all of the specified a/d conver sions have ended, the a/d converter changes to the trigger wait status (adce0, adce1 = 1). a/d conversion is performed agai n when the interrupt signal specified by the itrg0 or itrg1 register is generated. figure 11-11. example of timer trigger scan mode operation (for a/d converter 0): inttm00 selected by itrg0, itrg1 register (a) set to scan ani01 to ani04 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 intm00 (1) adce0 bit of adscm00 = 1 (enabled) (2) inttm00 interrupt generation (3) a/d conversion of ani01 (4) store conversion result in adcr01 (5) a/d conversion of ani02 (6) store conversion result in adcr02 (7) a/d conversion of ani03 (8) store conversion result in adcr03 (9) a/d conversion of ani04 (10) store conversion result in adcr04 (11) intad0 interrupt generation
chapter 11 a/d converter 539 user?s manual u15195ej5v0ud 11.10 operation in external trigger mode in external trigger mode, an analog input (ani00 to ani05, ani10 to ani17) is a/d converted at the adtrg0 or adtrg1 pin input timing. the valid edge of an external input signal in external tr igger mode can be specified as the rising edge, falling edge, or both rising and falling edges using the es21 or es20 bit of the intm1 register for a/ d converter 0 and the es31 or es30 bit of the intm1 register for a/d converter 1. 11.10.1 operation in select mode one analog input (ani00 to ani05, an i10 to ani17) specified by the ad scm00 or adscm10 register is a/d converted. the conversion result is stored in the adcr0m or adcr1n register (m = 0 to 5, n = 0 to 7). using the adtrg0 or adtrg1 signal as a trigger, one analog input is a/d converted at a time and the result is stored in the adcr0m or adcr1n register. analog input s correspond one-to-one with a/d conversion result registers. for each a/d conversion, an a/d conversion end interrupt (intad0 or intad1) is generated, which terminates a/d conversion (adcs0, adcs1 bit = 0). trigger analog input a/d conversion result register adtrgm signal animn adcrmn remark m = 0, 1 n: 0 to 5 when m = 0, or 0 to 7 when m = 1 to restart a/d conversion, a trigger must be input again from the adtrgn pin (n = 0, 1). this is optimal for applications that read results each ti me there is an a/d conversion in synchronization with an external trigger. figure 11-12. example of select mode (external tr igger select) operation (ani02): for a/d converter 0 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adtrg0 (1) adce0 bit of adscm00 = 1 (enabled) (2) external trigger generation (3) a/d conversion of ani02 (4) store conversion result in adcr02 (5) intad0 interrupt generation
chapter 11 a/d converter 540 user?s manual u15195ej5v0ud 11.10.2 operation in scan mode using the adtrg0 or adtrg1 signal as a trigger, pins from the conversion start analog input pin to the conversion termination analog input pin specified by the adscm00 or adscm10 register are sequentially selected and a/d converted. a/d conversion results are stored in the adcr0m or adcrn1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7). when conversion ends for all of the specified analog inputs, an intad0 or intad1 interrupt is generated, which terminates a/d conversion (adcs0, adcs1 = 0). trigger analog input a/d conversion result register anin0 adcrn0 anin1 adcrn1 anin2 adcrn2 anin3 adcrn3 anin4 adcrn4 anin5 adcrn5 ani16 adcr16 adtrgn signal ani17 adcr17 remark n = 0, 1 after all specified a/d conversions have ended, a/d conversion is restarted when an external trigger signal occurs. this is optimal for applications that regularly monitor mult iple analog inputs in synchronization with an external trigger. figure 11-13. example of scan mode (external trigger scan) operation: for a/d converter 0 (a) when setting to scan ani01 to ani04 ani00 ani01 ani02 ani03 ani04 ani05 adcr00 adcr01 adcr02 adcr03 adcr04 adcr05 a/d converter 0 adtrg0 (1) adce0 bit of adscm00 = 1 (enabled) (2) external trigger generation (3) a/d conversion of ani01 (4) store conversion result in adcr01 (5) a/d conversion of ani02 (6) store conversion result in adcr02 (7) a/d conversion of ani03 (8) store conversion result in adcr03 (9) a/d conversion of ani04 (10) store conversion result in adcr04 (11) intad0 interrupt generation
chapter 11 a/d converter 541 user?s manual u15195ej5v0ud 11.11 operation cautions 11.11.1 stopping a/d conversion operation if 0 is written in the adce0 or adce1 bit of the adscm 00 or adscm10 register duri ng a/d conversion, it stops the a/d conversion operation and an a/d conv ersion result is not stored in the adcr0m or adcr1n register (m = 0 to 5, n = 0 to 7). 11.11.2 trigger input during a/d conversion operation if a trigger is input during a/d conver sion, that trigger input is ignored. 11.11.3 external or timer trigger interval make the trigger interval (input time interval) in external or timer trigger mode longer than the conversion time specified by the fr2 to fr0 bits of the adscm01 or adscm11 register. (1) when interval = 0 if multiple triggers are input simultaneously, processi ng is performed assuming that they are one trigger signal. (2) when 0 < interval < conversion time if an external or timer trigger is input during a/ d conversion, that trigger input is ignored. (3) when interval = conversion time if an external or timer trigger is input at the same time as the end of a/d conv ersion (conflict of compare termination signal and trigger), interrupt generation and storage of the value at which conversion ended in the adcr0m or adcr1n register is performed correctly (m = 0 to 5, n = 0 to 7). 11.11.4 operation in standby modes (1) halt mode a/d conversion is suspended. if released by nmi or maskable interrupt input, the adscm00, adscm10, adscm01, or adscm11 register and adcr0m or adcr1n r egister maintain their values (m = 0 to 5, n = 0 to 7). if released by reset input, the adcr0m and adcr1n registers are initialized. (2) idle mode, software stop mode since clock provision to a/d converter 0 or 1 stops, a/d conversion is not performed. if released by nmi or maskable interrupt input, the adscm00, adscm10, adscm 01, or adscm11 register and adcr0m or adcr1n register maintain their values (m = 0 to 5, n = 0 to 7). however, if idle mode or software stop mode is set during an a/d conversion operation, the a/d conversion operation stops. if released by reset input, the adcr0m and adcr1n registers are initialized. 11.11.5 compare match interrupt in timer trigger mode the tm0n timer 0 register underflow interrupt (inttm 00 or inttm01) and cm003 to cm005 or cm013 to cm015 match interrupt (intcm003 to intcm005 or intcm013 to intcm015) are a/d conversion start triggers that start a conversion operation (n = 0,1). at this time, the cm003 to cm005 or cm013 to cm015 match interrupt (intcm003 to intcm005 or intcm013 to intcm015) also functions as a co mpare register match interrupt for the cpu. in order not to generate these match interrupts for the cpu, disable interrupts usi ng the mask bits (tm0mk0, tm0mk1, cm03mk0 to cm05mk0, cm03mk1 to cm05mk1) of the interru pt control registers (tm0ic0, tm0ic1, cm03ic0 to cm05ic0, cm03ic1 to cm05ic1).
chapter 11 a/d converter 542 user?s manual u15195ej5v0ud 11.11.6 timing that makes the a/ d conversion result undefined if the timing of the end of a/d conversion and the timing of the stop of operation of the a/d converter conflict, the a/d conversion value may be undefined. because of this , be sure to read the a/d conversion result while the a/d converter is in operation. furthermore, when reading an a/d conversion result after the a/d converter operation has stopped, be sure to have done so by the ti me the next conversion result is complete. the conversion result read timing is shown in figures 11-14 and 11-15 below. figure 11-14. conversion result read timi ng (when conversion resu lt is undefined) a/d conversion end a/d conversion end adcrnm intadn adcen normal conversion result read normal conversion result undefined value a/d operation stopped undefined value read remark n = 0, 1 when n = 0: m = 0 to 5 when n = 1: m = 0 to 7 figure 11-15. conversion result read ti ming (when conversion result is normal) a/d conversion end adcrnm intadn adcen a/d operation stopped normal conversion result read normal conversion result remark n = 0, 1 when n = 0: m = 0 to 5 when n = 1: m = 0 to 7
chapter 11 a/d converter 543 user?s manual u15195ej5v0ud 11.12 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the per centage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always repr esented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av ddn ? 0)/100 = av ddn /100 remark n = 0, 1 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, linearity error, and e rrors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 11-16. overall error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ddn (n = 0, 1) 0
chapter 11 a/d converter 544 user?s manual u15195ej5v0ud (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is convert ed to the same digital code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 11-17. quan tization error 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ddn (n = 0, 1) (4) zero-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 11-18. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ddn (n = 0, 1) digital output (lower 3 bits) analog input (lsb) -1 100
chapter 11 a/d converter 545 user?s manual u15195ej5v0ud (5) full-scale error this shows the difference between the actual meas urement value of the analog input voltage and the theoretical value (3/2lsb) when the digital output changes from 1??110 to 1??111. figure 11-19. full-scale error 100 011 010 000 0 av ddn av ddn ?1 av ddn ?2 av ddn ?3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (n = 0, 1) (6) differential linearity error while the ideal width of code output is 1lsb, this in dicates the difference between the actual measurement value and the ideal value. figure 11-20. differential linearity error 0 av ddn (n = 0, 1) digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width
chapter 11 a/d converter 546 user?s manual u15195ej5v0ud (7) integral linearity error this shows the degree to which the conversion characteristics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 11-21. integral linearity error 0 av ddn (n = 0, 1) digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 (8) conversion time this expresses the time from when each trigger wa s generated to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 11-22. sampling time sampling time conversion time
547 user?s manual u15195ej5v0ud chapter 12 port functions 12.1 features input-only ports: 6 i/o ports: 47 ports function alternately as i/o pi ns of other peripheral functions input or output can be specified in bit units 12.2 basic configuration of ports the v850e/ia2 has a total of 53 on-chip i/o ports (ports 0 to 4, dh, dl, ct, cm), of which 6 are input-only ports. the port configuration is shown below. port dh p00 p05 p10 p12 p20 p27 p30 p34 p40 p42 pdh0 pdh5 pdl0 pdl15 pct0 pct1 pct4 pct6 pcm0 pcm1 port dl port ct port cm port 0 port 1 port 2 port 3 port 4 (1) functions of each port the v850e/ia2 has the ports shown below. any port can operate in 8-bit or 1-bit un its and can provide a variety of controls. moreover, besides its function as a port, each has functions as the i/o pins of on-chip peripheral i/o in control mode. refer to (3) port block diagrams for a block diagram of the block type of each port.
chapter 12 port functions 548 user?s manual u15195ej5v0ud port name pin name port function function in control mode block type port 0 p00 to p05 6-bit input nmi input timer/counter output stop signal input external interrupt input a/d converter (adc) external trigger input timer 3 output stop signal input e port 1 p10 to p12 3-bit i/o timer/counter i/o external interrupt input b, k port 2 p20 to p27 8-bit i/o timer/counter i/o external interrupt input b, k, l port 3 p30 to p34 5-bit i/o serial interfac e i/o (uart0, uart1/csi1) a, c, f, g, h port 4 p40 to p42 3-bit i/o serial interface i/o (csi0) a, c, j port dh pdh0 to pdh5 6-bit i/o external address bus (a16 to a21) n port dl pdl0 to pdl15 16-bit i/o external address/data bus (ad0 to ad15) m port ct pct0 pct1, pct4, pct6 4-bit i/o external bus interface control signal output i port cm pcm0, pcm1 2-bit i/o wait insertion signal input internal system clock output d, i cautions 1. when switching to the control mode, be sure to set ports that operate as output pins or i/o pins in the control mode using the following procedure. <1> set the inactive level for the signal outpu t in the control mode in the corresponding bits of port n (n = 0 to 4, cm, cs, ct, dh, and dl). <2> switch to the control mode using the port n mode control register (pmcn). if <1> above is not performed, the conten ts of port n may be output for a moment when switching from the port mode to the control mode. 2. when port manipulation is performed by a bit manipulation instruction (set1, clr1, or not1), perform byte data read for the port a nd process the data of only the bits to be manipulated, and write the byte data after conversion back to the port. for example, in ports in which input and output are mixed , because the contents of the output latch are overwritten to bits other than the bits for manipulation, the output latch of the input pin becomes undefined (in the input mode, however, the pin status does not change because the output buffer is off). therefore, when switching the port from input to output, set the output expected value to the corresponding bit, and then switch to the output port. this is the same as when the control mode and output port are mixed. 3. the state of the port pin can be read by se tting the port n mode register (pmn) to the input mode regardless of the settings of the pmcn register. when the pmn register is set to the output mode, the value of the port n register (p n) can be read in the port mode while the output state of the alternate function can be read in the control mode.
chapter 12 port functions 549 user?s manual u15195ej5v0ud (2) functions of each port pin after reset and registers that set port or control mode pin function after reset port name pin name single-chip mode romless mode mode-setting register p00/nmi p00 (input mode) p01/eso0/intp0 p01 (input mode) p02/eso1/intp1 p02 (input mode) p03/adtrg0/intp2 p03 (input mode) p04/adtrg1/intp3 p04 (input mode) port 0 p05/intp4/to3off p05 (input mode) ? p10/tiud10/to10 p10 (input mode) pmc1, pfc1 p11/tcud10/intp100 p11 (input mode) port 1 p12/tclr10/intp101 p12 (input mode) pmc1 p20/ti2/intp20 p20 (input mode) pmc2 p21/to21/intp21 p21 (input mode) p22/to22/intp22 p22 (input mode) p23/to23/intp23 p23 (input mode) p24/to24/intp24 p24 (input mode) pmc2, pfc2 p25/tclr2/intp25 p25 (input mode) p26/ti3/tclr3/intp30 p26 (input mode) pmc2 port 2 p27/to3/intp31 p27 (input mode) pmc2, pfc2 p30/rxd0 p30 (input mode) p31/txd0 p31 (input mode) p32/rxd1/si1 p32 (input mode) p33/txd1/so1 p33 (input mode) port 3 p34/asck1/sck1 p34 (input mode) pmc3 p40/si0 p40 (input mode) p41/so0 p41 (input mode) port 4 p42/sck0 p42 (input mode) pmc4 pcm0/wait pcm0 (input mode) wait port cm pcm1/clkout pcm1 (input mode) clkout pmccm pct0/lwr pct0 (input mode) lwr pct1/uwr pct1 (input mode) lwr pmcct pct4/rd pct4 (input mode) rd pmcct port ct pct6/astb pct6 (input mode) astb pmcct port dh pdh0/a16 to pdh5/a21 pdh0 to pdh5 (input mode) a16 to a21 pmcdh port dl pdl0/ad0 to pdl15/ad15 pdl0 to pdl7 (input mode) ad0 to ad15 pmcdl
chapter 12 port functions 550 user?s manual u15195ej5v0ud (3) port block diagrams figure 12-1. type a block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn output signal in control mode pmn address internal bus selector selector selector remark m: port number n: bit number
chapter 12 port functions 551 user?s manual u15195ej5v0ud figure 12-2. type b block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address noise elimination edge detection input signal in control mode internal bus selector selector remark m: port number n: bit number
chapter 12 port functions 552 user?s manual u15195ej5v0ud figure 12-3. type c block diagram wr pmc wr pm wr port rd in pmcmn pmmn pmn pmn address input signal in control mode internal bus selector selector remark m: port number n: bit number
chapter 12 port functions 553 user?s manual u15195ej5v0ud figure 12-4. type d block diagram wr pmc set/reset control of pmc address pmccm0 pmcm0 pcm0 pcm0 rd in input signal in control mode wr pm wr port selector internal bus selector
chapter 12 port functions 554 user?s manual u15195ej5v0ud figure 12-5. type e block diagram rd in pmn address noise elimination edge detection 1 input signal in control mode internal bus selector remark m: port number n: bit number figure 12-6. type f block diagram internal bus selector selector selector selector wr pfc wr pmc wr pm wr port pfc33 pmc33 pm33 p33 output signal in control mode rd in address p33
chapter 12 port functions 555 user?s manual u15195ej5v0ud figure 12-7. type g block diagram internal bus wr pfc wr pmc wr pm wr port pfc32 pmc32 pm32 p32 selector selector selector rd in address input signal in control mode note p32 note the signal level of the input signal is as follows in control mode. input signal in control mode pmc32 bit (pmc3 register) pfc32 bit (pfc3 register) rxd1 si1 0 h l 1 0 pin level l 1 1 h pin level h: high level l: low level : don?t care
chapter 12 port functions 556 user?s manual u15195ej5v0ud figure 12-8. type h block diagram internal bus pfc34 selector pmc34 pm34 p34 selector selector selector selector selector address rd in output signal 1 in control mode asck1 output enable signal sck1 output enable signal output signal 2 in control mode 1 1 1 wr pfc wr pmc wr pm wr port input signal in control mode note p34 note the signal level of the input signal is as follows in control mode. input signal in control mode pmc34 bit (pmc3 register) pfc34 bit (pfc3 register) asck1 sck1 0 l l 1 0 pin level l 1 1 l pin level h: high level l: low level : don?t care
chapter 12 port functions 557 user?s manual u15195ej5v0ud figure 12-9. type i block diagram wr pmc wr pm set/reset control of pmc pmcmn pmmn wr port pmn internal bus selector selector selector output signal in control mode rd in pmn 1 1 address remark m: port number n: bit number
chapter 12 port functions 558 user?s manual u15195ej5v0ud figure 12-10. type j block diagram wr pmc wr pm wr port rd in pmc42 pm42 p42 p42 address input signal in control mode output signal in control mode sck0 output enable signal internal bus selector selector selector
chapter 12 port functions 559 user?s manual u15195ej5v0ud figure 12-11. type k block diagram wr pfc wr pmc wr pm wr port rd in pfcmn pmcmn pmmn pmn pmn address input signal in control mode output signal in control mode internal bus selector selector selector noise elimination edge detection remark m: port number n: bit number
chapter 12 port functions 560 user?s manual u15195ej5v0ud figure 12-12. type l block diagram internal bus wr pfc pfc27 wr pmc pmc27 intp4 note to3sp wr pm pm27 wr port p27 noise elimination edge detection selector selector selector output signal in control mode input signal in control mode rd in address r q d p27 note output signal after an edge on the intp4 pin has been detected.
chapter 12 port functions 561 user?s manual u15195ej5v0ud figure 12-13. type m block diagram internal bus wr pmc pmcmn pstpoff boenx wr pm pmmn wr port pmn boenx boenx selector selector selector selector output signal in control mode input signal in control mode rd in address pmn set/reset control of pmc 1 1 1 remarks 1. m: port number n: bit number 2. x = 0, 1 3. pstpoff: signal in idle/software stop mode boenx: a/d output signal
chapter 12 port functions 562 user?s manual u15195ej5v0ud figure 12-14. type n block diagram wr pmc set/reset control of pmc wr pm wr port rd in pmcmn pmmn pmn pmn address 1 1 pstpoff output signal in control mode selector selector selector selector internal bus remarks 1. m: port number n: bit number 2. pstpoff: signal in idle/software stop mode
chapter 12 port functions 563 user?s manual u15195ej5v0ud 12.3 pin functions of each port 12.3.1 port 0 port 0 is a 6-bit input-only port in which all pins are fixed to input. 7 ? p0 6 ? 5 p05 4 p04 3 p03 2 p02 1 p01 0 p00 address fffff400h after reset undefined besides functioning as an input port, in control mode, it can also operate as the time r/counter output stop signal input, external interrupt request input, a/d converter (adc) external trigger input, and timer 3 output stop signal input. although this port is also used as nmi, eso0/intp 0, eso1/intp1, adtrg0/in tp2, adtrg1/intp3, and intp4/to3off, these functions cannot be switched with input port functions . the status of each pin is read by reading the port. (1) operation in control mode port alternate pin name remarks block type p00 nmi non-maskable interrupt request input p01 eso0/intp0 p02 eso1/intp1 timer/counter output stop signal input or external interrupt request input p03 adtrg0/intp2 p04 adtrg1/intp3 a/d converter (adc) external trigger input or external interrupt request input port 0 p05 intp4/to3off external interrupt request input/timer 3 output stop signal input e
chapter 12 port functions 564 user?s manual u15195ej5v0ud 12.3.2 port 1 port 1 is a 3-bit i/o port in which input or output can be specified in 1-bit units. 7 ? p1 6 ? 5 ? 4 ? 3 ? 2 p12 1 p11 0 p10 address fffff402h after reset undefined bit position bit name function 2 to 0 p1n (n = 2 to 0) i/o port besides functioning as a port, in control mode, it can al so operate as the timer/counter i/o and external interrupt request input. (1) operation in control mode port alternate pin name remarks block type p10 tiud10/to10 timer/counter i/o k p11 tcud10/intp100 port 1 p12 tclr10/intp101 timer/counter input or external interrupt request input b caution p10 to p12 have hyst eresis characteristics when the alternate functions ar e input, but not in the port mode. (2) setting of i/o mode and control mode the port 1 mode register (pm1) is used to set the i/o mode of port 1 and the por t 1 mode control register (pmc1) and port function control register 1 (pfc1) are used to set the operation in control mode. (a) port 1 mode register (pm1) this register can be read or written in 8-bit or 1-bit units. write 1 in bits 3 to 7. 7 1 pm1 6 1 5 1 4 1 3 1 2 pm12 1 pm11 0 pm10 address fffff422h after reset ffh bit position bit name function 2 to 0 pm1n (n = 2 to 0) specifies input/output mode of p1n pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 12 port functions 565 user?s manual u15195ej5v0ud (b) port 1 mode control register (pmc1) this register can be read or written in 8-bit or 1-bit units. write 0 in bits 3 to 7. caution the pmc11 and pmc12 bits are also us ed as external interrupts (intp100 and intp101). when not using them as external interrupts, mask interrupt requests (refer to 7.3.4 interrupt control registers (xxicn)). 7 0 pmc1 6 0 5 0 4 0 3 0 2 pmc12 1 pmc11 0 pmc10 address fffff442h after reset 00h bit position bit name function 2 pmc12 specifies operation mode of p12 pin. 0: i/o port mode 1: tclr10 input mode or external interrupt request (intp101) input mode 1 pmc11 specifies operation mode of p11 pin. 0: i/o port mode 1: tcud10 input mode or external interrupt request (intp100) input mode 0 pmc10 specifies operation mode of p10 pin. 0: i/o port mode 1: tiud10 input mode or to10 output mode (c) port 1 function control register (pfc1) this register can be read or written in 8-bit or 1-bit units. write 0 in bits other than 0. caution when port mode is specified by the port 1 mode control register (pmc1), the setting of this register is invalid. 7 0 pfc1 6 0 5 0 4 0 3 0 2 0 1 0 0 pfc10 address fffff462h after reset 00h bit position bit name function 0 pfc10 specifies operation mode of p10 pin in control mode. 0: tiud10 input mode 1: to10 output mode
chapter 12 port functions 566 user?s manual u15195ej5v0ud 12.3.3 port 2 port 2 is an 8-bit i/o port in which input or output can be specified in 1-bit units. 7 p27 p2 6 p26 5 p25 4 p24 3 p23 2 p22 1 p21 0 p20 address fffff404h after reset undefined bit position bit name function 7 to 0 p2n (n = 7 to 0) i/o port besides functioning as a port, in control mode, it also can operate as the timer/counter i/o and external interrupt request input. (1) operation in control mode port alternate pin name remarks block type p20 ti2/intp20 timer/counter input or external interrupt request input b p21 to 24 to21/intp21 to to24/intp24 timer/counter output or external interrupt request input k p25 tclr2/intp25 p26 ti3/tclr3/intp30 timer/counter input or external interrupt request input b port 2 p27 to3/intp31 timer/counter output or external interrupt request input l caution p20, p21, and p25 to p27 ha ve hysteresis characterist ics when the alternate functions are input, but not in the port mode. (2) setting of i/o mode and control mode the port 2 mode register (pm2) is used to set the i/o mode of port 2 and the por t 2 mode control register (pmc2) and port 2 function control register (pfc2) are used to set the operation in control mode. (a) port 2 mode register (pm2) this register can be read or written in 8-bit or 1-bit units. 7 pm27 pm2 6 pm26 5 pm25 4 pm24 3 pm23 2 pm22 1 pm21 0 pm20 address fffff424h after reset ffh bit position bit name function 7 to 0 pm2n (n = 7 to 0) specifies input/output mode of p2n pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 12 port functions 567 user?s manual u15195ej5v0ud (b) port 2 mode control register (pmc2) this register can be read or written in 8-bit or 1-bit units. caution the pmc20, pmc25, and pmc26 bits al so serve as external interrupts (intp20, intp25, and intp30). when not using them as ext ernal interrupts, mask interrupt requests (refer to 7.3.4 interrupt control registers (xxicn)). 7 pmc27 pmc2 6 pmc26 5 pmc25 4 pmc24 3 pmc23 2 pmc22 1 pmc21 0 pmc20 address fffff444h after reset 00h bit position bit name function 7 pmc27 specifies operation mode of p27 pin 0: i/o port mode 1: to3 output mode or external interrupt request (intp31) input mode 6 pmc26 specifies operation mode of p26 pin 0: i/o port mode 1: ti3 and tclr3 input mode or external interrupt request (intp30) input mode 5 pmc25 specifies operation mode of p25 pin 0: i/o port mode 1: tclr2 input mode or external interrupt request (intp25) input mode 4 to 1 pmc24 to pmc21 specify operation mode of p24 to p21 pins 0: i/o port mode 1: to24 to to21 output mode or external interrupt request (intp24 to intp21) input mode 0 pmc20 specifies operation mode of p20 pin 0: i/o port mode 1: ti2 input mode or external interrupt request (intp20) input mode (c) port 2 function control register (pfc2) this register can be read or written in 8-bit or 1-bit units. write 0 in bits 0, 5, and 6. caution when port mode is specified by the port 2 mode control register (pmc2), the setting of this register is invalid. 7 pfc27 pfc2 6 0 5 0 4 pfc24 3 pfc23 2 pfc22 1 pfc21 0 0 address fffff464h after reset 00h bit position bit name function 7 pfc27 specifies operation mode of p27 pin in control mode 0: external interrupt request (intp31) input mode 1: to3 output mode 4 to 1 pfc24 to pfc21 specify operation mode of p24 to p21 pins in control mode 0: external interrupt request (intp24 to intp21) input mode 1: to24 to to21 output mode
chapter 12 port functions 568 user?s manual u15195ej5v0ud 12.3.4 port 3 port 3 is a 5-bit i/o port in which input or output can be specified in 1-bit units 7 ? p3 6 ? 5 ? 4 p34 3 p33 2 p32 1 p31 0 p30 address fffff406h after reset undefined bit position bit name function 4 to 0 p3n (n = 4 to 0) i/o port besides functioning as a port, in control mode, it also can operate as the serial interface (uart0, uart1/csi1) i/o. (1) operation in control mode port alternate pin name remarks block type p30 rxd0 c p31 txd0 a p32 rxd1/si1 g p33 txd1/so1 f port 3 p34 asck1/sck1 serial interface (uart0, uart1/csi1) i/o h caution p30, p32, and p34 have hyst eresis characteristics when the alternate functions are input, but not in the port mode. (2) setting of i/o mode and control mode the port 3 mode register (pm3) is used to set the i/o mode of port 3 and the por t 3 mode control register (pmc3) and the port 3 function control register (pfc 3) are used to set the operation in control mode. (a) port 3 mode register (pm3) this register can be read or written in 8-bit or 1-bit units. 7 1 pm3 6 1 5 1 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 address fffff426h after reset ffh bit position bit name function 4 to 0 pm3n (n = 4 to 0) specifies input/output mode of p3n pin. 0: output mode (output buffer on) 1: input mode (output buffer off)
chapter 12 port functions 569 user?s manual u15195ej5v0ud (b) port 3 mode control register (pmc3) this register can be read or written in 8-bit or 1-bit units. 7 0 pmc3 6 0 5 0 4 pmc34 3 pmc33 2 pmc32 1 pmc31 0 pmc30 address fffff446h after reset 00h bit position bit name function 4 pmc34 specifies operation mode of p34 pin 0: i/o port mode 1: asck1/sck1 i/o mode 3 pmc33 specifies operation mode of p33 pin 0: i/o port mode 1: txd1/so1 output mode 2 pmc32 specifies operation mode of p32 pin 0: i/o port mode 1: rxd1/si1 input mode 1 pmc31 specifies operation mode of p31 pin 0: i/o port mode 1: txd0 output mode 0 pmc30 specifies operation mode of p30 pin 0: i/o port mode 1: rxd0 input mode (c) port 3 function control register (pfc3) this register can be read or written in 8-bit or 1- bit units. write 0 in bits other than 2 to 4. caution when port mode is specified by the port 3 mode control register (pmc3), the setting of this register is invalid. 7 0 pfc3 6 0 5 0 4 pfc34 3 pfc33 2 pfc32 1 0 0 0 address fffff466h after reset 00h bit position bit name function 4 pfc34 specifies operation mode of p34 pin in control mode 0: asck1 i/o mode 1: sck1 i/o mode 3 pfc33 specifies operation mode of p33 pin in control mode 0: txd1 output mode 1: so1 output mode 2 pfc32 specifies operation mode of p32 pin in control mode 0: rxd1 input mode 1: si1 input mode
chapter 12 port functions 570 user?s manual u15195ej5v0ud 12.3.5 port 4 port 4 is a 3-bit i/o port in which input or output can be specified in 1-bit units. 7 ? p4 6 ? 5 ? 4 ? 3 ? 2 p42 1 p41 0 p40 address fffff408h after reset undefined bit position bit name function 2 to 0 p4n (n = 2 to 0) i/o port besides functioning as a port, in control mode, it al so can operate as the serial interface (csi0) i/o. (1) operation in control mode port alternate pin name remarks block type p40 si0 c p41 so0 a port 4 p42 sck0 serial interface (csi0) i/o j caution p40 and p42 have hysteresis characteristics when the alternate functions are input, but not in the port mode.
chapter 12 port functions 571 user?s manual u15195ej5v0ud (2) setting of i/o mode and control mode the port 4 mode register (pm4) is used to set the i/o mode of port 4 and the por t 4 mode control register (pmc4) is used to set the operation in control mode. (a) port 4 mode register (pm4) this register can be read or written in 8-bit or 1-bit units. 7 1 pm4 6 1 5 1 4 1 3 1 2 pm42 1 pm41 0 pm40 address fffff428h after reset ffh bit position bit name function 2 to 0 pm4n (n = 2 to 0) specifies input/output mode of p4n pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port 4 mode control register (pmc4) this register can be read or written in 8-bit or 1-bit units. 7 0 pmc4 6 0 5 0 4 0 3 0 2 pmc42 1 pmc41 0 pmc40 address fffff448h after reset 00h bit position bit name function 2 pmc42 specifies operation mode of p42 pin 0: i/o port mode 1: sck0 i/o mode 1 pmc41 specifies operation mode of p41 pin 0: i/o port mode 1: so0 output mode 0 pmc40 specifies operation mode of p40 pin 0: i/o port mode 1: si0 input mode
chapter 12 port functions 572 user?s manual u15195ej5v0ud 12.3.6 port dh port dh is a 6-bit i/o port in which input or output can be spec ified in 1-bit units. 7 ? pdh 6 ? 5 pdh5 4 pdh4 3 pdh3 2 pdh2 1 pdh1 0 pdh0 address fffff006h after reset undefined bit position bit name function 5 to 0 pdhn (n = 5 to 0) i/o port besides functioning as a port, in c ontrol mode, this can operate as an address bu s when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type port dh pdh5 to pdh0 a21 to a16 memory expansion address bus n
chapter 12 port functions 573 user?s manual u15195ej5v0ud (2) setting of i/o mode and control mode the port dh mode register (pmdh) is used to set the i/o mode of port dh and the port dh mode control register (pmcdh) is used to se t the operation in control mode. (a) port dh mode register (pmdh) this register can be read or written in 8-bit or 1-bit units. 7 1 pmdh 6 1 5 pmdh5 4 pmdh4 3 pmdh3 2 pmdh2 1 pmdh1 0 pmdh0 address fffff026h after reset ffh bit position bit name function 5 to 0 pmdhn (n = 5 to 0) specifies input/output mode of pdhn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port dh mode control register (pmcdh) this register can be read or written in 8-bit or 1-bit units. caution set bits 7 and 6 as follows. operation mode bit 7 bit 6 single-chip mode 0 0 romless mode 1 1 7 pmcdh7 pmcdh 6 pmcdh6 5 pmcdh5 4 pmcdh4 3 pmcdh3 2 pmcdh2 1 pmcdh1 0 pmcdh0 address fffff046h after reset note 00h/ffh note 00h: single-chip mode ffh: romless mode bit position bit name function 5 to 0 pmcdhn (n = 5 to 0) specifies operation mode of pdhn pin 0: i/o port mode 1: a21 to a16 output mode
chapter 12 port functions 574 user?s manual u15195ej5v0ud 12.3.7 port dl port dl is a 16-bit i/o port in which inpu t or output can be spec ified in 1-bit units. when using the higher 8 bits of pdl as pdlh and the lower 8 bits as pdll, it can be used as an 8-bit i/o port that can specify input/output in 1-bit units. 15 pdl15 pdl 14 pdl14 13 pdl13 12 pdl12 11 pdl11 10 pdl10 9 pdl9 8 pdl8 7 pdl7 6 pdl6 5 pdl5 4 pdl4 3 pdl3 2 pdl2 1 pdl1 0 pdl0 address fffff005h after reset undefined address fffff004h bit position bit name function 15 to 0 pdln (n = 15 to 0) i/o port besides functioning as a port, in control mode, this c an operate as an address/data bus when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type port dl pdl15 to pdl0 ad15 to ad0 memory expansion address/data bus m
chapter 12 port functions 575 user?s manual u15195ej5v0ud (2) setting of i/o mode and control mode the port dl mode register (pmdl) is used to set the i/o mode of port dl and the port dl mode control register (pmcdl) is used to set the operation in control mode. (a) port dl mode register (pmdl) the pmdl register can be read or written in 16-bit units. when using the higher 8 bits of t he pmdl register as the pmdlh regi ster and the lower 8 bits as the pmdll register, it can be read or written in 8-bit or 1-bit units. 15 pmdl15 pmdl 14 pmdl14 13 pmdl13 12 pmdl12 11 pmdl11 10 pmdl10 9 pmdl9 8 pmdl8 7 pmdl7 6 pmdl6 5 pmdl5 4 pmdl4 3 pmdl3 2 pmdl2 1 pmdl1 0 pmdl0 address fffff025h after reset ffffh address fffff024h bit position bit name function 15 to 0 pmdln (n = 15 to 0) specifies input/output mode of pdln pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port dl mode control register (pmcdl) the pmcdl register can be read or written in 16-bit units. when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, it can be read or written in 8-bit or 1-bit units. 15 pmcdl15 pmcdl 14 pmcdl14 13 pmcdl13 12 pmcdl12 11 pmcdl11 10 pmcdl10 9 pmcdl9 8 pmcdl8 7 pmcdl7 6 pmcdl6 5 pmcdl5 4 pmcdl4 3 pmcdl3 2 pmcdl2 1 pmcdl1 0 pmcdl0 address fffff045h after reset note 0000h/ffffh address fffff044h note 0000h : single-chip mode ffffh : romless mode bit position bit name function 15 to 0 pmcdln (n = 15 to 0) specifies operation mode of pdln pin. 0: i/o port mode 1: ad15 to ad0 i/o mode
chapter 12 port functions 576 user?s manual u15195ej5v0ud 12.3.8 port ct port ct is a 4-bit i/o port in which input or output can be spec ified in 1-bit units. 7 ? pct 6 pct6 5 ? 4 pct4 3 ? 2 ? 1 pct1 0 pct0 address fffff00ah after reset undefined bit position bit name function 6, 4, 1, 0 pctn (n = 6, 4, 1, 0) i/o port besides functioning as a port, in control mode, this can operate as control signal outputs when memory is expanded externally. (1) operation in control mode port alternate pin name remarks block type pct0 lwr pct1 uwr write strobe signal output pct4 rd read strobe signal output port ct pct6 astb address strobe signal output i
chapter 12 port functions 577 user?s manual u15195ej5v0ud (2) setting of i/o mode and control mode the port ct mode register (pmct) is used to se t the i/o mode of port ct and the port ct mode control register (pmcct) is used to se t the operation in control mode. (a) port ct mode register (pmct) this register can be read or written in 8-bit or 1-bit units. 7 1 pmct 6 pmct6 5 1 4 pmct4 3 1 2 1 1 pmct1 0 pmct0 address fffff02ah after reset ffh bit position bit name function 6, 4, 1, 0 pmctn (n = 6, 4, 1, 0) specifies input/output mode of pctn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port ct mode control register (pmcct) this register can be read or written in 8-bit or 1-bit units. 7 0 pmcct 6 pmcct6 5 0 4 pmcct4 3 0 2 0 1 pmcct1 0 pmcct0 address fffff04ah after reset note 00h/53h note 00h: single-chip mode 53h: romless mode bit position bit name function 6 pmcct6 specifies operation mode of pct6 pin 0: i/o port mode 1: astb output mode 4 pmcct4 specifies operation mode of pct4 pin 0: i/o port mode 1: rd output mode 1 pmcct1 specifies operation mode of pct1 pin 0: i/o port mode 1: uwr output mode 0 pmcct0 specifies operation mode of pct0 pin 0: i/o port mode 1: lwr output mode
chapter 12 port functions 578 user?s manual u15195ej5v0ud 12.3.9 port cm port cm is a 2-bit i/o port in which input or output can be spec ified in 1-bit units. 7 ? pcm 6 ? 5 ? 4 ? 3 ? 2 ? 1 pcm1 0 pcm0 address fffff00ch after reset undefined bit position bit name function 1, 0 pcmn (n = 1, 0) i/o port besides functioning as a port, in control mode, this can operate as the wait insertion signal input and internal system clock output. (1) operation in control mode port alternate pin name remarks block type pcm0 wait note wait insertion signal input d port cm pcm1 clkout internal system clock output i note in the romless mode, the default op eration mode of the pcm0 pin is the wait input mode. when unused, fix the pin to the inactive level. when used as a port, this pin functions in the contro l mode until the port mode is set using the port cm mode control register (pmccm). set this pin to the inactive level during this period.
chapter 12 port functions 579 user?s manual u15195ej5v0ud (2) setting of i/o mode and control mode the port cm mode register (pmcm) is used to set the i/o mode of port cm and the cm mode control register (pmccm) is used to set the operation in control mode. (a) port cm mode register (pmcm) this register can be read or written in 8-bit or 1-bit units. 7 1 pmcm 6 1 5 1 4 1 3 1 2 1 1 pmcm1 0 pmcm0 address fffff02ch after reset ffh bit position bit name function 1, 0 pmcmn (n = 1, 0) specifies input/output mode of pcmn pin. 0: output mode (output buffer on) 1: input mode (output buffer off) (b) port cm mode control register (pmccm) this register can be read or written in 8-bit or 1-bit units. 7 0 pmccm 6 0 5 0 4 0 3 0 2 0 1 pmccm1 0 pmccm0 address fffff04ch after reset note 00h/03h note 00h: single-chip mode 03h: romless mode bit position bit name function 1 pmccm1 specifies operation mode of pcm1 pin 0: i/o port mode 1: clkout output mode 0 pmccm0 specifies operation mode of pcm0 pin 0: i/o port mode 1: wait input mode
chapter 12 port functions 580 user?s manual u15195ej5v0ud 12.4 operation of port function the operation of a port differs depending on whether it is set in the input or output mode, as follows. 12.4.1 writing to i/o port (1) in output mode a value can be written to the output latch (pn) by writi ng it to the port n register (pn). the contents of the output latch are output from the pin. once data is written to the output latch, it is hel d until new data is written to the output latch. (2) in input mode a value can be written to the output latch (pn) by writing it to the port n regi ster (pn). however, the status of the pin does not change because the output buffer is off. once data is written to the output latch, it is hel d until new data is written to the output latch. caution a bit manipulation instruction (clr1, set 1, not1) manipulates 1 bit but accesses a port in 8-bit units. if this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, ar e overwritten to the current input pin status and become undefined. 12.4.2 reading from i/o port (1) in output mode the contents of the output latch (pn) can be read by reading the port n register (pn). the contents of the output latch do not change. (2) in input mode the status of the pin can be read by re ading the port n register (pn). t he contents of the output latch (pn) do not change. 12.4.3 output status of alternate function in control mode the status of a port pin can be read by setting the port n mode register (pmn) to the input mode regardless of the setting of the pmcn register. if the pmn register is set to the output mode, the value of t he port n register (pn) can be read in the port mode, and t he output status of the al ternate function can be read in the control mode.
chapter 12 port functions 581 user?s manual u15195ej5v0ud 12.5 noise eliminator 12.5.1 interrupt pins a timing controller to guarantee the noise elimination time shown below is added to the pins that operate as nmi and valid edge inputs in port control mode. a signal input that changes in less than this elimination time is not accepted internally. pin noise elimination time p00/nmi p01/eso0/intp0, p02/eso1/intp1 p03/adtrg0/intp2, p04/adtrg1/intp3 p05/intp4/to3off analog delay (several 10 ns) cautions 1. the above non-maskable/m askable interrupt pins are used to release standby mode. a clock control timing circuit is not used since the internal system clock is stopped in standby mode. 2. the noise eliminator is valid only in control mode. 12.5.2 timer 10, timer 3 input pins noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10 and timer 3. a signal input that changes in less t han these elimination times is not accepted internally. pin noise elimination time sampling clock timer 10 p10/tiud10/to10 p11/tcud10/intp100 p12/tclr10/intp101 select from f xxtm10 f xxtm10 /2 f xxtm10 /4 f xxtm10 /8 p26/ti3/intp30/tclr3 select from f xxtm3 /2 f xxtm3 /4 f xxtm3 /8 f xxtm3 /16 timer 3 p27/to3/intp31 4 to 5 clocks select from f xxtm3 /32 f xxtm3 /64 f xxtm3 /128 f xxtm3 /256 cautions 1. since the above pin no ise filtering uses clock sampling, in put signals are not received when the cpu clock is stopped. 2. the noise eliminator is valid only in control mode. remark f xxtm10 : clock of tm10 selected in prm02 register (be sure to set prm02 = 01h) f xxtm3 : clock of tm3 selected in prm03 register
chapter 12 port functions 582 user?s manual u15195ej5v0ud figure 12-15. example of noise elimination timing noise elimination clock input signal internal signal timers 1, 2, 3 rising edge detection timers 1, 2, 3 falling edge detection 2 clocks 2 clocks 5 clocks 5 clocks 4 clocks 4 clocks 3 clocks 3 clocks caution if there are three or less noise elimination clocks while the ti mer 1 or 3 input signal is high level (or low level), the input pulse is eliminated as noise. if it is sampled at least four times, the edge is detected as valid input.
chapter 12 port functions 583 user?s manual u15195ej5v0ud (1) timer 10 noise elimination ti me selection register (nrc10) the nrc10 register is used to set the clock sour ce of timer 10 input pin noise elimination time. it can be read or written in 8-bit or 1-bit units. caution the noise elimination function starts oper ating by setting the tm1ce0 bit of the tmc10 register to 1 (enab ling count operations). 7 0 nrc10 6 0 5 0 4 0 3 0 2 0 1 nrc101 0 nrc100 address fffff5f8h after reset 00h bit position bit name function selects the tiud10/to10, tcud10/intp100, and tclr10/intp101 pin noise elimination clocks. nrc101 nrc100 noise elimination clocks 0 0 f xxtm10 /8 0 1 f xxtm10 /4 1 0 f xxtm10 /2 1 1 f xxtm10 1, 0 nrc101, nrc100 remark f xxtm10 : clock of tm10 selected by prm02 register (be sure to set prm02 = 01h)
chapter 12 port functions 584 user?s manual u15195ej5v0ud (2) timer 3 noise elimination ti me selection register (nrc3) the nrc3 register is used to set the clock source of the timer 3 input pin noise elimination time. it can be read or written in 8-bit or 1-bit units. caution the noise elimination function starts oper ating by setting the tm3ce0 bit of the tmc30 register to 1 (enab ling count operations). 7 0 nrc3 6 0 5 0 4 0 3 nrc33 2 nrc32 1 nrc31 0 nrc30 address fffff698h after reset 00h bit position bit name function selects the to3/intp31 pin noise elimination clock. nrc33 nrc32 noise elimination clock 0 0 f xxtm3 /256 0 1 f xxtm3 /128 1 0 f xxtm3 /64 1 1 f xxtm3 /32 3, 2 nrc33, nrc32 remark f xxtm3 : clock of tm3 selected by prm03 register selects the ti3/intp30/tclr3 pin noise elimination clock. nrc31 nrc30 noise elimination clocks 0 0 f xxtm3 /16 0 1 f xxtm3 /8 1 0 f xxtm3 /4 1 1 f xxtm3 /2 1, 0 nrc31, nrc30 remark f xxtm3 : clock of tm3 selected by prm03 register
chapter 12 port functions 585 user?s manual u15195ej5v0ud 12.5.3 timer 2 input pins a noise eliminator using analog filtering and digital filt ering using clock sampling are added to the timer 2 input pins. a signal input that changes in less than th is elimination time is not accepted internally. digital filter pin analog filter noise elimination time noise elimination time sampling clock p20/ti2/intp20 p21/to21/intp21 to p24/to24/intp24 p25/tclr2/intp25 10 to 100 ns 4 to 5 clocks f xxtm2 cautions 1. since digital filteri ng uses clock sampling, if it is sel ected, input signals are not received when the cpu clock is stopped. 2. the noise eliminator is valid only in control mode. 3. refer to figure 12-15 for an example of a noise eliminator. remark f xxtm2 : clock of tm20 and tm21 selected in prm02 register (be sure to set prm02 = 01h)
chapter 12 port functions 586 user?s manual u15195ej5v0ud (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) the femn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination time and the input valid edge. it can be read or written in 8-bit or 1-bit units. cautions 1. be sure to clear (0) the stfte bit of timer 2 clock stop regist er 0 (stopte0) even when using the ti2/intp20, to21/intp21, to22 /intp22, to23/intp23, to24/intp24, and tclr2/intp25 pins as intp20, intp21, intp22, intp23, intp24, and intp25, respectively, and not using timer 2. 2. setting the trigger mode of the intp2n pin should be performed after setting the pmc2 register. if the pmc2 register is set after setting th e femn register, an invalid interrupt may occur when the pmc2 register is set (n = 0 to 5). 3. the noise elimination function starts ope rating by setting the c een bit of the tcre0 register to 1 (enab ling count operations). (1/2) 7 dfen00 fem0 6 0 5 0 4 0 3 edge010 2 edge000 1 tms010 0 tms000 address fffff630h after reset 00h address fffff631h after reset 00h address fffff632h after reset 00h address fffff633h after reset 00h address fffff634h after reset 00h address fffff635h after reset 00h intp20 7 dfen01 6 0 5 0 4 0 3 edge011 2 edge001 1 tms011 0 tms001 intp21 7 dfen02 6 0 5 0 4 0 3 edge012 2 edge002 1 tms012 0 tms002 intp22 7 dfen03 6 0 5 0 4 0 3 edge013 2 edge003 1 tms013 0 tms003 intp23 7 dfen04 6 0 5 0 4 0 3 edge014 2 edge004 1 tms014 0 tms004 intp24 7 dfen05 6 0 5 0 4 0 3 edge015 2 edge005 1 tms015 0 tms005 intp25 fem1 fem2 fem3 fem4 fem5 bit position bit name function 7 dfen0n specifies the intp2n pin filter. 0: analog filter 1: digital filter caution when the dfen0n bit = 1, the sampling clock of the digital filter is f xxtm2 (clock selected by the prm02 register). remark n = 0 to 5
chapter 12 port functions 587 user?s manual u15195ej5v0ud (2/2) bit position bit name function specifies the intp2n pin valid edge. edge01n ege00n operation 0 0 interrupt due to intcc2n note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges 3, 2 edge01n, edge00n note specify when selecting intcc2n according to a match of tm20, tm21 and the subchannel compare registers (tms01n, tm s00n bit settings) (n = 0 to 5). selects capture input note . tms01n tms00n operation 0 0 used as pin 0 1 digital filter (noise eliminator specification) 1 0 capture to subchannel 1 according to timer 1 1 capture to subchannel 2 according to timer 1, 0 tms01n, tms00n note capture input according to intcm100 and intcm101 can be selected only for the fem1 and fem2 registers. set the values of the tms01m and tms00m bits in the femm register to 00b or 01b. se ttings other than these are prohibited (m = 1, 3 to 5). capture according to intp21, intp22 and intcm100, intcm101 is possible for subchannel 1 and subchannel 2 of timer 2. examples are shown below. (a) capture subchannel 1 on intcm101 fem1 register = xxxxxx10b tmic0 register = 00000010b (b) capture subchannel 2 on intcm101 fem2 register = xxxxxx11b tmic0 register = 00001000b remark n = 0 to 5
chapter 12 port functions 588 user?s manual u15195ej5v0ud 12.6 cautions 12.6.1 hysteresis characteristics the following ports do not have hysteresis characteristics in the port mode. p10 to p12 p20, p21, p25 to p27 p30, p32, p34 p40, p42
589 user?s manual u15195ej5v0ud chapter 13 reset function when a low level is input to the reset pin, the system is reset and each hardware item of the v850e/ia2 is initialized to its initial status. when the reset pin changes from low level to high level, t he reset status is released and the cpu starts program execution. initialize the contents of va rious registers as needed within the program. 13.1 features noise elimination using analog delay (approx. 60 ns) at reset pin (reset) 13.2 pin functions during a system reset period, most pin output is high impedance (all pins except clkout note , reset, x2, v dd , v ss , v ss3 , cv ss , rv dd , regout, regin, av dd0 , av dd1 , av ss0 , and av ss1 pins). thus, if memory is extended externally, a pull-up (or pull- down) resistor must be attached to each pin of ports dh, dl, ct, and cm. if there are no resistors, the external me mory that is connected may be destroyed when these pins become high impedance. similarly, perform pin processing so that on-chip perip heral i/o function signal outputs and output ports are not affected. note in romless mode, clkout signals ar e also output during a reset period. in single-chip mode, clkout signals are not output until the pmccm register is set. table 13-1 shows the operation status of each pin during a reset period. table 13-1. operation status of each pin during reset period pin status pin name in single-chip mode in romless mode a16 to a21, ad0 to ad15, lwr, uwr, rd, astb, wait high impedance (input port mode) high impedance external access pin clkout high impedance (input port mode) operation port 0 to 4 high impedance (input port mode) port pin note ports cm, ct, dh, dl high impedance (input port mode) refer to the description of the external access pin. (control mode) to0n0 to to0n5 (pins dedicated to timer 0 output) high impedance dedicated function pin ani00 to ani05, ani10 to ani17 (pins dedicated to a/d converter input) high impedance (a/d converter input) note the names of the control pi ns that function alternately as port pins are omitted. remark n = 0, 1
chapter 13 reset function 590 user?s manual u15195ej5v0ud (1) reset signal acknowledgment reset internal system reset signal elimination as noise reset acknowledgment reset release analog delay analog delay analog delay note note the internal system reset signal re mains active for a period of at least 4 system clocks after the timing of a reset release by the reset pin. (2) reset at power-on <1> reset circuit reset 5 v 5 v 5 v 5 v reset generator regulator control (regres5) pin high-impedance control (res5) internal circuit control (res3) 3.3 v reset generator 3.3 v 3.3 v note note apply 5 v initially. if 5 v is not applied initially, th is level cannot be determined, and a reset will not occur. caution apply power in the following sequence. <1> 5 v power supply <2> 3.3 v power supply
chapter 13 reset function 591 user?s manual u15195ej5v0ud <2> reset timing v dd (5 v) regin (3.3 v) reset (input) internal regres5 (5 v) internal res5 (5 v) internal res3 (3.3 v) undefined active low active low active high active high oscillation stabilization time reset release analog delay note undefined undefined regulator output stabilization time note the internal system reset signal st ays active for at least 4 system clo cks after the reset status caused by the reset pin is released. <3> description a reset operation at power-on (power supply app lication) must guarantee ?r egulator output stabilization time + oscillation stabilization time? from power-on un til reset acknowledgment due to the low level width of the reset signal. cautions 1. the v850e/ia2 has an internal regul ator that generates 3.3 v from a 5 v system power supply. therefore, 3.3 v system pow er is supplied after the lapse of the regulator output stabilization time after 5 v power was supplied. when supplying the two power supplies from external supplies with the regulator turned off, be sure to supply 5 v system power first. 2. the v850e/ia2 is internally reset afte r 3.3 v system power h as been supplied. during the regulator output stabilization time , the internal circuits may not be reset when only 5 v system power is being supp lied. consequently, the pins may output undefined levels. for this reason, the v 850e/ia2 makes the pins listed in (a) below that may affect the application system (mainl y the i/o pins of the internal timers) go into a high-impedance state (r efer to (b) and (c) below). note that pins other than those to be controlled do not go into a high-impedance state unless supplied with 3.3 v system power. the pins listed in (a) m ay also output undefined levels until a 5 v reset (internal res5) occurs (after the power was supplie d until vdd reaches approximately 1.8 v (reference value)) if the 5 v system power supply is gradually stabilized. the undefined level output time de pends on how rapidly the power supply is stabilized. attention must be paid when the system requires several tens of ms for the 5 v system power to stabilize.
chapter 13 reset function 592 user?s manual u15195ej5v0ud (a) pins to be controlled to000 to to005, to010 to to015, p10/ to10/tiud10, p11/intp100/tcud10, p12/intp101/tclr10, p20/intp20/ti2, p21/intp21/to21, p22/intp22/to22, p23/intp23/to23, p24/intp24/to24, p25 /intp25/tclr2, p26/tclr3/intp30/ti3, p27/intp31/to3 (b) circuit of above pins output buffer i/o control signal of pin 5 v system reset (res5) 1: reset output buffer enable signal 0: output buffer off 1: output buffer on (at 3.3 v system reset) v dd v dd pin to be controlled level shifter (c) internal reset of 5 v system /3.3 v system power supply (i) operation on turning on/off power v dd (5 v system) regin (3.3 v system) reset (input) internal res5 (5 v system) internal res3 (3.3 v system) pin to be controlled analog delay high impedance pin manipulation instruction low level because power is off controlled by external reset ic low level because power is off operates note note the internal system reset signal stays active for at least 4 system clocks after the reset status caused by the reset pin is released.
chapter 13 reset function 593 user?s manual u15195ej5v0ud (ii) reset during normal operation v dd (5 v system) regin (3.3 v system) reset (input) internal res5 (5 v system) internal res3 (3.3 v system) pin to be controlled high impedance operates operates pin manipulation instruction note 1 note 1 note 2 note 1 h h notes 1. analog delay 2. the internal system reset signal stays active for at least 4 system clocks after the reset status caused by the reset pin is released.
chapter 13 reset function 594 user?s manual u15195ej5v0ud 13.3 initialization initialize the contents of each regi ster as needed within the program. table 13-2 shows the initial val ues of the cpu, internal ram, and on-chip peripheral i/o after reset. table 13-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (1/5) on-chip hardware register name initial value after reset general-purpose register (r0) 00000000h general-purpose registers (r1 to r31) undefined program registers program counter (pc) 00000000h status save registers during interrupt (eipc, eipsw) undefined status save registers during nmi (fepc, fepsw) undefined interrupt cause register (ecr) 00000000h program status word (psw) 00000020h status save registers during callt execution (ctpc, ctpsw) undefined status save registers during exception/debug trap (dbpc, dbpsw) undefined cpu system registers callt base pointer (ctbp) undefined internal ram ? undefined chip area selection control register n (cscn) (n = 0, 1) 2c11h bus size configurat ion register (bsc) 5555h bus control function system wait control register (vswc) 77h bus cycle type configuration r egister n (bctn) (n = 0,1) cccch data wait control register n (dwcn) (n = 0,1) 3333h address wait control register (awc) 0000h memory control function bus cycle control register (bcc) aaaah dma source address register nl (dsanl) (n = 0 to 3) undefined dma source address register nh (dsanh) (n = 0 to 3) undefined dma destination address register nl (ddanl) (n = 0 to 3) undefined dma destination address register nh (ddanh) (n = 0 to 3) undefined dma transfer count register n (dbcn) (n = 0 to 3) undefined dma addressing control register n (dadcn) (n = 0 to 3) 0000h dma channel control register n (dchcn) (n = 0 to 3) 00h dma disable status register (ddis) 00h dma restart register (drst) 00h dma function dma trigger source register n (dtfrn) (n = 0 to 3) 00h in service priority register (ispr) 00h external interrupt mode register n (intmn) (n = 0 to 2) 00h interrupt mask register n (imrn) (n = 0 to 3) ffffh interrupt mask register nl (imrnl) (n = 0 to 3) ffh interrupt mask register nh (imrnh) (n = 0 to 3) ffh on-chip peripheral i/o interrupt/ exception control function signal edge selection register 10 (sesa10) 00h
chapter 13 reset function 595 user?s manual u15195ej5v0ud table 13-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (2/5) on-chip hardware register name initial value after reset valid edge selection register (sesc) 00h timer 2 input filter mode register n (femn) (n = 0 to 5) 00h interrupt/ exception control function interrupt control registers (p0ic0 to p0ic4, detic0, detic1, tm0ic0, tm0ic1, tm2ic0, tm2ic1, tm3ic0, cc10ic0, cc10ic1, cc2ic0 to cc2ic5, cc3ic0, cc3ic1, cm00ic1, cm01ic1, cm02ic1, cm03ic0, cm03ic1, cm04ic0, cm04ic1, cm05ic0, cm05ic1, cm10ic0, cm10ic1, cm4ic0, dmaic0 to dmaic3, csiic0, csiic1, seic0, sric0, sric1, stic0, stic1, adic0, adic1) 47h command register (prcmd) undefined power save control register (psc) 00h clock control register (ckc) 00h power save mode register (psmr) 00h power save control function lock register (lockr) 0000000xb peripheral command register (phcmd) undefined system control peripheral status register (phs) 00h dead time timer reload register n (dtrrn) (n = 0,1) 0fffh buffer registers cm0n, cm1n (bfcm0n, bfcm1n) (n = 0 to 5) ffffh timer control register 0n (tmc0n) (n = 0,1) 0508h timer control register 0nl (tmc0nl) (n = 0, 1) 08h timer control register 0nh (tmc0nh) (n = 0, 1) 05h timer unit control register 0n (tuc0n) (n = 0,1) 01h timer output mode register n (tomrn) (n = 0,1) 00h pwm software timing output register n (pston) (n = 0,1) 00h pwm output enable register n (poern) (n = 0,1) 00h tomr write enable register n (specn) (n = 0,1) 0000h timer 0 timer 0 clock selection register (prm01) 00h timer 10 (tm10) 0000h compare register 1n (cm1n) (n = 00, 01) 0000h capture/compare register 1n (cc1n) (n = 00, 01) 0000h capture/compare control register 0 (ccr0) 00h timer unit mode register 0 (tum0) 00h timer control register 10 (tmc10) 00h signal edge selection register 10 (sesa10) 00h prescaler mode register 10 (prm10) 07h status register 0 (status0) 00h timer connection selection register 0 (tmic0) 00h timer 1/timer 2 clock select ion register (prm02) 00h cc101 capture input selection register (csl10) 00h on-chip peripheral i/o timer 1 timer 10 noise elimination time se lection register (nrc10) 00h
chapter 13 reset function 596 user?s manual u15195ej5v0ud table 13-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (3/5) on-chip hardware register name initial value after reset timer 2 clock stop regi ster 0 (stopte0) 0000h timer 2 clock stop register 0l (stopte0l) 00h timer 2 clock stop register 0h (stopte0h) 00h timer 2 count clock/control edge selection register 0 (cse0) 0000h timer 2 count clock/control edge se lection register 0l (cse0l) 00h timer 2 count clock/control edge selection register 0h (cse0h) 00h timer 2 subchannel input event edge selection register 0 (sese0) 0000h timer 2 subchannel input event edge selection register 0l (sese0l) 00h timer 2 subchannel input event edge selection register 0h (sese0h) 00h timer 2 time base control register 0 (tcre0) 0000h timer 2 time base control register 0l (tcre0l) 00h timer 2 time base control register 0h (tcre0h) 00h timer 2 output control register 0 (octle0) 0000h timer 2 output control register 0l (octle0l) 00h timer 2 output control register 0h (octle0h) 00h timer 2 subchannels 0 and 5 capture/compare control register (cmse050) 0000h timer 2 subchannels 1 and 2 capture/compare control register (cmse120) 0000h timer 2 subchannels 3 and 4 capture/compare control register (cmse340) 0000h timer 2 subchannel n secondary capture/compare register (cvsen0) (n = 0 to 4) 0000h timer 2 subchannel n main capture/compare register (cvpen0) (n = 0 to 4) 0000h timer 2 subchannel n capture/compare register (cvsen0) (n = 0, 5) 0000h timer 2 time base status register 0 (tbstate0) 0101h timer 2 time base status register 0l (tbstate0l) 01h timer 2 time base status register 0h (tbstate0h) 01h timer 2 capture/compare 1 to 4 st atus register 0 (ccstate0) 0000h timer 2 capture/compare 1 to 4 status register 0l (ccstate0l) 00h timer 2 capture/compare 1 to 4 status register 0h (ccstate0h) 00h timer 2 output delay register 0 (odele0) 0000h timer 2 output delay register 0l (odele0l) 00h timer 2 output delay register 0h (odele0h) 00h timer 2 timer 2 software event capture register 0 (csce0) 0000h timer 3 (tm3) 0000h capture/compare register 3n (cc3n) (n = 0,1) 0000h timer control register 30 (tmc30) 00h on-chip peripheral i/o timer 3 timer control register 31 (tmc31) 20h
chapter 13 reset function 597 user?s manual u15195ej5v0ud table 13-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (4/5) on-chip hardware register name initial value after reset valid edge selection register (sesc) 00h timer 3 clock selection register (prm03) 00h timer 3 noise elimination time selection register (nrc3) 00h timer 3 timer 3 output control register (toc3) 00h timer 4 (tm4) 0000h compare register 4 (cm4) 0000h timer 4 timer control register 4 (tmc4) 00h clocked serial interface mode regi ster n (csimn) (n = 0,1) 00h clocked serial interface clock selecti on register n (csicn) (n = 0,1) 00h clocked serial interface receive buffer register n (sirbn) (n = 0,1) 0000h clocked serial interface re ceive buffer register ln (sirbln) (n = 0, 1) 00h clocked serial interface transmit buffe r register n (sotbn) (n = 0,1) 0000h clocked serial interface transmit bu ffer register ln (sotbln) (n = 0, 1) 00h clocked serial interface read-only receive buffer register n (sirben) (n = 0,1) 0000h clocked serial interface read -only receive buffer register ln (sirbeln) (n = 0, 1) 00h clocked serial interface first stage transmit buffer register n (sotbfn) (n = 0,1) 0000h clocked serial inte rface first stage transmit buffer register ln (sotbfln) (n = 0, 1) 00h serial i/o shift register n (sion) (n = 0,1) 0000h serial i/o shift register ln (sioln) (n = 0, 1) 00h prescaler mode register 3 (prsm3) 00h serial interface function (csi0, csi1) prescaler compare register 3 (prscm3) 00h asynchronous serial interface mode register 0 (asim0) 01h receive buffer register 0 (rxb0) ffh asynchronous serial interface st atus register 0 (asis0) 00h transmit buffer register 0 (txb0) ffh asynchronous serial interface transm it status register 0 (asif0) 00h baud rate generator control register 0 (brgc0) ffh serial interface function (uart0) clock selection register 0 (cksr0) 00h asynchronous serial interface mo de register 10 (asim10) 81h asynchronous serial interface mo de register 11 (asim11) 00h asynchronous serial interface st atus register 1 (asis1) 00h 2-frame consecutive receive buffer register 1 (rxb1) undefined receive buffer register l1 (rxbl1) undefined 2-frame consecutive transmit shift register 1 (txs1) undefined on-chip peripheral i/o serial interface function (uart1) transmit shift register l1 (txsl1) undefined
chapter 13 reset function 598 user?s manual u15195ej5v0ud table 13-2. initial values of cpu, internal ram, and on-chip periphera l i/o after reset (5/5) on-chip hardware register name initial value after reset prescaler mode register 1 (prsm1) 00h serial interface function (uart1) prescaler compare register 1 (prscm1) 00h a/d scan mode register n0 (adscmn0) (n = 0,1) 0000h a/d scan mode register n0l (adscmn0l) (n = 0, 1) 00h a/d scan mode register n0h (adscmn0h) (n = 0, 1) 00h a/d scan mode register n1 (adscmn1) (n = 0,1) 0000h a/d scan mode register n1l (adscmn1l) (n = 0, 1) 00h a/d scan mode register n1h (adscmn1h) (n = 0, 1) 00h a/d voltage detection mode register n (adetmn) (n = 0,1) 0000h a/d voltage detection mode register nl (adetmnl) (n = 0, 1) 00h a/d voltage detection mode register nh (adetmnh) (n = 0, 1) 00h a/d conversion result register 0n (adcr0n) (n = 0 to 5) 0000h a/d conversion result register 1n (adcr1n) (n = 0 to 7) 0000h a/d converter a/d internal trigger selection register n (itrgn) (n = 0, 1) 00h ports (p0 to p4, pdh, pct, pcm) undefined port (pdl) undefined port (pdll) undefined port (pdlh) undefined mode registers (pm1 to pm4, pmdh, pmct, pmcm) ffh mode register (pmdl) ffffh mode register (pmdll) ffh mode register (pmdlh) ffh mode control registers (pmc1 to pmc4) 00h mode control registers (pmcdh) 00h/ffh mode control register (pmcdl) 0000h/ffffh mode control register (pmcdll) 00h/ffh mode control register (pmcdlh) 00h/ffh mode control register (pmcct) 00h/53h mode control register (pmccm) 00h/03h port function function control registers (pfc1, pfc2, pfc3) 00h regulator regulator control register (regc) 00h on-chip peripheral i/o flash memory flash programming mode c ontrol register (flpmc) 08h/0ch/00h note note pd703114: 00h pd70f3114: 08h or 0ch (for details, refer to 15.7.12 flash programming mode control register (flpmc) .) caution in the table above, ?unde fined? means either undefined at the time of a power-on reset or undefined due to data destruction when reset input and data write ti ming are synchronized. for a reset other than this, data is main tained in its previous status.
user?s manual u15195ej5v0ud 599 chapter 14 regulator 14.1 features ? two power supplies, one for the internal cpu and one for the peripheral interface, are not necessary. ? a 5 v single power supply system can be configured by connecting an n-ch transistor (2sd1950 (vl standard product, surface mount type) or 2sd1581 (independent type) is recommended). ? if a 3.3 v power supply is available, it can be directly connected to the regin pin. 14.2 functional outline the v850e/ia2 has an internal regulator that can be used to configure a 5 v single power supply system. to use this regulator, connect an n-ch transistor (2sd1950 (vl standard product, surface mount type) or 2sd1581 (independent type) is recommended) to the regout pin, and the regin pin to cv ss via a capacitor for stabilizing the regulator output (refer to 14.3 connection example ). if two power supplies (5 v system for the peripheral interface and 3.3 v system for the internal cpu) are avai lable on the system, the regul ator can be stopped by the regulator control register (regc). the regulator always operates in each operation mode (nor mal operation, halt, idle, and software stop mode). if the 3.3 v power supply is provided separately, setting regc = 01h suppresses the current consumption (several 10 a) of the on-chip regulator.
chapter 14 regulator user?s manual u15195ej5v0ud 600 14.3 connection example (1) when using an on-chip regulator an on-chip regulator is used connected to an n-ch transistor. an example of connection when using an n-ch transis tor and the mount pad dimensions when mounted on the 2sd1950 (vl standard product) (when using a glass epoxy board) are shown below. figure 14-1. example of connection when using n-ch transistor rv dd v dd (4.5 to 5.5 v) regout n-ch transistor 22 f (recommended) regoff generator regin (3.3 v) internal circuit regulator v850e/ia2 r cv ss remark the 2sd1950 (vl standard product, surface mo unt type) or 2sd1581 (independent type) is recommended as the n-ch transistor. 110 k ? is recommended for r. an electrolytic capacitor of 22 f is recommended.
chapter 14 regulator user?s manual u15195ej5v0ud 601 figure 14-2. mount pad dimensions when mounted on 2sd1950 (vl standard product) (glass epoxy board) (unit: mm) 1.0 1.0 2.2 1.5 1.5 1.0 0.9 0.9 1.5 2.2 45 45 (2) when using an external regulator when an on-chip regulator is not used, an external regulator can be used. an example of connection when using an exter nal regulator application is shown below. figure 14-3. connection when using external regulator rv dd v dd regout (open) regin v850e/ia2 cv ss 3.3 v regulator 5 v regulator power supply remark connect a capacitor or inductance to the regulator i/o as required.
chapter 14 regulator user?s manual u15195ej5v0ud 602 14.4 control register (1) regulator control register (regc) the regc register controls the operation of the regulator. this register can be read/written in 8-bit or 1-bit units. cautions 1. change the value of the regc re gister only once after the system has been reset for system stabilization. 2. make sure that the pins are set as follows when the regc0 bit = 1 (when the regulator is stopped). ? regout pin: leave open ? regin pin: supply 3.3 v (3.0 to 3.6 v) to this pin. 3. also make sure that the pins are set as follows when the regc0 bit = 0 (regulator operating) (for details of the connection me thod, refer to 14.3 connection example). ? regout pin: connect this pin to the base of the external transistor. ? regin pin: connect this pin to the emi tter of the external transistor and to an electrolytic capacitor. ? connect a bias resistor between the base and emitter of the external transistor. 7 0 regc 6 0 5 0 4 0 3 0 2 0 1 0 0 regc0 address fffff300h after reset 00h bit position bit name function 0 regc0 controls the operation of the regulator. 0: regulator operates. 1: regulator stops.
603 user?s manual u15195ej5v0ud chapter 15 flash memory ( pd70f3114) the pd70f3114 is the flash memory version of the v 850e/ia2 and has an on-chip 128 kb flash memory. caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when pre-producing an applicatio n set with the flash memory version and then mass producing it with the mask rom version, be sure to c onduct sufficient evaluations on the commercial samples (cs) (not engineeri ng samples (es)) of the mask rom versions. writing to flash memory can be performed with the memory mounted on the target system (on board). a dedicated flash programmer is connected to t he target system to perform writing. the following can be considered as the development env ironment and the applications of flash memory. software can be changed after the v850e/ia 2 is solder-mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier. 15.1 features all area batch erase communication via serial interface from the dedicated flash programmer erase/write voltage: v pp = 7.8 v on-board programming 15.2 writing using flash programmer writing can be performed either on-board or off-board using a dedicated flash programmer. caution when writing flash memory using the flash programmer, be sure to operate the v850e/ia2 at 5 frequency in pll mode. (1) on-board programming the contents of the flash memory are rewritten after the v850e/ia2 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to flash memory is performed by the dedicated program adapter (fa series), etc., before mounting the v850e/ia2 on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd.
chapter 15 flash memory ( pd70f3114) 604 user?s manual u15195ej5v0ud when the flash writing adapter (f a-100gc-8eu) and dual-power-supply adapter (fa-tvc) are used for writing to the pd70f3114gc, connect the pins as follows. table 15-1. connection of v850e/ia2 flash writing adapter (fa-100gc-8eu) v850e/ia2 when uart0 used when csi0 used name marked on fa-100gc- 8eu pwb pin name pin no. pin name pin no. si txd0/p31 26 so0/p41 23 so rxd0/p30 25 si0/p40 22 sck ? sck0/p42 24 x1 x1 17 note 1 x1 17 note 1 x2 x2 18 note 1 x2 18 note 1 /reset reset 19 reset 19 v pp mode1/v pp 62 mode1/v pp 62 reserve/hs ? a16/pdh0 note 2 56 v dd 39, 64, 86 v dd 39, 64, 86 av dd0 94 av dd0 94 av dd1 2 av dd1 2 mode0 12 mode0 12 vdd note 3 rv dd 14 rv dd 14 v ss3 13, 63 v ss3 13, 63 v ss 38, 87 v ss 38, 87 av ss0 95 av ss0 95 cv ss 20 cv ss 20 av ss1 3 av ss1 3 gnd note 3 nmi/p00 74 nmi/p00 74 note 4 cksel 21 cksel 21 notes 1. the clock amplitude of x1 and x2 is 3.3 v. configure the oscillator on the fa-100gc-8eu board using a resonator and a capacitor. the following figure shows an example of the oscillator. example cv ss x1 x2 2. connection is not required for this pin when not using a handshake. 3. use the dual-power-supply adapter (fa-tvc) for generating 3.3 v on the fa -100gc-8eu board. in this case, the 2sd1950 or 2sd1581 is not required. 4. in pll mode: gnd in direct mode: v dd remark ? : leave open
chapter 15 flash memory ( pd70f3114) 605 user?s manual u15195ej5v0ud when the flash writing adapter (fa-100gf-3ba) and du al-power-supply adapter (fa-tvc) are used for writing to the pd70f3114gf, connect the pins as follows. table 15-2. connection of v850e/ia2 flash writing adapter (fa-100gf-3ba) v850e/ia2 when uart0 used when csi0 used name marked on fa-100gf- 3ba pwb pin name pin no. pin name pin no. si txd0/p31 28 so0/p41 25 so rxd0/p30 27 si0/p40 24 sck ? sck0/p42 26 x1 x1 19 note 1 x1 19 note 1 x2 x2 20 note 1 x2 20 note 1 /reset reset 21 reset 21 v pp mode1/v pp 64 mode1/v pp 64 reserve/hs ? a16/pdh0 note 2 58 v dd 41, 66, 88 v dd 41, 66, 88 av dd0 96 av dd0 96 av dd1 4 av dd1 4 mode0 14 mode0 14 vdd note 3 rv dd 16 rv dd 16 v ss3 15, 65 v ss3 15, 65 v ss 40, 89 v ss 40, 89 av ss0 97 av ss0 97 cv ss 22 cv ss 22 av ss1 5 av ss1 5 gnd note 3 nmi/p00 76 nmi/p00 76 note 4 cksel 23 cksel 23 notes 1. the clock amplitude of x1 and x2 is 3.3 v. configure the oscillator on the fa-100gf-3ba board using a resonator and a capacitor. the following figure shows an example of the oscillator. example cv ss x1 x2 2. connection is not required for this pin when not using a handshake. 3. use the dual-power-supply adapter (fa-tvc) for generating 3.3 v on the fa-100gf-3ba board. in this case, the 2sd1950 or 2sd1581 is not required. 4. in pll mode: gnd in direct mode: v dd remark ? : leave open
chapter 15 flash memory ( pd70f3114) 606 user?s manual u15195ej5v0ud 15.3 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850e/ia2. figure 15-1. environment for writing a program to flash memory v850e/ia2 dedicated flash programmer v ss3 v ss uart0 reset csi0 rs-232-c host machine v dd v pp regin v dd v pp1 gnd fa-tvc pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx y yyy statve usb a host machine is required for controlling the dedicated flash programmer. uart0 or csi0 is used for the inte rface between the dedicated flash programmer and the v850e/ia2 to perform writing, erasing, etc. a dedicated program adapter (fa series) and dual-p ower-supply adapter (fa-tvc) are required for off-board writing. 15.4 communication mode (1) uart0 transfer rate: 4,800 bps to 76,800 bps (lsb first) figure 15-2. communication with de dicated flash programmer (uart0) v850e/ia2 dedicated flash programmer v pp1 v pp reset reset so si txd0 rxd0 v ss3 v ss gnd v dd regin v dd fa-tvc pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x xx x x x x xxxx yyyy statve caution the operating clock amplit ude of the v850e/ia2 is 3.3 v.
chapter 15 flash memory ( pd70f3114) 607 user?s manual u15195ej5v0ud (2) csi0 transfer rate: up to 2 mhz (msb first) figure 15-3. communication with de dicated flash programmer (csi0) v850e/ia2 v pp1 v pp reset so si sck dedicated flash programmer sck0 so0 si0 reset v ss3 v ss gnd v dd regin v dd fa-tvc pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve caution the operating clock amplit ude of the v850e/ia2 is 3.3 v. the dedicated flash programmer out puts transfer clocks and the v8 50e/ia2 operates as a slave. (3) handshake-supported csi communication transfer rate: up to 2 mhz (msb first) figure 15-4. communication with dedicated flash programmer (hands hake-supported csi communication) v850e/ia2 dedicated flash programmer v pp1 v pp reset reset so si so0 si0 pdh0 sck sck0 hs v ss3 v ss gnd v dd regin v dd fa-tvc pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve caution the operating clock amplit ude of the v850e/ia2 is 3.3 v.
chapter 15 flash memory ( pd70f3114) 608 user?s manual u15195ej5v0ud 15.5 pin connection when performing on-board writing, instal l a connector on the target system to connect to the dedicated flash programmer. also, install a function on-board to switch from the normal operation mode (single-chip mode or romless mode) to the flas h memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming become the same status as they were immediately after reset in single- chip mode. therefore, all the ports become output high- impedance status, so that pin connection is required when the external device does not acknowledge the output high- impedance status. 15.5.1 mode1/v pp pin in the normal operation mode, 0 v is input to the mode1/v pp pin. in the flash memory programming mode, 7.8 v writing voltage is supplied to the mode1/v pp pin. the following shows an ex ample of the connection of the mode1/v pp pin. figure 15-5. connection example of mode1/v pp pin v850e/ia2 mode1/v pp pull-down resistor (r vpp = 5 to 50 k ? ) dedicated flash programmer connection pin 15.5.2 serial interface pin the following shows the pins used by each serial interface. table 15-3. pins used by each serial interface serial interface pins used csi0 so0, si0, sck0 csi0 + hs so0, si0, sck0, pdh0 uart0 txd0, rxd0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) which is connected to another device (output), a conflict of signals occurs. to av oid the conflict of signals, isolate the connection to the other device or set the other dev ice to the output high-impedance status.
chapter 15 flash memory ( pd70f3114) 609 user?s manual u15195ej5v0ud figure 15-6. conflict of signals (serial interface input pin) v850e/ia2 input pin output pin other device dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. therefore, isolate the signals on the other device side. (2) malfunction of the other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. figure 15-7. malfunction of other device v850e/ia2 output pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the v850e/ia2 outputs affects the other device, isolate the signal on the other device side. v850e/ia2 input pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
chapter 15 flash memory ( pd70f3114) 610 user?s manual u15195ej5v0ud 15.5.3 reset pin when connecting the reset signals of the dedicated flash progr ammer to the reset pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when the reset signal is input from the user system in flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 15-8. conflict of signals (reset pin) v850e/ia2 reset output pin reset signal generator dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. 15.5.4 nmi pin do not change the input signal to the nmi pin in flash me mory programming mode. if it is changed in flash memory programming mode, programming may not be performed correctly. 15.5.5 mode0, mode1 pins to shift to the flash memory programming mode, set mode0 to high level, apply the writing voltage (7.8 v) to the mode1/v pp pin, and release reset. 15.5.6 port pins when the flash memory programming mode is set, all the port pins except the pins which communicate with the dedicated flash programmer become output high-impedance status. nothing need be done to these port pins. if problems such as disabling output high-im pedance status should occur to the external devices connected to the ports, connect them to v dd or v ss via resistors. 15.5.7 other signal pins connect x1 and x2 to the same status as in the normal operation mode. the amplitude is 3.3 v. 15.5.8 power supply supply the power supply (v dd , v ss , v ss3 , av dd0 , av dd1 , av ss0 , av ss1 , cv ss , rv dd ) the same as in normal operation mode. supply 3.3 v to the regin pin from the dual-power-supply adapter (fa-tvc).
chapter 15 flash memory ( pd70f3114) 611 user?s manual u15195ej5v0ud 15.6 programming method 15.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 15-9. flash memory manipulating procedure start switch to flash memory programming mode supply reset pulse select communication mode manipulate flash memory end? end no yes
chapter 15 flash memory ( pd70f3114) 612 user?s manual u15195ej5v0ud 15.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedi cated flash programmer, set the v850e/ia1 in the flash memory programming mode. to switch to this mode, set the mode0 and mode1/v pp pins before canceling reset. when performing on-board writing, cha nge modes using a jumper, etc. ? mode0: high-level input ? mode1/v pp : 7.8 v figure 15-10. flash memory programming mode ... n 1 flash memory programming mode 7.8 v mode1/v pp 3.3 v 0 v reset 2 15.6.3 selection of communication mode in the v850e/ia2, a communication mode is selected by inputting pulses (16 pulses max.) to v pp pin after switching to the flash memory programming mode. the v pp pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 15-4. list of communication mode v pp pulse communication mode remarks 0 csi0 3 handshake-supported csi v850e/ia2 performs slave operation, msb first 8 uart0 communication rate: 9600 bps (after reset), lsb first others rfu (reserved) setting prohibited
chapter 15 flash memory ( pd70f3114) 613 user?s manual u15195ej5v0ud 15.6.4 communication commands the v850e/ia2 communicates with the dedicated flash programmer by means of commands. a command sent from the dedicated flash programmer to the v850e/ia2 is called a ?command?. the response signal sent from the v850e/ia2 to the dedicated flash programmer is called the ?response command?. figure 15-11. communication commands v850e/ia2 dedicated flash programmer command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx xxx yyy x x x x x x x x x x x x x x x xxxx yyyy statve the following shows the commands for controlling flash me mory of the v850e/ia2. all of these commands are issued from the dedicated flash programmer, and the v850 e/ia2 performs the various processing corresponding to the commands. table 15-5. commands for controlling flash memory category command name function batch verify command compares the contents of the entire memory and the input data. verify area verify command compares the contents of the specified area and the input data. batch erase command erases the c ontents of the entire memory. area erase command erases the contents of the specified area. erase write back command writes back the contents which were erased. batch blank check command checks the erase state of the entire memory. blank check area blank check command checks the erase state of the specified area. high-speed write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. data write continuous write command writes data from the address following the high- speed write command executed immediately before, and executes verify check. status read out command acquires the status of operations. oscillation frequency setting command sets the oscillation frequency. erasing time setting command sets the erasing time of batch erase. writing time setting command sets the writing time of data write. write back time setting command sets the write back time. silicon signature command reads outs the silicon signature information. system setting and control reset command escapes from each state.
chapter 15 flash memory ( pd70f3114) 614 user?s manual u15195ej5v0ud the v850e/ia2 sends back response commands for the co mmands issued from the dedicated flash programmer. the following shows the response commands the v850e/ia2 sends out. table 15-5. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc. 15.7 flash memory programming by self-programming the pd70f3114 supports a self-programming function to rewr ite the flash memory using a user program. by using this function, the flash memory can be rewritten with a user application. this se lf-programming function can be also used to upgrade the program in the field. 15.7.1 outline of self-programming self-programming implements erasure and writing of the flash memory by calling the self-programming function (device?s internal processi ng) on the program placed in the block 0 space (000000h to 1fffffh) and areas other than internal rom area. to place the program in the bl ock 0 space and internal rom area, copy the program to areas other than 000000h to 1fffffh (e.g. internal ram area) and execute the program to call the self- programming function. to call the self-programming function, change the operating mode from normal operation mode to self- programming mode using the flash programmi ng mode control register (flpmc). figure 15-12. outline of self-programming 128 kb flash memory 00000h 1ffffh erase area note (64 kb) erase area note (64 kb) flash memory normal operation mode self-programming mode 00000h 1ffffh flpmc 02h flpmc 00h self-programming function (erase/write routine incorporated) note data is erased in area units (64 kb).
chapter 15 flash memory ( pd70f3114) 615 user?s manual u15195ej5v0ud 15.7.2 self-programming function the pd70f3114 provides self-programming functions, as s hown in table 15-7. by combining these functions, erasing/writing flash memory becomes possible. table 15-7. function list type function name function erase area erase erases the specified area. continuous write in word units continuously writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. write pre-write writes 0 to flash memory before erasure. erase verify checks whether an ov er erase occurred after erasure. erase byte verify checks whether erasure is complete. check internal verify checks whether the signal level of the post-write data in flash memory is appropriate. write back area write back writes back th e flash memory area in which an over erase occurred. acquire information flash memory information read reads out information about flash memory. 15.7.3 outline of self-programming interface to execute self-programming using t he self-programming interface, the envi ronmental conditions of the hardware and software for manipulating the flash memory must be satisfied. it is assumed that the self-programming interface is used in an assembly language. (1) entry program this program is to call the inter nal processing of the device. it is a part of the application program, and must be executed in memory other than the block 0 space and internal rom area (flash memory). (2) device internal processing this is manipulation of the flash memory executed inside the device. this processing manipulates the flash memory after it has been called by the entry program. (3) ram parameter this is a ram area to which the parameters necessary for self-programming, such as write time and erase time, are written. it is set by the application pr ogram and referenced by the device internal processing.
chapter 15 flash memory ( pd70f3114) 616 user?s manual u15195ej5v0ud the self-programming interface is outlined below. figure 15-13. outline of self-programming interface application program entry program ram parameter device internal processing flash memory self-programming interface flash-memory manipulation 15.7.4 hardware environment to write or erase the flash memory, a high voltage must be applied to the v pp pin. to execute self-programming, a circuit that can generate a write voltage (v pp ) and that can be controlled by software is necessary on the application system. an example of a circuit that can select a voltage to be applied to the v pp pin by manipulating a port is shown below. figure 15-14. example of self-p rogramming circuit configuration v dd = 3.3 v 0.3 v pd70f3114 v dd , av ddn , rv dd v ss3 , v ss , cv ss , av ssn v pp output port ic for power supply output input on/off v ss 10 k ? 10 k ? v in v pp = 7.8 v 0.3 v regin v dd = 5.0 v 0.5 v remark n = 0, 1
chapter 15 flash memory ( pd70f3114) 617 user?s manual u15195ej5v0ud the voltage applied to the v pp pin must satisfy the following conditions: ? hold the voltage applied to the v pp pin at 0 v in the normal operation mode and hold the v pp voltage only while the flash memory is being manipulated. ? the v pp voltage must be stable from before manipulation of the flash memory star ts until manipulation is complete. cautions 1. apply 0 v to the v pp pin when reset is released. 2. implement self-programming in single-chip mode 0 or 1. 3. apply the voltage to the v pp pin in the entry program. 4. if both writing and erasing are executed by using the self-programming function and flash memory programmer on the target board, be sure to communicate with the programmer using csi0 (do not use the handshake-supported csi). figure 15-15. timing to apply voltage to v pp pin flash memory manipulation reset signal v pp signal v pp 0 v v dd or regin 0 v
chapter 15 flash memory ( pd70f3114) 618 user?s manual u15195ej5v0ud 15.7.5 software environment the following conditions must be satisfie d before using the entry program to call the device internal processing. table 15-8. software en vironmental conditions item description location of entry program execute the entry program in memory other than the block 0 space and flash memory area. the device internal processing cannot be directly ca lled by the program that is executed on the flash memory. execution status of program the device internal processing cannot be called while an interrupt is being serviced (np bit of psw = 0, id bit of psw = 1). masking interrupts mask all the maskable interrupts used. mask each interrupt by using the corresponding interrupt control register. to mask a maskable interrupt, be sure to specif y masking by using the corresponding interrupt control register. mask the maskable interrupt ev en when the id bit of the psw = 1 (interrupts are disabled). manipulation of v pp voltage stabilize the voltage applied to the v pp pin (v pp voltage) before starting manipulation of the flash memory. after completion of the manipulation, return the voltage of the v pp pin to 0 v. initialization of internal timer do not use the internal timer while the flash memory is being manipulated. because the internal timer is initialized after the fl ash memory has been used, initialize the timer with the application program to use the timer again. stopping reset signal input do not input the reset signal while t he flash memory is being manipulated. if the reset signal is input while the flash memory is being manipulated, the contents of the flash memory under manipulation become undefined. stopping nmi signal input do not input the nmi signal while the flash memory is being manipulated. if the nmi signal is input while the flash memory is being manipulated, the flash memory may not be correctly manipulated by the device internal processing. if an nmi occurs while the device internal processing is in progress, the occurrence of the nmi is reflected in the nmi flag of the ram parameter. if manipulation of the flash memory is affected by the occurrence of the nmi, the function of each self-programming function is reflected in the return value. reserving stack area the device internal processing takes over the stack used by t he user program. it is necessary that an area of 300 bytes be reserved for the stack size of the user program when the device internal processing is called. r3 is used as the stack pointer. saving general-purpose registers the device internal processing rewrites the co ntents of r6 to r14, r20, and r31 (lp). save and restore these register contents as necessary.
chapter 15 flash memory ( pd70f3114) 619 user?s manual u15195ej5v0ud 15.7.6 self-programming function number to identify a self-programming function, the following numbers are assigned to the respective functions. these function numbers are used as parameters when the device internal processing is called. table 15-9. self-programming function number function no. function name 0 acquiring flash information 1 erasing area 2 to 4 rfu 5 area write back 6 to 8 rfu 9 erase byte verify 10 erase verify 11 to 15 rfu 16 continuous write in word units 17 to 19 rfu 20 pre-write 21 internal verify other prohibited remark rfu: reserved for future use
chapter 15 flash memory ( pd70f3114) 620 user?s manual u15195ej5v0ud 15.7.7 calling parameters the arguments used to call the self-programming function are shown in the table below. in addition to these arguments, parameters such as the write time and erase ti me are set to the ram parameters indicated by ep (r30). table 15-10. calling parameters function name first argument (r6) function no. second argument (r7) third argument (r8) fourth argument (r9) return value (r10) acquiring flash information 0 option number note 1 ? ? note 1 erasing area 1 area erase start address ? ? 0: normal completion other than 0: error area write back 5 none (acts on erase manipulation area immediately before) ? ? none erase byte verify 9 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error erase verify 10 none (acts on erase manipulation area immediately before) ? ? 0: normal completion other than 0: error continuous write in word units note 2 16 write start address note 3 start address of write source data note 3 number of words to be written (word units) 0: normal completion other than 0: error pre-write 20 write start address number of bytes to be written ? 0: normal completion other than 0: error internal verify 21 verify star t address number of bytes to be verified ? 0: normal completion other than 0: error notes 1. see 15.7.10 flash information for details. 2. prepare write source data in memory other than the flash memory when data is written continuously in word units. 3. this address must be at a 4-byte boundary. caution for all the functions, ep (r30) must in dicate the first address of the ram parameter.
chapter 15 flash memory ( pd70f3114) 621 user?s manual u15195ej5v0ud 15.7.8 contents of ram parameters reserve the following 48-byte area in the internal ram or external ram for the ram parameters, and set the parameters to be input. set the base addresses of these parameters to ep (r30). table 15-11. description of ram parameter address size i/o description ep+0 4 bytes ? for internal operations ep+4:bit 5 note 1 1 bit input operation flag (be sure to set this fl ag to 1 before calling the device internal processing.) 0: normal operation in progress 1: self-programming in progress ep+4:bit 7 notes 2, 3 1 bit output nmi flag 0: nmi not detected 1: nmi detected ep+8 4 bytes input erase time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = erase time ( s)/internal operation unit time ( s) example: if erase time is 0.4 s 0.4 1,000,000/100 = 4,000 (integer operation) ep+0xc 4 bytes input write bac k time (unsigned 4 bytes) expressed as 1 count value in units of the internal operation unit time (100 s). set value = write back time ( s)/internal operation unit time ( s) example: if write back time is 1 ms 1 1,000/100 = 10 (integer operation) ep+0x10 2 bytes input timer set value for creating internal operation unit time (unsigned 2 bytes) write a set value that makes the value of timer 4 the internal operation unit time (100 s). set value = operating frequency (hz)/1,000,000 internal operation unit time ( s)/ timer division ratio (4) + 1 note 4 example: if the operating frequency is 40 mhz 40,000,000/1,000,000 100/4 + 1 = 1,001 (integer operation) ep+0x12 2 bytes input timer set value for creating write time (unsigned 2 bytes) write a set value that makes the value of timer 4 the write time. set value = operating frequency (hz)/write time ( s)/timer division ratio (4) + 1 note 4 example: if the operating frequency is 40 mhz and the write time is 20 s 40,000,000/1,000,000 20/4 + 1 = 201 (integer operation) ep+0x14 28 bytes ? for internal operations notes 1. fifth bit of address of ep+4 (least significant bit is bit 0.) 2. seventh bit of address of ep+4 (least significant bit is bit 0.) 3. clear the nmi flag by the user program because it is not cleared by the device internal processing. 4. the device internal processing sets this value minus 1 to the timer. because th e fraction is rounded up, add 1 as indicated by the ex pression of the set value. caution be sure to reserve the ram parameter area at a 4-byte boundary.
chapter 15 flash memory ( pd70f3114) 622 user?s manual u15195ej5v0ud 15.7.9 errors during self-programming the following errors related to manipulation of the flas h memory may occur during self-programming. an error occurs if the return value (r10) of each function is not 0. table 15-12. errors during self-programming error function description overerase error erase verify excessive erasure occurs. undererase error (blank check error) erase byte verify erasure is insuffic ient. additional erase operation is needed. verify error continuous write in word units the written data cannot be correctly read. either an attempt has been made to write to flash memory that has not been erased, or writing is not sufficient. internal verify error internal verify the wr itten data is not at the correct signal level. caution the overerase error and undererase error may simultaneously occur in the entire flash memory. 15.7.10 flash information for the flash information acquisition function (function no. 0), the option number (r7) to be specified and the contents of the return value (r10) are as follows. to acqui re all flash information, call the function as many times as required in accordance with the format shown below. table 15-13. flash information option no. (r7) return value (r10) 0 specification prohibited 1 specification prohibited 2 bit representation of return value (msb: bi t 31) fffffffffff fffffaaaaaaaaffffffff (lsb: bit 0) bits 31 to 16: ffffffffffffffff (reserved for future use) mask bits 31 to 16 because they are not normally 0. bits 15 to 8: aaaaaaaa (number of areas) (unsigned 8 bits) bits 7 to 0: ffffffff (reserved for future use) mask bits 7 to 0 because they are not normally 0. 3+0 end address of area 0 3+1 end address of area 1 cautions 1. the start address of area 0 is 0. the ?end address + 1? of the preceding area is the start address of the next area. 2. the flash information acquisition functi on does not check values su ch as the maximum number of areas specified by the argument of an option. if an illegal value is specified, an undefined value is returned.
chapter 15 flash memory ( pd70f3114) 623 user?s manual u15195ej5v0ud 15.7.11 area number the area numbers and memory map of the pd70f3114 are shown below. figure 15-16. area configuration area 1 (64 kb) area 0 (64 kb) 0 x 1 f f f f (end address of area 1) 0 x 0 0 0 0 0 (start address of area 0) 0 x 1 0 0 0 0 (start address of area 1) 0 x 0 f f f f (end address of area 0)
chapter 15 flash memory ( pd70f3114) 624 user?s manual u15195ej5v0ud 15.7.12 flash programming mode control register (flpmc) the flash programming mode control regist er (flpmc) is a register used to en able/disable writing to flash memory and to specify the self-programming mode. this register can be read/written in 8-bit or 1- bit units (the vpp bit (bit 2) is read-only). cautions 1. be sure to transfer control to th e internal ram or external memory beforehand to manipulate the flspm bit. however, in on- board programming mode set by the flash programmer, the specification of flspm bit is ignored. 2. do not change the initial value of bits 0 and 4 to 7. flpmc address fffff8d4h initial value note 08h/0ch/00h 7 6 5 4 <3> <2> <1> 0 0 flspm vpp vppdis 0 0 0 0 note 08h: when writing voltage is not applied to the v pp pin 0ch: when writing voltage is applied to the v pp pin 00h: product not provided with flash memory ( pd703114) bit position bit name function 3 vppdis enables/disables writing/erasing on-chip flash memory. when this bit is 1, writing/erasing on-chip flash memory is disabled even if a high voltage is applied to the v pp pin. 0: enables writing/erasing flash memory 1: disables writing/erasing flash memory 2 vpp indicates the voltage applied to the v pp pin reaches the writing-enabled level (read- only). this bit is used to check whether writing is possible or not in the self- programming mode. 0: indicates high-voltage application to v pp pin is not detected (the voltage has not reached the writing voltage enable level) 1: indicates high-voltage application to v pp pin is detected (the voltage has reached the writing voltage enable level) 1 flspm controls switching between internal rom and the self-programming interface. this bit can switch the mode between the normal mode set by the mode pin on the application system and the self-programming mo de. the setting of this bit is valid only if the voltage applied to the v pp pin reaches the writing voltage enable level. 0: normal mode (for all addresses, instruction fetch is performed from on-chip flash memory) 1: self-programming mode (device internal processing is started)
chapter 15 flash memory ( pd70f3114) 625 user?s manual u15195ej5v0ud setting data to the flash programming mode control regist er (flpmc) is performed in the following sequence. <1> disable interrupts (set the np bit and id bit of the psw to 1). <2> prepare the data to be set in the specif ic register in a general-purpose register. <3> write data to the peripheral command register (phcmd). <4> set the flash programming mode control register (flpmc) by executing the following instructions. ? store instruction (st/sst instructions) ? bit manipulation instruction (set1/clr1/not1 instructions) <5> insert nop instructions (5 instructions (<5> to <9>)). <10> cancel the interrupt disabled stat e (reset the np bit of the psw to 0). [description example] <1> ldsr rx, 5 <2> mov 0x02, r10 <3> st.b r10, phcmd[r0] <4> st.b r10, flpmc[r0] <5> nop <6> nop <7> nop <8> nop <9> nop <10> ldsr ry, 5 remark rx: value written to the psw ry: value returned to the psw no special sequence is required for reading a specific register. cautions 1. if an interrupt is acknowledged between when phcmd is issued (<3>) and writing to a specific register (<4>) immediat ely after issuing phcmd, writi ng to the specific register may not be performed and a protection error may occu r (the prerr bit of the phs register = 1). therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. similarly, disable acknowledgment of interrupts when a bit manipulation instruction is used to set a specific register. 2. use the same general-purpose register used to set a specific register (<3>) for writing to the phcmd register (<4>) even though the data wri tten to the phcmd register is dummy data. this is the same as when a general-purpo se register is used for addressing. 3. before executing this processing, complete all dma transfer operations.
chapter 15 flash memory ( pd70f3114) 626 user?s manual u15195ej5v0ud 15.7.13 calling device internal processing this section explains the procedure to call the dev ice internal processing from the entry program. before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary argum ents and ram parameters have been set. call the device internal processing by setting the flspm bit of the flas h programming mode control register (flpmc) to 1 and then executing the trap 0x1f instruction. th e processing is always called using the same procedure. it is assumed that the program of this interface is described in an assembly language. <1> set the flpmc register as follows: ? vppdis bit = 0 (to enable writing/erasing flash memory) ? flspm bit = 1 (to select self-programming mode) <2> clear the np bit of the psw to 0 (to enable nmis (only when nmis are used on the application)). <3> execute trap 0x1f to transfer the cont rol to the device?s internal processing. <4> set the np bit and id bit of the psw to 1 (to disable all interrupts). <5> set the value to the peripheral command register (phcmd) that is to be set to the flpmc register. <6> set the flpmc register as follows: ? vppdis bit = 1 (to disable writing/erasing flash memory) ? flspm bit = 0 (to select normal operation mode) <7> wait for the internal manipulation setup time (see 15.7.13 (5) internal ma nipulation setup parameter ). (1) parameter r6: first argument (sets a self-programming function number) r7: second argument r8: third argument r9: fourth argument ep: first address of ram parameter (2) return value r10: return value (return value from device internal processing of 4 bytes) ep+4:bit 7: nmi flag (flag indicating whether an nmi occurred while the device internal processing was being executed) 0: nmi did not occur while device internal processing was being executed. 1: nmi occurred while device internal processing was being executed. if an nmi occurs while control is being transfe rred to the device internal processing, the nmi request may never be reflected. because the nmi flag is not internally reset, this bit must be cleared before calling the device internal processi ng. after the control returns from the device internal processing, nmi dummy processing can be executed by checking the status of this flag using software. (3) description transfer control to the device internal processing specif ied by a function number using the trap instruction. to do this, the hardware and software environmental conditi ons must be satisfied. even if trap 0x1f is used in the user application program, trap 0x1f is treated as another operation afte r the flpmc register has been set. therefore, use of the tr ap instruction is not rest ricted on the application.
chapter 15 flash memory ( pd70f3114) 627 user?s manual u15195ej5v0ud (4) program example an example of a program in which the entry program is executed as a subroutine is shown below. in this example, the return address is saved to the stack and then the device internal processing is called. this program must be located in memory other th an the block 0 space and flash memory area. isetup 130 -- internal manipulation setup parameter entryprogram: add -4, sp -- prepare st.w lp, 0[sp] -- save return address movea lo(0x00a0), r0, r10 -- ldsr r10, 5 -- psw = np, id mov lo(0x0002), r10 -- st.b r10, phcmd[r0] -- phcmd = 2 st.b r10, flpmc[r0] -- vppdis = 0, flspm = 1 nop nop nop nop nop movea lo(0x0020), r0, r10 -- ldsr r10, 5 -- psw = id trap 0x1f -- device internal process movea lo(0x00a0), r0, r6 -- ldsr r6, 5 -- psw = np, id mov lo(0x08), r6 st.b r6, phcmd[r0] -- phcmd = 8 st.b r6, flpmc[r0] -- vppdis = 1, flspm = 0 nop nop nop nop nop mov isetup, lp -- loop time = 130 loop: divh r6, r6 -- to kill time add -1, lp -- decrement counter jne loop -- ld.w 0[sp], lp -- reload lp add 4, sp -- dispose jmp [lp] -- return to caller
chapter 15 flash memory ( pd70f3114) 628 user?s manual u15195ej5v0ud (5) internal manipulation setup parameter if the self-programming mode is switch ed to the normal operation mode, the pd70f3114 must wait for 100 s before it accesses the flash memory. in the program exam ple in (4) above, the elapse of this wait time is ensured by setting isetup to ?104? (@ 40 mhz operatio n). the total number of execution clocks in this example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clo ck) + jne instruction (3 clocks)). ensure that a wait time of 100 s elapses by using the following expression. 39 clocks (total number of execution clocks) 25 ns (@ 40 mhz operation) 104 (isetup) = 101.4 s (wait time)
chapter 15 flash memory ( pd70f3114) 629 user?s manual u15195ej5v0ud 15.7.14 erasing flash memory flow the procedure to erase the flash memory is illustrated bel ow. the processing of each function number must be executed in accordance with the specified calling procedure. figure 15-17. erasing flash memory flow ... function no. 20 ... function no. 1 ... function no. 9 ... function no. 10 ... function no. 5 ... function no. 10 ... function no. 9 erase write error undererase error set ram parameter. mask interrupts. pre-write erase area erase byte verify erase verify area write back erase verify clear number of times write-back is repeated. erase byte verify write error? undererase? maximum number of times of repeating erasure is exceeded? maximum number of times of repeating write-back is exceeded? overerase? overerase? undererase? set v pp voltage. clear v pp voltage. unmask interrupts. clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. overerase error clear v pp voltage. unmask interrupts. normal completion clear v pp voltage. unmask interrupts. yes yes yes yes no no no yes no no no yes no yes
chapter 15 flash memory ( pd70f3114) 630 user?s manual u15195ej5v0ud 15.7.15 continuous writing flow the procedure to write data all at once to the flash memory by using the fu nction to continuously write data in word units is illustrated below. the processing of each functi on number must be executed in accordance with the specified calling procedure. figure 15-18. continuous writing flow ... function no. 16 yes no continuous writing mask interrupts. set v pp voltage. continuous writing error? clear v pp voltage. unmask interrupts. write error clear v pp voltage. unmask interrupts. normal completion set ram parameter.
chapter 15 flash memory ( pd70f3114) 631 user?s manual u15195ej5v0ud 15.7.16 internal verify flow the procedure of internal verificati on is illustrated below. the processing of each function number must be executed in accordance with the specified calling procedure. figure 15-19. internal verify flow ... function no. 21 yes no internal verify mask interrupts. set v pp voltage. internal verify error? clear v pp voltage. unmask interrupts. internal verify error clear v pp voltage. unmask interrupts. normal completion set ram parameter.
chapter 15 flash memory ( pd70f3114) 632 user?s manual u15195ej5v0ud 15.7.17 acquiring flash information flow the procedure to acquire the flash info rmation is illustrated below. the proce ssing of each function number must be executed in accordance with t he specified calling procedure. figure 15-20. acquiring flash information flow ... function no. 0 acquiring flash information mask interrupts. set v pp voltage. acquiring flash information clear v pp voltage. unmask interrupts. end set ram parameter.
chapter 15 flash memory ( pd70f3114) 633 user?s manual u15195ej5v0ud 15.7.18 self-programming library v850 series flash memory self-programming user?s manual is available for reference when executing self- programming. in this manual, the library uses the self-programming inte rface of the v850 series and can be used in c as a utility and as part of the application program . to use the library, thoroughly evaluate it on the application system. (1) functional outline figure 15-21 outlines the function of the self-programming library. in this figure, a rewriting module is located in area 0 and the data in area 1 is rewritten or erased. the rewriting module is a user program to rewrite the flash memory. the other areas can be also rewritten by using the flash functions included in this self-progr amming library. the flash functions expand the entry program in the external memory or internal ram and call the device internal processing. when using the self-programming library, make sure that the hardware conditions, such as the write voltage, and the software conditions, such as interrupts, are satisfied. figure 15-21. functional outlin e of self-programming library rewriting module flash rewriting program self-programming library flash function flash environment erase/write flash memory rewriting module area 1 area 0
chapter 15 flash memory ( pd70f3114) 634 user?s manual u15195ej5v0ud the configuration of the self-programming library is outlined below. figure 15-22. outline of self-p rogramming library configuration application program entry program ram parameter device internal processing flash memory self-programming interface self-programming library flash memory manipulation c interface
chapter 15 flash memory ( pd70f3114) 635 user?s manual u15195ej5v0ud 15.8 how to distinguish flash memory and mask rom versions it is possible to distinguish a flash memory version ( pd70f3114) and a mask rom version ( pd703114) by means of software, using the methods shown below. <1> disable interrupts (set the np bit of psw to 1). <2> write data to the peripheral command register (phcmd). <3> set the vppdis bit of the flash progra mming mode control register (flpmc) to 1. <4> insert nop instructions (5 instructions (<4> to <8>)). <9> cancel the interrupt disabled state (reset the np bit of the psw to 0). <10> read the vppdis bit of the flash prog ramming mode control register (flpmc). ? if the value read is 0: mask rom version ( pd703114) ? if the value read is 1: flash memory version ( pd70f3114) [description example] <1> ldsr rx, 5 <2> st.b r10, phcmd[r0] <3> set1 3, flpmc[r0] <4> nop <5> nop <6> nop <7> nop <8> nop <9> ldsr ry, 5 <10> tst1 3, flpmc[r0] bnz br remark rx: value written to the psw ry: value returned to the psw cautions 1. if an interrupt is acknowledged between when phcmd is issued (<2>) and writing to a specific register (<3>) immediat ely after issuing phcmd, writi ng to a specific register may not be performed and a protection error may occu r (the prerr bit of the phs register = 1). therefore, set the np bit of the psw to 1 (<1>) to disable interrupt acknowledgment. similarly, disable acknowledgment of interrupts when a bit manipulation instruction is used to set a specific register. 2. when a store instru ction is used for setti ng a specific register, be sure to use the same general-purpose register used to set the specifi c register for writing to the phcmd register even though the data written to the phcmd regist er is dummy data. this is the same as when a general-purpose regist er is used for addressing. 3. before executing this processing, complete all dma transfer operations.
636 user?s manual u15195ej5v0ud chapter 16 electrical specifications 16.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit regin regin pin ?0.5 to +4.6 v v dd v dd pin ?0.5 to +7.0 v rv dd rv dd pin ?0.5 to +7.0 v cv ss cv ss pin ?0.5 to +0.5 v av dd av dd0 , av dd1 pins ?0.5 to v dd + 0.5 note 1 v power supply voltage av ss av ss0 , av ss1 pins ?0.5 to +0.5 v v i1 other than x1 and v pp pins ?0.5 to v dd + 0.5 note 1 v input voltage v i2 v pp pin ( pd70f3114 only) note 2 ?0.5 to +8.5 v clock input voltage v k x1 pin ?0.5 to regin + 1.0 note 1 v av dd > v dd ?0.5 to v dd + 0.5 note 1 v analog input voltage v ian ani00 to ani05 pins, ani10 to ani17 pins v dd av dd ?0.5 to av dd + 0.5 note 1 v per pin for the to000 to to005 and to010 to to015 pins 20 ma per pin other than for the to000 to to005 and to010 to to015 pins 4.0 ma output current, low i ol total for all pins 180 ma per pin ?4.0 ma output current, high i oh total for all pins ?100 ma operating ambient temperature t a ?40 to +85 c storage temperature t stg ?65 to +150 c
chapter 16 electrical specifications 637 user?s manual u15195ej5v0ud notes 1. be sure not to exceed the absolute maximum rati ngs (max. value) of each power supply voltage. 2. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more (2 ms when the power supply voltage is stepped down via a regulator) after v dd has reached the lower-limit value (4.5 v) of the operating voltage range (see a in the figure below). ? when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (4.5 v) of the operating voltage range of v dd (see b in the figure below). 4.5 v v dd 0 v 0 v v pp 4.5 v a b cautions 1. do not directly connect output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open drain pins or open collector pins, however , can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the ab solute maximum rati ng is exceeded even momentarily for any parameter. that is, th e absolute maximum ra tings are rated values at which the product is on the verge of su ffering physical damage, and therefore the product must be used under conditions that en sure that the absolu te maximum ratings are not exceeded. the ratings and conditi ons shown below for dc characteristics and ac characteristics are within the range fo r normal operation and quality assurance. capacitance (t a = 25 c, regin = v dd = rv dd = v ss3 = v ss = cv ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions power supply voltage operation mode internal system clock frequency (f xx ) operating ambient temperature (t a ) regin v dd = rv dd direct mode 4 to 25 mhz ?40 to +85 c 3.3 v 0.3 v 5.0 v 0.5 v pll mode 4 to 40 mhz ?40 to +85 c 3.3 v 0.3 v 5.0 v 0.5 v caution when interfacing to the external devices using the clkout signal, make the internal system clock frequency (f xx ) 32 mhz or lower.
chapter 16 electrical specifications 638 user?s manual u15195ej5v0ud clock oscillator characteristics (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v) (a) ceramic resonator or crystal resonator connection x2 r d c2 c1 x1 parameter symbol conditions min. typ. max. unit oscillation frequency f x 4 6.4 mhz remarks 1. connect the oscillator as close to the x1 and x2 pins as possible. 2. do not wire any other signal lines in the area indicated by the broken lines. 3. for the resonator selection and oscillator constan t, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) external clock input open external clock high-speed cmos inverter x2 x1 cautions 1. connect the high-speed cmos in verter as close to th e x1 pin as possible. 2. thoroughly evaluate the matching between the v850e/ia2 and the high-speed cmos inverter. 3. when an internal regul ator is used, the external clock must not be used. this is because a malfunction may occur if the 3.3 v system volt age supplied by the internal regulator and the voltage of the external clock differ in potential. when using an external clock, do not use the internal regulator and externally supply the regin pin with a 3.3 v system voltage of the same potential as the external clock.
chapter 16 electrical specifications 639 user?s manual u15195ej5v0ud recommended oscillator constant (a) ceramic resonator (i) murata manufacturing co., ltd. (t a = ?40 to +85 c) oscillation frequency recommended circuit constant recommended voltage range type product name f x (mhz) c1 (pf) c2 (pf) r d ( ?) min. (v) max. (v) cstcr4m00g55-r0 4.0 on-chip on-chip 0 3.0 3.6 surface mount cstcr6m00g55-r0 6.0 on-chip on-chip 0 3.0 3.6 caution this oscillator constant is a reference va lue based on evaluation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is n ecessary in the ac tual application, apply to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and o scillation frequency indicate only os cillator character istics. use the v850e/ia2 so that the internal ope rating conditions are within the specifications of the dc and ac characteristics.
chapter 16 electrical specifications 640 user?s manual u15195ej5v0ud dc characteristics (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 pins for bus control note 1 2.2 v dd v v ih2 port pins note 2 0.7v dd v dd v v ih3 port pins other than notes 1, 2, reset pin 0.8v dd v dd v input voltage, high v ih4 x1 pin 0.8regin regin + 0.3 v v il1 pins for bus control note 1 0 0.8 v v il2 port pins note 2 0 0.3v dd v v il3 port pins other than notes 1, 2, reset pin 0 0.2v dd v input voltage, low v il4 x1 pin ?0.5 0.15regin v output voltage, high v oh i oh = ?2.5 ma v dd ? 1.0 v i ol = 15 ma 2.0 v v ol1 pwm output note 3 i ol = 2.5 ma 0.4 v output voltage, low v ol2 pins other than note 3 i ol = 2.5 ma 0.4 v input leakage current, high i lih v i = v dd 10 a input leakage current, low i lil v i = 0 v ?10 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ?10 a analog pin input leakage current i lian ani00 to ani05, ani10 to ani17 pins 10 a note 5 , pd703114 1.8f xx + 15 3.0f xx + 30 ma regin note 5 , pd70f3114 2.0f xx + 15 3.2f xx + 30 ma during normal operation i dd1 v dd + rv dd note 6 30 45 ma regin note 5 0.8f xx + 10 1.2f xx + 15 ma in halt mode i dd2 v dd + rv dd note 6 15 30 ma regin 8 15 ma in idle mode i dd3 v dd + rv dd note 6 0.5 1.0 ma pd703114 25 300 a regin pd70f3114 25 600 a power supply current note 4 in stop mode i dd4 v dd + rv dd note 6 30 60 a notes 1. ad0/pdl0 to ad15/pdl15, a16/pdh0 to a21/pd h5, lwr/pct0, uwr/pct1, rd/pct4, astb/pct6, wait/pcm0, clkout/pcm1 2. p31/txd0, p33/so1/txd1, p41/so0 3. to000 to to005, to010 to to015 4. value in the pll mode 5. determine the value by calculating f xx from the operating conditions. 6. the current of the to000 to to005 and to010 to to015 pins is not included. remark f xx : internal system clock frequency
chapter 16 electrical specifications 641 user?s manual u15195ej5v0ud data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit v dddr stop mode, regin = v dddr 1.5 3.6 v data retention voltage hv dddr stop mode, v dd = rv dd = hv dddr 3.6 5.5 v pd703114 25 300 a i dddr regin = v dddr pd70f3114 25 600 a data retention current hi dddr v dd = rv dd = hv dddr , note 1 30 60 a power supply voltage rise time t rvd 200 s power supply voltage fall time t fvd 200 s power supply voltage retention time (from stop mode setting) t hvd 0 ms stop release signal input time t drel 0 ns data retention input voltage, high v ihdr note 2 0.8hv dddr hv dddr v data retention input voltage, low v ildr note 2 0 0.2hv dddr v notes 1. the current of the to000 to to005 and to010 to to015 pins is not included. 2. p00/nmi, p01/eso0/intp0, p02/eso1/intp1, p03/adtrg0/intp2, p04/adtrg1/intp3, p05/intp4/to3off, p10/tiud10/to10, p1 1/tcud10/intp100, p12/tclr10/intp101, p20/ti2/intp20, p21/to21/intp21 to p24/to24/intp 24, p25/tclr2/intp25, p26/ti3/tclr3/intp30, p27/to3/intp31, p30/rxd0, p32/rxd1/si1, p34/asc k1/sck1, p40/si0, p42/sck0, mode0, mode1, cksel, reset caution enter or restore from the stop mode when regin = 3.0 to 3.6 v and v dd = rv dd = 4.5 to 5.5 v. remark the typ. value is a reference value for when t a = 25 c. t hvd v dddr , hv dddr t drel v ihdr v ihdr t fvd t rvd regin, v dd , rv dd stop mode release interrupt (nmi, etc.) (released by falling edge) stop mode release interrupt (nmi, etc.) (released by rising edge) stop mode setting reset (input) v ildr
chapter 16 electrical specifications 642 user?s manual u15195ej5v0ud ac characteristics (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) ac test input test points (a) other than (b), (c), and (d) below v dd 0 v 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points (b) p31/txd0, p33/so1/txd1, p41/so0 v dd 0 v 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd test points (c) ad0/pdl0 to ad15/pdl15, a16/pdh0 to a21/ pdh5, lwr/pct0, uwr/pct1, rd/pct4, astb/pct6, wait/pcm0, clkout/pcm1 v dd 0 v 2.2 v 0.8 v 2.2 v 0.8 v test points (d) x1 regin 0 v 0.8 regin 0.15 regin 0.8 regin 0.15 regin test points ac test output test points v dd 0 v 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points
chapter 16 electrical specifications 643 user?s manual u15195ej5v0ud load condition dut (device under test) c l = 50 pf caution in cases where the lo ad capacitance is greater than 50 pf due to the circuit configuration, insert a buffer or other elemen t to reduce the devi ce?s load capacitance to 50 pf or lower.
chapter 16 electrical specifications 644 user?s manual u15195ej5v0ud (1) clock timing (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit direct mode 20 125 ns x1 input cycle t cyx <1> pll mode 156 250 ns direct mode 6 ns x1 input high-level width t wxh <2> pll mode 50 ns direct mode 6 ns x1 input low-level width t wxl <3> pll mode 50 ns direct mode 4 ns x1 input rise time t xr <4> pll mode 10 ns direct mode 4 ns x1 input fall time t xf <5> pll mode 10 ns 4 40 mhz cpu operation frequency f xx ? clkout signal used note 4 32 mhz 25 250 ns clkout output cycle t cyk <6> clkout signal used note 31.25 250 ns clkout high-level width t wkh <7> 0.5t ? 9 ns clkout low-level width t wkl <8> 0.5t ? 11 ns clkout rise time t kr <9> 11 ns clkout fall time t kf <10> 9 ns delay time from x1 to clkout t dxk <11> direct mode 40 ns note when interfacing to the external devices using the cl kout signal, make the internal system clock frequency (f xx ) 32 mhz or lower. remark t = t cyk x1 <3> <1> <2> <4> <5> x1 (direct mode) ( pll mode) <5> <1> <2> <3> <4> <11> <11> clkout (output) <8> <9> <7> <10> <6>
chapter 16 electrical specifications 645 user?s manual u15195ej5v0ud (2) output waveform (except for clkout) (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit output rise time t or <12> 15 ns output fall time t of <13> 15 ns <13> <12> signals other than clkout (3) regulator output stabilization time (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v) parameter symbol conditions min. max. unit regulator output stabilization time t rg <14> external npn transistor: 2sd1950 (vl compliant product) or 2sd1581 stabilization capacitance: c = 22 f (electrolytic capacitor) bias resistance between b and e: r = 110 k ? 2 ms caution the regulator output stabilization time (t rg ) varies depending on the extern al transistor, stabilization capacitance, and bias resi stance between b and e. rv dd rv dd regin regin 4.5 v 3.3 v 0 v 0 v <14>
chapter 16 electrical specifications 646 user?s manual u15195ej5v0ud (4) reset timing (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit reset pin high-level width t wrsh <15> 500 ns at power-on 500 + t os + t rg ns at stop mode release note 500 + t os ns reset pin low-level width t wrsl <16> other than at power-on and at stop mode release 500 ns note release the stop mode in the range of regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v. caution thoroughly evaluate the oscillation stabilization time. remark t os : oscillation stabilization time t rg : regulator output stabilization time reset (input) <15> <16>
chapter 16 electrical specifications 647 user?s manual u15195ej5v0ud (5) multiplexed bus timing (a) clkout asynchronous (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb ) t sast <17> (0.5 + w as )t ? 16 ns address hold time (from astb ) t hsta <18> (0.5 + w ah )t ? 15 ns address float delay time from rd t frda <19> 11 ns data input setup time from address t said <20> (2 + w + w as + w ah )t ? 40 ns data input setup time from rd t srdid <21> (1 + w)t ? 40 ns delay time from astb to rd, lwr, uwr t dstrdwr <22> (0.5 + w ah )t ? 15 ns data input hold time (from rd ) t hrdid <23> 0 ns address output time from rd t drda <24> (1 + i)t ? 15 ns delay time from rd, lwr, uwr to astb t drdwrst <25> 0.5t ? 15 ns delay time from rd to astb t drdst <26> (1.5 + i + w as )t ? 15 ns rd, lwr, uwr low-level width t wrdwrl <27> (1 + w)t ? 22 ns astb high-level width t wsth <28> (1 + w as )t ? 15 ns data output time from lwr, uwr t dwrod <29> 10 ns data output setup time (to lwr, uwr ) t sodwr <30> (1 + w)t ? 25 ns data output hold time (from lwr, uwr ) t hwrod <31> t ? 20 ns t sawt1 <32> w 1 (1.5 + w as + w ah )t? 40 ns wait data output hold time (to address) t sawt2 <33> (1.5 + w + w as + w ah )t ? 40 ns t hawt1 <34> w 1 (0.5 + w + w as + w ah )t ns wait hold time (from address) t hawt2 <35> (1.5 + w + w as + w ah )t ns t sstwt1 <36> w 1 (1 + w ah )t ? 32 ns wait setup time (to astb ) t sstwt2 <37> (1 + w + w ah )t ? 32 ns t hstwt1 <38> w 1 (w + w ah )t ns wait hold time (from astb ) t hstwt2 <39> (1 + w + w ah )t ns remarks 1. t = t cyk 2. w as : number of address setup wait states (0 or 1) 3. w ah : number of address hold wait states (0 or 1) 4. w: number of wait clocks inserted in the bus cycle the sampling timing changes when a programmable wait is inserted. 5. i: number of idle states inse rted after the read cycle (0 or 1) 6. observe at least one of the data input hold times t hkid or t hrdid . 7. to understand how the number of wait cycles to be inserted is determined, refer to 4.6.3 relationship between programmable wa it and external wait.
chapter 16 electrical specifications 648 user?s manual u15195ej5v0ud (b) clkout synchronous (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout to address t dka <40> ?7 19 ns delay time from clkout to address float t fka <41> ?12 15 ns delay time from clkout to astb t dkst <42> ?3 + w ah t 19 + w ah t ns delay time from clkout to rd, lwr, uwr t dkrdwr <43> ?5 19 ns data input setup time (to clkout ) t sidk <44> 21 ns data input hold time (from clkout ) t hkid <45> 5 ns delay time from clkout to data output t dkod <46> 19 ns wait setup time (to clkout ) t swtk <47> 21 ns wait hold time (from clkout ) t hkwt <48> 5 ns remarks 1. t = t cyk 2. w ah : number of address hold wait states (0 or 1) 3. observe at least one of the data input hold times t hkid or t hrdid .
chapter 16 electrical specifications 649 user?s manual u15195ej5v0ud (c) read cycle (clkout syn chronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output) rd (output) ad0 to ad15 (i/o) astb (output) wait (input) t1 t2 tw t3 address hi-z <40> <20> <41> <42> <17> <28> <43> <22> <36> <38> <37> <39> <32> <34> <33> <35> <47> <47> <48> <21> <27> <19> <18> <44> <45> <42> <23> <43> <24> <26> <25> <48> data caution when using the clkout signal for interf acing with external devic es, set the internal system clock frequency (f xx ) to 32 mhz or lower. remark lwr and uwr are high level.
chapter 16 electrical specifications 650 user?s manual u15195ej5v0ud (d) write cycle (clkout synch ronous/asynchronous, 1 wait) clkout (output) ad0 to ad15 (i/o) astb (output) lwr (output) uwr (output) a16 to a21 (output) wait (input) t1 t2 tw t3 data address <40> <46> <42> <17> <18> <28> <42> <43> <22> <36> <47> <38> <37> <39> <32> <34> <33> <35> <48> <47> <48> <29> <30> <27> <43> <25> <31> caution when using the clkout signal for interf acing with external devic es, set the internal system clock frequency (f xx ) to 32 mhz or lower. remark rd is high level.
chapter 16 electrical specifications 651 user?s manual u15195ej5v0ud (6) interrupt timing (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit nmi high-level width t wnih <49> 500 ns nmi low-level width t wnil <50> 500 ns n = 0 to 4 500 ns n = 100, 101, 30, 31 5t + 10 ns n = 20 to 25 (when analog filter specified) 250 ns intpn high-level width t with <51> n = 20 to 25 (when digital filt er specified) 5t + 10 ns n = 0 to 4 500 ns n = 100, 101, 30, 31 5t + 10 ns n = 20 to 25 (when analog filter specified) 250 ns intpn low-level width t witl <52> n = 20 to 25 (when digital filt er specified) 5t + 10 ns remark t: digital filter sampling clock t can be selected by setting the following registers. ? intp100, intp101: can be selected from f xx /2, f xx /4, f xx /8, and f xx /16 by setting the nrc101 and nrc100 bits of the timer 10 noise elimination time select register (nrc10) (f xx : internal system clock). ? intp30: can be selected from f xxtm3 /2, f xxtm3 /4, f xxtm3 /8, and f xxtm3 /16 by setting the nrc31 and nrc30 bits of the timer 3 noise elimination time selection register (nrc3) (f xxtm3 : clock selected with the timer 3 clock selection register (prm03)). ? intp31: can be selected from f xxtm3 /32, f xxtm3 /64, f xxtm3 /128, and f xxtm3 /256 by setting the nrc33 and nrc32 bits of the nrc3 register (f xxtm3 : clock selected with the prm03 register). nmi (input) intpnv (input) <49> <50> <51> <52> remark n = 0 to 4, 100, 101, 20 to 25, 30, 31
chapter 16 electrical specifications 652 user?s manual u15195ej5v0ud (7) timer input timing (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. max. unit tiud10, tcud10 high-/low-level width t wudh , t wudl <53> 5t + 10 ns tiud10, tcud10 input time difference t phud <54> 5t + 10 ns n = 10, 2 (other than for through input), 3 5t + 10 ns tclrn high-/low-level width t wtch , t wtcl <55> n = 2 (for through input note ) 2t + 10 ns m = 2 (other than for through input), 3 5t + 10 ns tim high-/low-level width t wtih , t wtil <56> m = 2 (for through input note ) 2t + 10 ns note when setting the cese1 and cese0 bits of timer 2 count clock/control edge selection register 0 (cse0) to 1 and 0, respectively. remarks 1. t: digital filter sampling clock t can be selected by setting the following registers. ? tiud10, tcud10, tclr10: can be selected from f xx /2, f xx /4, f xx /8, and f xx /16 by setting the nrc101 and nrc100 bits of the timer 10 noise elimination time select register (nrc10). ? tclr2, ti2: fixed to f xx /2. ? tclr3, ti3: can be selected from f xxtm3 /2, f xxtm3 /4, f xxtm3 /8, and f xxtm3 /16 by setting the nrc31 and nrc30 bits of the timer 3 noise eliminatio n time selection register (nrc3) (f xxtm3 : clock selected with the timer 3 clock selection register (prm03)). 2. f x : internal system clock frequency <53> tiud10 (input) tcud10 (input) tclrn (input) tim (input) <53> <53> <53> <54> <54> <54> <54> <55> <55> <56> <56> remark n = 10, 2, 3 m = 2, 3
chapter 16 electrical specifications 653 user?s manual u15195ej5v0ud (8) timer operating frequency (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit timer 00, timer 01 operating frequency t 0 40 mhz timer 10 operating frequency t 1 20 mhz timer 20, timer 21 operating frequency t 2 20 mhz timer 3 operating frequency t 3 32 mhz remarks 1. t 0 : f xx or f xx /2 can be selected using the timer 0 clock selection register (prm01). t 1 : select f xx /2 by setting the timer 1/timer 2 clo ck selection register (prm02) to 01h. t 2 : select f xx /2 by setting the timer 1/timer 2 clo ck selection register (prm02) to 01h. t 3 : f xx or f xx /2 can be selected using the timer 3 clock selection register (prm03). 2. f xx : internal system clock frequency (9) csi timing (1/2) (a) master mode (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle t cysk1 <57> output 200 ns sckn high-level width t wsk1h <58> output 0.5t cysk1 ? 25 ns sckn low-level width t wsk1l <59> output 0.5t cysk1 ? 25 ns sin setup time (to sckn ) t ssisk <60> 35 ns sin hold time (from sckn ) t hsksi <61> 30 ns son output delay time (from sckn ) t dskso <62> 30 ns son output hold time (from sckn ) t hskso <63> 0.5t cysk1 ? 20 ns remark n = 0, 1 (b) slave mode (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle t cysk1 <57> input 200 ns sckn high-level width t wsk1h <58> input 90 ns sckn low-level width t wsk1l <59> input 90 ns sin setup time (to sckn ) t ssisk <60> 50 ns sin hold time (from sckn ) t hsksi <61> 50 ns son output delay time (from sckn ) t dskso <62> 50 ns son output hold time (from sckn ) t hskso <63> t wsk1h ns remark n = 0, 1
chapter 16 electrical specifications 654 user?s manual u15195ej5v0ud (9) csi timing (2/2) <57> <59> <58> <60> <61> <62> <63> sin (input) son (output) sckn (i/o) output data input data remarks 1. the broken lines indicate high impedance. 2. n = 0, 1 (10) uart0 timing (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit uart0 baud rate generator input frequency f brg 20 mhz remarks 1. uart0 baud rate generator input frequency (f brg ): can be selected from f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512, f xx /1024, and f xx /2048 by setting the tps3 to tps0 bits of clock select register 0 (cksr0). 2. f xx : internal system clock frequency
chapter 16 electrical specifications 655 user?s manual u15195ej5v0ud (11) uart1 timing (1/2) (a) clocked master mode (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit asck1 cycle t cysk0 <64> output 1000 ns asck1 high-level width t wsk0h <65> output kt ? 20 ns asck1 low-level width t wsk0l <66> output kt ? 20 ns rxd1 setup time (to asck1 ) t srxsk <67> 1.5t + 35 ns rxd1 hold time (from asck1 ) t hskrx <68> 0 ns txd1 output delay time (from asck1 ) t dsktx <69> t + 10 ns txd1 output hold time (from asck1 ) t hsktx <70> (k + 1)t ? 20 ns remarks 1. t = 2t cyk 2. k: setting value of prescaler compare register 1 (prscm1) of uart1 (b) clocked slave mode (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit asck1 cycle t cysk0 <64> input 1000 ns asck1 high-level width t wsk0h <65> input 4t + 80 ns asck1 low-level width t wsk0l <66> input 4t + 80 ns rxd1 setup time (to asck1 ) t srxsk <67> t + 10 ns rxd1 hold time (from asck1 ) t hskrx <68> t + 10 ns txd1 output delay time (from asck1 ) t dsktx <69> 2.5t + 45 ns txd1 output hold time (from asck1 ) t hsktx <70> (k + 1.5)t ns remarks 1. t = 2t cyk 2. k: setting value of prescaler compare register 1 (prscm1) of uart1
chapter 16 electrical specifications 656 user?s manual u15195ej5v0ud (11) uart1 timing (2/2) <64> <66> <65> <67> <68> <69> <70> rxd1 (input) txd1 (output) asck1 (i/o) output data input data
chapter 16 electrical specifications 657 user?s manual u15195ej5v0ud a/d converter characteristics (t a = ?40 to +85 c, regin = 3.0 to 3.6 v, av dd = v dd = rv dd = 5 .0 v 0.5 v, v ss = v ss3 = v ss = cv ss = 0 v, c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution ? 10 bit overall error note 1 ? 4 lsb quantization error ? 1/2 lsb conversion time t conv 5 10 s sampling time t samp 833 ns zero-scale error note 1 ? 4 lsb full-scale error note 1 ? 4 lsb differential linearity error note 1 ? 4 lsb integral linearity error note 1 ? 4 lsb analog input voltage v ian ?0.3 av dd + 0.3 v analog reference voltage av dd 4.5 5.5 v avdd power supply current note 2 ai dd 4 8 ma notes 1. quantization error ( 0.5 lsb) is not included. 2. the v850e/ia2 incorporates two a/d converters. this is the rated value for one converter. remark lsb: least significant bit
chapter 16 electrical specifications 658 user?s manual u15195ej5v0ud 16.2 flash memory programming mode basic characteristics (t a =10 to 40 c (during rewrite), t a = ?40 to +85 c (except during rewrite), regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v) parameter symbol conditions min. typ. max. unit operating frequency f x 4 40 mhz v pp1 during flash memory programming 7.5 7.8 8.1 v v ppl v pp low-level detection ? 0.3 0.2regin v v ppm v pp , regin level detection 0.65regin regin + 0.3 v v pp supply voltage v pph v pp high-voltage level detection 7.5 7.8 8.1 v v dd3 supply current i dd1 v pp = v pp1 3.2f xx + 30 ma v pp supply current i pp v pp = 7.8 v 100 ma step erase time t er note 1 0.398 0.4 0.402 s overall erase time t era when the step erase time = 0.4 s, note 2 40 s write-back time t wb note 3 0.99 1 1.01 ms number of write-backs per write-back command c wb when the write-back time = 1 ms, note 4 300 count/ write-back command number of erase/write-backs c erwb 16 count step writing time t wt note 5 18 20 22 s overall writing time per word t wtw when the step writing time = 20 s (1 word = 4 bytes), note 6 20 200 s/word number of rewrites c erwr 1 erase + 1 write after erase = 1 rewrite, note 7 100 count notes 1. the recommended setting value of the step erase time is 0.4 s. 2. the prewrite time prior to erasure and the eras e verify time (write-back time) are not included. 3. the recommended setting value of the write-back time is 1 ms. 4. write-back is executed once by the issuance of the write-back command. therefore, the retry count must be the maximum value minus the number of commands issued. 5. the recommended setting value of the step writing time is 20 s. 6. 20 s is added to the actual writing time per word. the in ternal verify time during and after the writing is not included. 7. when writing initially to shipped products, it is c ounted as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remark when the pg-fp4 is used, a time parameter required fo r writing/erasing by downloading parameter files is automatically set. do not change the settings unless otherwise specified.
chapter 16 electrical specifications 659 user?s manual u15195ej5v0ud serial write operation characteristics (t a = 10 to +40 c, regin = 3.0 to 3.6 v, v dd = rv dd = 5.0 v 0.5 v, v ss3 = v ss = cv ss = 0 v) parameter symbol conditions min. typ. max. unit v dd to v pp set time <71> t drpsr t rg + 0.01 ms v pp to reset set time <72> t psrrf 1 s reset to v pp count start time <73> t rfof v pp = 7.8 v 10t + 1500 ns count execution time <74> t count 15 ms v pp counter high-level width <75> t ch 1 s v pp counter low-level width <76> t cl 1 s v pp counter rise time <77> t r 1 s v pp counter fall time <78> t f 1 s v pp to regin reset time <79> t pfdr 10 s remarks 1. t rg : regulator output stabilization time 2. t = t cyk <73> <76> <75> <74> <78> <77> 0 v 0 v reset (input) <72> <79> 0 v 4.5 v regin v dd v dd v pp regin v dd v pp 0 v 3.0 v <71>
660 user?s manual u15195ej5v0ud chapter 17 package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 ? 0.04 m 0.17 + 0.03 ? 0.07 r3 + 7 ? 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
chapter 17 package drawings 661 user?s manual u15195ej5v0ud 80 81 50 100 1 31 30 51 100-pin plastic qfp (14x20) hi j detail of lead end m q r k m l p s s n g f note each lead centerline is located within 0.15 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 23.6 0.4 20.0 0.2 0.30 0.10 0.6 h 17.6 0.4 i c 14.0 0.2 0.15 j 0.65 (t.p.) k 1.8 0.2 l 0.8 0.2 f 0.8 p100gf-65-3ba1-4 n p q 0.10 2.7 0.1 0.1 0.1 r5 5 s 3.0 max. m 0.15 + 0.10 ? 0.05 c d a b s
662 user?s manual u15195ej5v0ud chapter 18 recommended soldering conditions the pd703114 and 70f3114 should be soldered and mounted under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 18-1. surface mounting ty pe soldering conditions (1) pd703114gc- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd703114gc(a)- -8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3114gc-8eu: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3114gc(a)-8eu: 100-pin plastic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: twice or less exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) ir35-107-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: twice or less exposure limit: 7 days note (after that, prebake at 125c for 10 to 72 hours) vp15-107-2 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? (2) pd703114gf- -3ba: 100-pin plastic qfp (14 20) pd70f3114gf-3ba: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: twice or less exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir35-207-2 vps package peak temperature: 215c, time: 25 to 40 seconds (at 200c or higher), count: twice or less exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) vp15-207-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once preheating temperature: 120c max. (package surface temperature) exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ws60-207-1 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ?
chapter 18 recommended soldering conditions 663 user?s manual u15195ej5v0ud (3) pd703114gc- -8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd703114gc(a)- -8eu-a: 100-pin plastic lqfp (fine pitch) (14 14) pd70f3114gc-8eu-a: 100-pin plast ic lqfp (fine pitch) (14 14) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less exposure limit: 7 days note (after that, prebake at 125c for 20 to 72 hours) ir60-207-3 wave soldering for details, consult an nec electronics sales representative. ? partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? (4) pd703114gf- -3ba-a: 100-pin plastic qfp (14 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260c, time: 60 seconds max. (at 220c or higher), count: three times or less exposure limit: 3 days note (after that, prebake at 125c for 20 to 72 hours) ir60-203-3 wave soldering for details, consult an nec electronics sales representative. ? partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). remarks 1. products with -a at the end of the part number are lead-free products. 2. for soldering methods and conditions other than those recommended above, consult an nec electronics sales representative. 3. for soldering conditions for the pd70f3114gc(a)-8eu-a and 70f3114gf-3ba-a, consult an nec electronics sales representative.
664 user?s manual u15195ej5v0ud appendix a notes on target system design the following shows a diagram of the connection condi tions between the in-circuit emulator option board and conversion connector. design your system making allowanc es for conditions such as the form of parts mounted on the target system as shown below. figure a-1. 100-pin plastic lqfp (fine pitch) (14 14) side view target system nqpack100sd yqpack100sd 231.26 mm note in-circuit emulator option board conversion connector ie-703114-mc-em1 in-circuit emulator ie-v850e-mc yqguide note yqsocket100sdn (sold separately) can be inse rted here to adjust the height (height: 3.2 mm). top view target system yqpack100sd, nqpack100sd, yqguide ie-703114-mc-em1 ie-v850e-mc connection condition diagram 13.3 mm 28.7445 mm 21.58 mm 17.9955 mm 75 mm 31.84 mm target system nqpack100sd yqpack100sd ie-703114-mc-em1 connect to ie-v850e-mc. yqguide
appendix a notes on target system design 665 user?s manual u15195ej5v0ud figure a-2. 100-pin plastic qfp (14 20) side view target system nqpack100rb yqpack100rb nexb-2r100sd/rb conversion connector yqguide 231.26 mm note in-circuit emulator option board ie-703114-mc-em1 in-circuit emulator ie-v850e-mc note yqsocket100sdn (sold separately) can be insert ed here to adjust the height (height: 3.2 mm). top view target system yqpack100rb, nqpack100rb, yqguide ie-703114-mc-em1 ie-v850e-mc nexb-2r100sd/rb 8 mm 20.7 mm pin 1 position connection condition diagram 33.2 mm 28.7 mm 18.5 mm 20 mm 38 mm target system nqpack100rb yqpack100rb ie-703114-mc-em1 connect to ie-v850e-mc. nexb-2r100sd/rb 75 mm pin 1 position
666 user?s manual u15195ej5v0ud appendix b register index (1/9) symbol register name unit page adcr00 a/d conversion result register 00 adc 521 adcr01 a/d conversion result register 01 adc 521 adcr02 a/d conversion result register 02 adc 521 adcr03 a/d conversion result register 03 adc 521 adcr04 a/d conversion result register 04 adc 521 adcr05 a/d conversion result register 05 adc 521 adcr10 a/d conversion result register 10 adc 521 adcr11 a/d conversion result register 11 adc 521 adcr12 a/d conversion result register 12 adc 521 adcr13 a/d conversion result register 13 adc 521 adcr14 a/d conversion result register 14 adc 521 adcr15 a/d conversion result register 15 adc 521 adcr16 a/d conversion result register 16 adc 521 adcr17 a/d conversion result register 17 adc 521 adetm0 a/d voltage detection mode register 0 adc 520 adetm0h a/d voltage detection mode register 0h adc 520 adetm0l a/d voltage detection mode register 0l adc 520 adetm1 a/d voltage detection mode register 1 adc 520 adetm1h a/d voltage detection mode register 1h adc 520 adetm1l a/d voltage detection mode register 1l adc 520 adic0 interrupt control register intc 150 adic1 interrupt control register intc 150 adscm00 a/d scan mode register 00 adc 517 adscm00h a/d scan mode register 00h adc 517 adscm00l a/d scan mode register 00l adc 517 adscm01 a/d scan mode register 01 adc 519 adscm01h a/d scan mode register 01h adc 519 adscm01l a/d scan mode register 01l adc 519 adscm10 a/d scan mode register 10 adc 517 adscm10h a/d scan mode register 10h adc 517 adscm10l a/d scan mode register 10l adc 517 adscm11 a/d scan mode register 11 adc 519 adscm11h a/d scan mode register 11h adc 519 adscm11l a/d scan mode register 11l adc 519 asif0 asynchronous serial interface mode transmit status register 0 uart0 415 asim0 asynchronous serial interface mode register 0 uart0 411 asim10 asynchronous serial interface mode register 10 uart1 442 asim11 asynchronous serial interface mode register 11 uart1 444
appendix b register index 667 user?s manual u15195ej5v0ud (2/9) symbol register name unit page asis0 asynchronous serial interface status register 0 uart0 414 asis1 asynchronous serial interface status register 1 uart1 445 awc address wait control register bcu 95 bcc bus cycle control register bcu 97 bct0 bus cycle type configuration register 0 bcu 85 bct1 bus cycle type configuration register 1 bcu 85 bfcm00 buffer register cm00 tm00 202 bfcm01 buffer register cm01 tm00 202 bfcm02 buffer register cm02 tm00 202 bfcm03 buffer register cm03 tm00 204 bfcm04 buffer register cm04 tm00 202 bfcm05 buffer register cm05 tm00 202 bfcm10 buffer register cm10 tm01 202 bfcm11 buffer register cm11 tm01 202 bfcm12 buffer register cm12 tm01 202 bfcm13 buffer register cm13 tm01 204 bfcm14 buffer register cm14 tm01 202 bfcm15 buffer register cm15 tm01 202 brgc0 baud rate generator control register 0 uart0 433 bsc bus size configuration register bcu 87 cc100 capture/compare register 100 tm10 308 cc101 capture/compare register 101 tm10 309 cc10ic0 interrupt control register intc 150 cc10ic1 interrupt control register intc 150 cc2ic0 interrupt control register intc 150 cc2ic1 interrupt control register intc 150 cc2ic2 interrupt control register intc 150 cc2ic3 interrupt control register intc 150 cc2ic4 interrupt control register intc 150 cc2ic5 interrupt control register intc 150 cc30 capture/compare register 30 tm3 371 cc31 capture/compare register 31 tm3 371 cc3ic0 interrupt control register intc 150 cc3ic1 interrupt control register intc 150 ccr0 capture/compare control register 0 tm10 302 ccstate0 timer 2 capture/compare 1 to 4 status register 0 tm2 344 ccstate0h timer 2 capture/compare 1 to 4 status register 0h tm2 344 ccstate0l timer 2 capture/compare 1 to 4 status register 0l tm2 344 ckc clock control register cg 177 cksr0 clock select register 0 uart0 432 cm000 compare register 000 tm00 201
appendix b register index 668 user?s manual u15195ej5v0ud (3/9) symbol register name unit page cm001 compare register 001 tm00 202 cm002 compare register 002 tm00 202 cm003 compare register 003 tm00 202 cm004 compare register 004 tm00 202 cm005 compare register 005 tm00 202 cm00ic1 interrupt control register intc 150 cm010 compare register 010 tm01 201 cm011 compare register 011 tm01 201 cm012 compare register 012 tm01 201 cm013 compare register 013 tm01 202 cm014 compare register 014 tm01 202 cm015 compare register 015 tm01 202 cm01ic1 interrupt control register intc 150 cm02ic1 interrupt control register intc 150 cm03ic0 interrupt control register intc 150 cm03ic1 interrupt control register intc 150 cm04ic0 interrupt control register intc 150 cm04ic1 interrupt control register intc 150 cm05ic0 interrupt control register intc 150 cm05ic1 interrupt control register intc 150 cm100 compare register 100 tm10 307 cm101 compare register 101 tm10 307 cm10ic0 interrupt control register intc 150 cm10ic1 interrupt control register intc 150 cm4 compare register 4 tm4 398 cm4ic0 interrupt control register intc 150 cmse050 timer 2 subchannel 0, 5 captur e/compare control register tm2 338 cmse120 timer 2 subchannel 1, 2 captur e/compare control register tm2 339 cmse340 timer 2 subchannel 3, 4 captur e/compare control register tm2 341 csc0 chip area selection control register bcu 82 csc1 chip area selection control register bcu 82 csce0 timer 2 software event capture register tm2 346 cse0 timer 2 count clock/control edge selection register 0 tm2 331 cse0h timer 2 count clock/control edge selection register 0h tm2 331 cse0l timer 2 count clock/contro l edge selection register 0l tm2 331 csic0 clocked serial interface cl ock selection register 0 csi0 480 csic1 clocked serial interface cl ock selection register 1 csi1 480 csiic0 interrupt control register intc 150 csiic1 interrupt control register intc 150 csim0 clocked serial interf ace mode register 0 csi0 478 csim1 clocked serial interf ace mode register 1 csi1 478
appendix b register index 669 user?s manual u15195ej5v0ud (4/9) symbol register name unit page csl10 cc101 capture input selection register tm10 306 cvpe10 timer 2 subchannel 1 main capture/compare register tm2 328 cvpe20 timer 2 subchannel 2 main capture/compare register tm2 328 cvpe30 timer 2 subchannel 3 main capture/compare register tm2 328 cvpe40 timer 2 subchannel 4 main capture/compare register tm2 328 cvse00 timer 2 subchannel 0 capture/compare register tm2 328 cvse10 timer 2 subchannel 1 sub capture/compare register tm2 329 cvse20 timer 2 subchannel 2 sub capture/compare register tm2 329 cvse30 timer 2 subchannel 3 sub capture/compare register tm2 329 cvse40 timer 2 subchannel 4 sub capture/compare register tm2 329 cvse50 timer 2 subchannel 5 capture/compare register tm2 329 dadc0 dma addressing control register 0 dmac 112 dadc1 dma addressing control register 1 dmac 112 dadc2 dma addressing control register 2 dmac 112 dadc3 dma addressing control register 3 dmac 112 dbc0 dma transfer count register 0 dmac 111 dbc1 dma transfer count register 1 dmac 111 dbc2 dma transfer count register 2 dmac 111 dbc3 dma transfer count register 3 dmac 111 dchc0 dma channel control register 0 dmac 114 dchc1 dma channel control register 1 dmac 114 dchc2 dma channel control register 2 dmac 114 dchc3 dma channel control register 3 dmac 114 dda0h dma destination address register 0h dmac 109 dda0l dma destination address register 0l dmac 110 dda1h dma destination address register 1h dmac 109 dda1l dma destination address register 1l dmac 110 dda2h dma destination address register 2h dmac 109 dda2l dma destination address register 2l dmac 110 dda3h dma destination address register 3h dmac 109 dda3l dma destination address register 3l dmac 110 ddis dma disable status register dmac 116 detic0 interrupt control register intc 150 detic1 interrupt control register intc 150 dmaic0 interrupt control register intc 150 dmaic1 interrupt control register intc 150 dmaic2 interrupt control register intc 150 dmaic3 interrupt control register intc 150 drst dma restart register dmac 116 dsa0h dma source address register 0h dmac 107 dsa0l dma source address register 0l dmac 108
appendix b register index 670 user?s manual u15195ej5v0ud (5/9) symbol register name unit page dsa1h dma source address register 1h dmac 107 dsa1l dma source address register 1l dmac 108 dsa2h dma source address register 2h dmac 107 dsa2l dma source address register 2l dmac 108 dsa3h dma source address register 3h dmac 107 dsa3l dma source address register 3l dmac 108 dtfr0 dma trigger factor register 0 dmac 117 dtfr1 dma trigger factor register 1 dmac 117 dtfr2 dma trigger factor register 2 dmac 117 dtfr3 dma trigger factor register 3 dmac 117 dtm00 dead time timer 00 tm00 201 dtm01 dead time timer 01 tm00 201 dtm02 dead time timer 02 tm00 201 dtm10 dead time timer 10 tm01 201 dtm11 dead time timer 11 tm01 201 dtm12 dead time timer 12 tm01 201 dtrr0 dead time timer reload register 0 tm00 201 dtrr1 dead time timer reload register 1 tm00 201 dwc0 data wait control register 0 bcu 94 dwc1 data wait control register 1 bcu 94 fem0 timer 2 input filter mode register 0 tm2 160, 586 fem1 timer 2 input filter mode register 1 tm2 160, 586 fem2 timer 2 input filter mode register 2 tm2 160, 586 fem3 timer 2 input filter mode register 3 tm2 160, 586 fem4 timer 2 input filter mode register 4 tm2 160, 586 fem5 timer 2 input filter mode register 5 tm2 160, 586 flpmc flash programming mode control register cpu 624 imr0 interrupt mask register 0 intc 153 imr0h interrupt mask register 0h intc 153 imr0l interrupt mask register 0l intc 153 imr1 interrupt mask register 1 intc 153 imr1h interrupt mask register 1h intc 153 imr1l interrupt mask register 1l intc 153 imr2 interrupt mask register 2 intc 153 imr2h interrupt mask register 2h intc 153 imr2l interrupt mask register 2l intc 153 imr3 interrupt mask register 3 intc 153 imr3h interrupt mask register 3h intc 153 imr3l interrupt mask register 3l intc 153 intm0 external interrupt mode register 0 intc 142 intm1 external interrupt mode register 1 intc 156
appendix b register index 671 user?s manual u15195ej5v0ud (6/9) symbol register name unit page intm2 external interrupt mode register 2 intc 156 ispr in-service priority register intc 154 itrg0 a/d internal trigger selection register 0 adc 524 itrg1 a/d internal trigger selection register 1 adc 524 lockr lock register cpu 180 nrc10 timer 10 noise elimination ti me selection register tm10 583 nrc3 timer 3 noise elimination ti me selection register tm3 584 octle0 timer 2 output control register tm2 336 octle0h timer 2 output control register 0h tm2 336 octle0l timer 2 output control register 0l tm2 336 odele0 timer 2 output delay register tm2 345 odele0h timer 2 output delay register 0h tm2 345 odele0l timer 2 output delay register 0l tm2 345 p0 port 0 port 563 p0ic0 interrupt control register intc 150 p0ic1 interrupt control register intc 150 p0ic2 interrupt control register intc 150 p0ic3 interrupt control register intc 150 p0ic4 interrupt control register intc 150 p1 port 1 port 564 p2 port 2 port 566 p3 port 3 port 568 p4 port 4 port 570 pcm port cm port 579 pct port ct port 576 pdh port dh port 572 pdl port dl port 574 pdlh port dlh port 574 pdll port dll port 574 pfc1 port 1 function control register port 565 pfc2 port 2 function control register port 567 pfc3 port 3 function control register port 569 phcmd peripheral command register cpu 176 phs peripheral status register cpu 179 pm1 port 1 mode register port 564 pm2 port 2 mode register port 566 pm3 port 3 mode register port 568 pm4 port 4 mode register port 571 pmc1 port 1 mode control register port 565 pmc2 port 2 mode control register port 567 pmc3 port 3 mode control register port 569
appendix b register index 672 user?s manual u15195ej5v0ud (7/9) symbol register name unit page pmc4 port 4 mode control register port 571 pmccm port cm mode control register port 579 pmcct port ct mode control register port 577 pmcdh port dh mode control register port 573 pmcdl port dl mode control register port 575 pmcdlh port dl mode control register h port 575 pmcdll port dl mode control register l port 575 pmcm port cm mode register port 579 pmct port ct mode register port 577 pmdh port dh mode register port 573 pmdl port dl mode register port 575 pmdlh port dl mode register h port 575 pmdll port dl mode register l port 575 poer0 pwm output enable register 0 tm00 218 poer1 pwm output enable register 1 tm01 218 prcmd command register cpu 184 prm01 timer 0 clock selection register tm0 205 prm02 timer 1/timer 2 clock sele ction register tm1/tm2 299, 330 prm03 timer 3 clock selection register tm3 373 prm10 prescaler mode register 10 tm10 305 prscm1 prescaler compare register 1 uart1 469 prscm3 prescaler compare register 3 csi0, csi1 510 prsm1 prescaler mode register 1 uart1 467 prsm3 prescaler mode register 3 csi0, csi1 509 psc power save control register cpu 185 psmr power save mode register cpu 184 psto0 pwm software timing output register 0 tm00 219 psto1 pwm software timing output register 1 tm01 219 regc regulator control register regulator 602 rxb0 receive buffer register uart0 416 rxb1 2-frame continuous recept ion buffer registers 1 uart1 447 rxbl1 receive buffer register l1 uart1 447 seic0 interrupt control register intc 150 sesa10 signal edge selection register 10 intc, tm10 157, 303 sesc valid edge selection register intc, tm3 159, 378 sese0 timer 2 subchannel input event edge selection register tm2 332 sese0h timer 2 subchannel input event edge selection register 0h tm2 332 sese0l timer 2 subchannel input event edge selection register 0l tm2 332 sio0 serial i/o shift register 0 csi0 490 sio1 serial i/o shift register 1 csi1 490 siol0 serial i/o shift register l0 csi0 491
appendix b register index 673 user?s manual u15195ej5v0ud (8/9) symbol register name unit page siol1 serial i/o shift register l1 csi1 491 sirb0 clocked serial interface re ceive buffer register 0 csi0 482 sirb1 clocked serial interface re ceive buffer register 1 csi1 482 sirbe0 clocked serial interface read- only receive buffer register 0 csi0 484 sirbe1 clocked serial interface read- only receive buffer register 1 csi1 484 sirbel0 clocked serial interface read- only receive buffer register l0 csi0 485 sirbel1 clocked serial interface read- only receive buffer register l1 csi1 485 sirbl0 clocked serial interface re ceive buffer register l0 csi1 483 sirbl1 clocked serial interface re ceive buffer register l1 csi0 483 sotb0 clocked serial interface tr ansmit buffer register 0 csi1 486 sotb1 clocked serial interface tr ansmit buffer register 1 csi0 486 sotbf0 clocked serial interface init ial transmit buffer register 0 csi1 488 sotbf1 clocked serial interface init ial transmit buffer register 1 csi0 488 sotbfl0 clocked serial interface init ial transmit buffer register l0 csi1 489 sotbfl1 clocked serial interface init ial transmit buffer register l1 csi0 489 sotbl0 clocked serial interface tr ansmit buffer register l0 csi1 487 sotbl1 clocked serial interface tr ansmit buffer register l1 csi0 487 spec0 tomr write enable register 0 tm00 228 spec1 tomr write enable register 1 tm01 228 sric0 interrupt control register intc 150 sric1 interrupt control register intc 150 status0 status register 0 tm10 306 stic0 interrupt control register intc 150 stic1 interrupt control register intc 150 stopte0 timer 2 clock st op register 0 tm2 330 stopte0h timer 2 clock st op register 0h tm2 330 stopte0l timer 2 clock st op register 0l tm2 330 tbstate0 timer 2 timer base status register 0 tm2 343 tbstate0h timer 2 timer base status register 0h tm2 343 tbstate0l timer 2 timer base status register 0l tm2 343 tcre0 timer 2 time base control register 0 tm2 333 tcre0h timer 2 time base control register 0h tm2 333 tcre0l timer 2 time base control register 0l tm2 333 tm00 timer 00 tm00 200 tm01 timer 01 tm01 200 tm0ic0 interrupt control register intc 150 tm0ic1 interrupt control register intc 150 tm10 timer 10 tm10 297 tm20 timer 20 tm2 328 tm21 timer 21 tm2 328 tm2ic0 interrupt control register intc 150
appendix b register index 674 user?s manual u15195ej5v0ud (9/9) symbol register name unit page tm2ic1 interrupt control register intc 150 tm3 timer 3 tm3 370 tm3ic0 interrupt control register intc 150 tm4 timer 4 tm4 397 tmc00 timer control register 00 tm00 206 tmc00h timer control register 00h tm00 206 tmc00l timer control register 00l tm00 206 tmc01 timer control register 01 tm01 206 tmc01h timer control register 01h tm01 206 tmc01l timer control register 01l tm01 206 tmc10 timer control register 10 tm10 301 tmc30 timer control register 30 tm3 374 tmc31 timer control register 31 tm3 376 tmc4 timer control register 4 tm4 400 tmic0 timer connection select ion register 0 tm1/tm2 405 to3c timer 3 output control register tm3 379 tomr0 timer output mode register 0 tm00 213 tomr1 timer output mode register 1 tm01 213 tuc00 timer unit control register 00 tm00 212 tuc01 timer unit control register 01 tm01 212 tum0 timer unit mode register 0 tm10 300 txb0 transmit buffer register 0 uart0 417 txs1 2-frame continuous transm ission shift register 1 uart1 450 txsl1 transmit shift register l1 uart1 450 vswc system wait control register bcu 78
675 user?s manual u15195ej5v0ud appendix c instruction set list c.1 conventions (1) symbols used in operand descriptions symbol explanation reg1 general-purpose register (used as source register) reg2 general-purpose register (usually used as destinat ion register. used as source register in some instructions.) reg3 general-purpose register (usually stores rema inder of division result or higher 32 bits of multiplication result.) bit#3 3-bit data for bit number specification immx x-bit immediate data dispx x-bit displacement data regid system register number vector 5-bit data that specifies a trap vector (00h to 1fh) cccc 4-bit data that shows a condition code sp stack pointer (r3) ep element pointer (r30) list x-item register list (2) symbols used in operands symbol explanation r 1 bit of data of code that specifies reg1 or regid r 1 bit of data of code that specifies reg2 w 1 bit of data of code that specifies reg3 d 1 bit of data of a displacement i 1 bit of immediate data (shows higher bit of immediate data) i 1 bit of immediate data cccc 4-bit data that shows a condition code cccc 4-bit data that shows condition code of bcond instruction bbb 3-bit data for bit number specification l 1 bit of data that specifies a pr ogram register in a register list s 1 bit of data that specifies a system register in a register list
appendix c instruction set list 676 user?s manual u15195ej5v0ud (3) symbols used in operations symbol explanation assignment gr [ ] general-purpose register sr [ ] system register zero-extend (n) zero-extend n to word length. sign-extend (n) sign-extend n to word length. load-memory (a, b) read data of size ?b? from address ?a?. store-memory (a, b, c) write data ?b? of size ?c? to address ?a?. load-memory-bit (a, b) read bit ?b? of address ?a?. store-memory-bit (a, b, c) write ?c? in bit ?b? of address ?a?. saturated (n) perform saturation proces sing of n (n is 2?s complement). if n is a computation result and n > 7fffffffh, make n = 7fffffffh. if n is a computation result and n < 80000000h, make n = 80000000h. result reflect result in flag. byte byte (8 bits) half-word halfword (16 bits) word word (32 bits) + addition ? subtraction || bit concatenation multiplication division % remainder of division result and logical product or logical sum xor exclusive logical sum not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) symbols used in execution clock symbol explanation i when executing another instruction immediat ely after instruction execution (issue). r when repeating same instruction immediat ely after instruction execution (repeat) | when using instruction execution result in inst ruction immediately afte r instruction execution (latency)
appendix c instruction set list 677 user?s manual u15195ej5v0ud (5) symbols used in flag operations symbol explanation (blank) no change 0 clear to 0. set or cleared according to result. r previously saved value is restored. (6) condition codes condition name (cond) condition code (cccc) condition expression explanation v 0000 ov = 1 overflow nv 1000 ov = 0 no overflow c/l 0001 cy = 1 carry lower (less than) nc/nl 1001 cy = 0 no carry no lower (greater than or equal) z/e 0010 z = 1 zero equal nz/ne 1010 z = 0 not zero not equal nh 0011 (cy or z) = 1 not higher (less than equal) h 1011 (cy or z) = 0 higher (greater than) n 0100 s = 1 negative p 1100 s = 0 positive t 0101 ? always (unconditional) sa 1101 sat = 1 saturated lt 0110 (s xor ov) = 1 less then signed ge 1110 (s xor ov) = 0 greater than or equal signed le 0111 ((s xor ov) or z) = 1 less than or equal signed gt 1111 ((s xor ov) or z) = 0 greater than signed
appendix c instruction set list 678 user?s manual u15195ej5v0ud c.2 instruction set (alphabetical order) (1/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat reg1, reg2 r r r r r 0 0 1 1 1 0 r r r r r gr[reg2] gr[reg2] + gr[reg1] 1 1 1 add imm5, reg2 r r r r r 0 1 0 0 1 0 i i i i i gr[reg2] gr[reg2] + sign-extend (imm5) 1 1 1 imm16, r r r r r 1 1 0 0 0 0 r r r r r gr[reg2] gr[reg1] + sign-extend (imm16) addi reg1, reg2 i i i i i i i i i i i i i i i i 1 1 1 and reg1, reg2 r r r r r 0 0 1 0 1 0 r r r r r gr[reg2] gr[reg2] and gr[reg1] 1 1 1 0 r r r r r 1 1 0 1 1 0 r r r r r 1 1 1 0 0 andi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] and zero-extend (imm 16) d d d d d 1 0 1 1 d d d c c c c conditions satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 if conditions are satisfied then pc pc + sign extend (disp9) conditions not satisfied 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 bsh reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 0 1 0 gr[reg3] gr[reg2] (23:16) || gr[reg2] (31:24)||gr [reg2] (7:0)||gr[reg2] (15:8) r r r r r 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 bsw reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 0 0 0 gr[reg3] gr[reg2] (7:0) || gr[reg2] (15:8)||gr [reg2] (23:16)||gr[reg2] (31:24) callt imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i ctpc pc + 2 (return pc) ctpsw psw adr ctbp + zero-extend (imm6 logically shift left by 1) pc ctbp + zero-extend (load-memory (adr, halfword) 5 5 5 1 0 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16[reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp 16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) 3 note 3 3 note 3 3 note 3 1 0 b b b 1 1 1 1 1 0 r r r r r clr1 reg2, [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 0) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 i i i i i cccc, imm5, reg2, reg3 w w w w w 0 1 1 0 0 0 c c c c 0 if conditions are satisfied then gr[reg3] sign-extend (imm5) else gr[reg3] gr[reg2] 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r cmov cccc, reg1, reg2, reg3 w w w w w 0 1 1 0 0 1 c c c c 0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1, reg2 r r r r r 0 0 1 1 1 1 r r r r r result gr[reg2] ? gr[reg1] 1 1 1 cmp imm5, reg2 r r r r r 0 1 0 0 1 1 i i i i i result gr[reg2] ? sign-extend (imm5) 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 ctret 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 pc ctpc psw ctpsw 4 4 4 r r r r r 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 dbret 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 pc dbpc psw dbpsw 4 4 4 r r r r r dbtrap 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 dbpc pc + 2 (return pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 di 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 psw.id 1 1 1 1 note 1
appendix c instruction set list 679 user?s manual u15195ej5v0ud (2/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat 0 0 0 0 0 1 1 0 0 1 i i i i il imm5, list12 l l l l l l l l l l l 0 0 0 00 sp sp + zero-extend (imm5 l ogically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list 12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 0 0 0 0 0 1 1 0 0 1 i i i i il dispose imm5, list12[reg1] l l l l l l l l l l l r r r rr sp sp + zero-extend (imm5 l ogically shift left by 2) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 r r r r r 1 1 1 1 1 1 r r r rr div reg1, reg2, reg3 w w w w w 0 1 0 1 1 0 0 0 0 00 gr[reg2] gr[reg2] gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1, reg2 r r r r r 0 0 0 0 1 0 r r r r r gr[reg2] gr[reg2] gr[reg1] note 6 35 35 35 r r r r r 1 1 1 1 1 1 r r r rr divh reg1, reg2, reg3 w w w w w 0 1 0 1 0 0 0 0 0 00 gr[reg2] gr[reg2] gr[reg1 ] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 r r r r r 1 1 1 1 1 1 r r r rr divhu reg1, reg2, reg3 w w w w w 0 1 0 1 0 0 0 0 0 10 gr[reg2] gr[reg2] gr[reg1 ] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 r r r r r 1 1 1 1 1 1 r r r rr divu reg1, reg2, reg3 w w w w w 0 1 0 1 0 0 0 0 0 10 gr[reg2] gr[reg2] gr[reg1 ] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 1 0 0 0 0 1 1 1 1 1 1 0 0 0 00 ei 0 0 0 0 0 0 0 1 0 1 1 0 0 0 00 psw.id 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 00 halt 0 0 0 0 0 0 0 1 0 0 1 0 0 0 00 stop 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 00 hsw reg2, reg3 w w w w w 0 1 1 0 1 0 0 0 1 00 gr[reg3] gr[reg2] (15:0)||gr[reg2] (31:16) 1 1 1 0 r r r r r 1 1 1 1 0 d d d d dd jarl disp22, reg2 d d d d d d d d d d d d d d d0 gr[reg2] pc + 4 pc pc + sign-extend (disp22) 3 3 3 jmp [reg1] 0 0 0 0 0 0 0 0 0 1 1 r r r rr pc gr[reg1] 4 4 4 0 0 0 0 0 1 1 1 1 0 d d d d dd jr disp22 d d d d d d d d d d d d d d d 0 pc pc + sign-extend (disp22) 3 3 3 r r r r r 1 1 1 0 0 0 r r r rr ld.b disp16[reg1], reg2 d d d d d d d d d d d d d d dd adr gr[reg1] + sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 11 r r r r r 1 1 1 1 0 b r r r rr ld.bu disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] zero (load-memory (adr, byte)) 1 1 note 11 r r r r r 1 1 1 0 0 1 r r r rr ld.h disp16[reg1], reg2 d d d d d d d d d d d d d d d 0 adr gr[reg1] + sign-extend (disp16) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2, regid r 0 r 0 r 0 r 0 r 0 1 0 1 0 1 0 1 0 1 0 1 1 r 0 r 0 r 0 r 0 r 0 sr[regid] gr[reg2] regid = psw 1 1 1 r r r r r 1 1 1 0 0 1 r r r rr ld.hu disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] zero-extend (load-memory (adr, halfword)) 1 1 note 11 note 7 notes 8, 10 note 8 note 12 note 8 note 5
appendix c instruction set list 680 user?s manual u15195ej5v0ud (3/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat r r r r r 1 1 1 0 0 1 r r r r r ld.w disp16[reg1], reg2 d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) gr[reg2] load-memory (adr, word) 1 1 note 11 reg1, reg2 r r r r r 0 0 0 0 0 0 r r r r r gr[reg2] gr[reg1] 1 1 1 imm5, reg2 r r r r r 0 1 0 0 0 0 i i i i i gr[reg2] sign-extend (imm5) 1 1 1 0 0 0 0 0 1 1 0 0 0 1 r r r r r gr[reg1] imm32 2 2 2 i i i i i i i i i i i i i i i i mov imm32, reg1 i i i i i i i i i i i i i i i i r r r r r 1 1 0 0 0 1 r r r r r movea imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] + sign-extend (imm16) 1 1 1 r r r r r 1 1 0 0 1 0 r r r r r movhi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] + (imm16 || 0 16 ) 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r reg1, reg2, reg3 w w w w w 0 1 0 0 0 1 0 0 0 0 0 gr[reg3] || gr[reg2] gr[reg2] gr[reg1] reg1 reg2 reg3, reg3 r0 1 2 note 14 2 r r r r r 1 1 1 1 1 1 i i i i i mul note 22 imm9, reg2, reg3 w w w w w 0 1 0 0 1 i i i i 0 0 gr[reg3] || gr[reg2] gr[reg2] sign-extend (imm9) 1 2 note 14 2 reg1, reg2 r r r r r 0 0 0 1 1 1 r r r r r gr[reg2] gr[reg2] note 6 gr[reg1] note 6 1 1 2 mulh imm5, reg2 r r r r r 0 1 0 1 1 1 i i i i i gr[reg2] gr[reg2] note 6 sign-extend (imm5) 1 1 2 r r r r r 1 1 0 1 1 1 r r r r r mulhi imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] note 6 imm16 1 1 2 r r r r r 1 1 1 1 1 1 r r r r r reg1, reg2, reg3 w w w w w 0 1 0 0 0 1 0 0 0 1 0 gr[reg3] || gr[reg2] gr[reg2] gr [reg1] reg1 reg2 reg3, reg3 r0 1 2 note 14 2 r r r r r 1 1 1 1 1 1 i i i i i mulu note 22 imm9, reg2, reg3 w w w w w 0 1 0 0 1 i i i i 1 0 gr[reg3]||gr[reg2] gr[reg2] zero-extend (imm9) 1 2 note 14 2 nop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 passes at least 1 cycle doing nothing. 1 1 1 not reg1, reg2 r r r r r 0 0 0 0 0 1 r r r r r gr[reg2] not (gr[reg1]) 1 1 1 0 0 1 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16[reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r r r not1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, z flag) 3 note 3 3 note 3 3 note 3 or reg1, reg2 r r r r r 0 0 1 0 0 0 r r r r r gr[reg2] gr[reg2] or gr [reg1] 1 1 1 0 r r r r r 1 1 0 1 0 0 r r r r r ori imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] or zero-extend (imm16) 1 1 1 0 0 0 0 0 0 1 1 1 1 0 i i i i i l list12, imm5 l l l l l l l l l l l 0 0 0 0 1 store-memory (sp-4, gr[reg in list12], word) sp sp ? 4 repeat 1 steps above until regs in list12 is stored sp sp-zero-extend (imm5) n+1 note 4 n+1 note 4 n+1 note 4 0 0 0 0 0 1 1 1 1 0 i i i i i l prepare list12, imm5, sp/imm note15 l l l l l l l l l l l f f 0 1 1 store-memory (sp-4, gr[reg in list12], word) gr[reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 note 8 note 13 note 13 note 16 imm16/imm32
appendix c instruction set list 681 user?s manual u15195ej5v0ud (4/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat 0 0 0 0 0 1 1 1 1 1 1 0 0 0 00 reti 0 0 0 0 0 0 0 1 0 1 0 0 0 0 00 if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 0 1 0 0 0 00 gr[reg2] gr[reg2] arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5, reg2 r r r r r 0 1 0 1 0 1 i i i ii gr[reg2] gr[reg2] arithmetically shift right by zero- extend (imm5) 1 1 1 0 r r r r r 1 1 1 1 1 1 0 c c cc sasf cccc, reg2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 00 if conditions are satisfied then gr[reg2] (gr[reg2] logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2] logically shift left by 1) or 00000000h 1 1 1 reg1, reg2 r r r r r 0 0 0 1 1 0 r r r rr gr[reg2] saturated (gr[reg2] + gr[reg1]) 1 1 1 satadd imm5, reg2 r r r r r 0 1 0 0 0 1 i i i ii gr[reg2] saturated (gr[reg2] sign-extend (imm5)) 1 1 1 satsub reg1, reg2 r r r r r 0 0 0 1 0 1 r r r rr gr[reg2] saturated (gr[reg2] ? gr[reg1]) 1 1 1 r r r r r 1 1 0 0 1 1 r r r rr satsubi imm16, reg1, reg2 i i i i i i i i i i i i i i ii gr[reg2] saturated (gr[reg1] ? sign-extend (imm16) 1 1 1 satsubr reg1, reg2 r r r r r 0 0 0 1 0 0 r r r rr gr[reg2] saturated (gr[reg1] ? gr[reg2]) 1 1 1 r r r r r 1 1 1 1 1 1 0 c c cc setf cccc, reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1 0 0 b b b 1 1 1 1 1 0 r r r rr bit#3, disp16 [reg1] d d d d d d d d d d d d d d dd adr gr[reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r rr set1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 00 adr gr[reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 1) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 1 0 0 0 0 00 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 r r r r r 0 1 0 1 1 0 i i i ii shl imm5, reg2 gr[reg2] gr[reg2] logically shift left by zero-extend (imm5) 1 1 1 0 r r r r r 1 1 1 1 1 1 r r r rr reg1, reg2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 00 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5, reg2 r r r r r 0 1 0 1 0 0 i i i ii gr[reg2] gr[reg2] logically shift right by zero-extend (imm5) 1 1 1 0 sld.b disp7[ep], reg2 r r r r r 0 1 1 0 d d d d d dd adr ep + zero-extend (disp7) gr[reg2] sign-extend (load-memory (adr, byte)) 1 1 note 9 sld.bu disp4[ep], reg2 r r r r r 0 0 0 0 1 1 0 d d dd adr ep + zero-extend (disp4) gr[reg2] zero-extend (load-memory (adr, byte)) 1 1 note 9 sld.h disp8[ep], reg2 r r r r r 1 0 0 0 d d d d d dd adr ep + zero-extend (disp8) gr[reg2] sign-extend (load-memory (adr, halfword)) 1 1 note 9 note 18 note 19
appendix c instruction set list 682 user?s manual u15195ej5v0ud (5/5) execution clock flags mnemonic operands opcode operation i r i cy ov s z sat sld.hu disp5[ep], reg2 r r r r r 0 0 0 0 1 1 1 d d d d adr ep + zero-extend (disp5) gr[reg2] zero-extend (load-memory (adr, halfword) 1 1 note 9 sld.w disp8[ep], reg2 r r r r r 1 0 1 0 d d d d d d 0 adr ep + zero-extend (disp8) gr[reg2] load-memory (adr, word) 1 1 note 9 sst.b reg2, disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep + zero-extend (disp7) store-memory (adr, gr[reg2], byte) 1 1 1 sst.h reg2, disp8[ep] r r r r r 1 0 0 1 d d d d d d d adr ep + zero-extend (disp8) store-memory (adr, gr[reg2], halfword) 1 1 1 sst.w reg2, disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adr ep + zero-extend (disp8) store-memory (adr, gr[reg2], word) 1 1 1 r r r r r 1 1 1 0 1 0 r r r r r st.b reg2, disp16 [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], byte) 1 1 1 r r r r r 1 1 1 0 1 1 r r r r r st.h reg2, disp16 [reg1] d d d d d d d d d d d d d d d 0 adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], halfword) 1 1 1 r r r r r 1 1 1 0 1 1 r r r r r st.w reg2, disp16 [reg1] d d d d d d d d d d d d d d d 1 adr gr[reg1] + sign-extend (disp16) store-memory (adr, gr[reg2], word) 1 1 1 r r r r r 1 1 1 1 1 1 r r r r r stsr regid, reg2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 gr[reg2] sr[regid] 1 1 1 sub reg1, reg2 r r r r r 0 0 1 1 0 1 r r r r r gr[reg2] gr[reg2] ? gr[reg1] 1 1 1 subr reg1, reg2 r r r r r 0 0 1 1 0 0 r r r r r gr[reg2] gr[reg1] ? gr[reg2] 1 1 1 switch reg1 0 0 0 0 0 0 0 0 0 1 0 r r r r r adr (pc + 2) + gr[reg1] logically shift left by 1) pc (pc + 2) + (sign-extend (load-memory (adr, halfword)) logically shift left by 1 5 5 5 sxb reg1 0 0 0 0 0 0 0 0 1 0 1 r r r r r gr[reg1] sign-extend (gr[reg1] (7:0)) 1 1 1 sxh reg1 0 0 0 0 0 0 0 0 1 1 1 r r r r r gr[reg1] sign-extend (gr[reg1] (15:0)) 1 1 1 0 0 0 0 0 1 1 1 1 1 1 i i i i i trap vector 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 eipc pc + 4 (return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1, reg2 r r r r r 0 0 1 0 1 1 r r r r r result gr[reg2] and gr[reg1] 1 1 1 0 1 1 b b b 1 1 1 1 1 0 r r r r r bit#3, disp16 [reg1] d d d d d d d d d d d d d d d d adr gr[reg1] + sign-extend (disp16) z flag not(load-memory-bit(adr,bit#3)) 3 note 3 3 note 3 3 note 3 r r r r r 1 1 1 1 1 1 r r r r r tst1 reg2, [reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1, reg2 r r r r r 0 0 1 0 0 1 r r r r r gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 r r r r r 1 1 0 1 0 1 r r r r r xori imm16, reg1, reg2 i i i i i i i i i i i i i i i i gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 0 0 0 0 0 0 0 0 1 0 0 r r r r r gr[reg1] zero-extend (gr[reg1] (7:0)) 1 1 1 zxh reg1 0 0 0 0 0 0 0 0 1 1 0 r r r r r gr[reg1] zero-extend (gr[reg1] (15:0)) 1 1 1 notes 18, 20 note 21 note 19 note 21 note 8 note 8
appendix c instruction set list 683 user?s manual u15195ej5v0ud notes 1. dddddddd is the higher 8 bits of disp9. 2. 4 if there is an instruction to overwrite the contents of the psw immediately before. 3. if there is no wait state (3 + num ber of read access wait states) 4. n is the total number of load registers in list12 (a ccording to the number of wait states. if there are no wait states, n is the total number of registers in list12. when n = 0, the operation is the same as n = 1.) 5. rrrrr : other than 00000 6. only the lower halfword of data is valid. 7. ddddddddddddddddddddd is the higher 21 bits of disp22. 8. ddddddddddddddd is the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states) 10. b : bit 0 of disp16 11. according to the number of wait stat es (2 if there are no wait states) 12. in this instruction, although the source register is regarded as reg2 for convenience of the mnemonic description, the reg1 field is used in the opcode. t herefore, the meanings of register specifications assigned in the mnemonic description and in the opc ode differ from those in other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii : lower 5 bits of imm9 iiii : higher 4 bits of imm9 14. shortened by 1 clock if reg2 = reg3 (lower 32 bits of result are not written to register) or reg3 = r0 (higher 32 bits of result are not written to register). 15. sp/imm: specify in bits 19 and 20 of sub-opcode. 16. ff = 00: load sp in ep. 01: load sign-extended 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit immediate data (bits 47 to 32) l ogically shifted 16 bits to the right in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. n + 3 clocks when imm = imm32 18. rrrrr : other then 00000 19. ddddddd is the higher 7 bits of disp8. 20. dddd is the higher 4 bits of disp5. 21. dddddd is the higher 6 bits of disp8. 22. in the mul reg1, reg2, reg3 and mulu reg1, reg2, reg3 instructions, prevent a combination of registers that satisfies all of the following cond itions. the operation when the instructions are executed with the following conditi ons satisfied is not guaranteed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0
684 user's manual u15195ej5v0ud appendix d revision history d.1 major revisions in this edition (1/2) page description throughout ? addition of the following lead-free products pd703114gc-xxx-8eu-a, 703114gc(a)-xxx-8eu-a, ? 703114gf-xxx-3ba-a, 70f3114gc-8eu-a, 70f3114gc(a)-8eu-a, 70f3114gf-3ba-a ? addition of flpmc register p. 18 addition of note to table 1-1 differences between v850e/ia1 and v850e/ia2 p. 19 change of number of instructions in 1.2 features p. 49 addition of note to table 3-2 system register numbers pp. 50, 51, 53, 54 addition of 3.2.2 (1) interrupt status saving registers (eipc, eipsw) , (2) nmi status saving registers (fepc, fepsw) , (5) callt execution status saving registers (ctpc, ctpsw) , (6) exception/debug trap status saving registers (dbpc, dbpsw) , and (7) callt base pointer (ctbp) p. 79 addition of 3.4.11 (2) restriction on conflict between sld instruction and interrupt request pp. 114, 115 modification of description in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) p. 116 modification of description in 6.3.7 dma restart register (drst) pp. 117, 119 modification of description and addition of caution to 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) p. 123 addition of figure 6-7 block transfer example p. 123 modification of description of caution in 6.5.1 two-cycle transfer p. 124 addition of note to table 6-1 relationship between transfer type and transfer target p. 125 deletion of a part of description in 6.7 dma channel priorities pp. 125, 126 modification of description in 6.8 next address setting function p. 129 addition of figure 6-9 example of forcible termination of dma transfer p. 132 modification of descriptions in 6.14 (2) transfer of misaligned data and (4) dma start factors p. 132 addition of 6.14 (5) program execution and dma transfer with internal ram p. 134 addition of caution to 7.1 features pp. 135, 137 addition of note and remark to table 7-1 interrupt/exception source list p. 160 addition of caution to 7.3.8 (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) p. 169 addition of caution to 7.5.2 (2) restore p. 173 modification of description in 7.8 periods in which cpu does not acknowledge interrupts p. 185 modification of description in 8.5.2 (3) power save control register (psc) p. 189 addition of description to table 8-4 operation status in idle mode p. 190 addition of caution to 8.5.4 (2) (a) release by a non-maskable interrupt request or an unmasked maskable interrupt request p. 191 addition of description to table 8-6 operation status in software stop mode p. 192 addition of caution to 8.5.5 (2) (a) release by a non-maskable interrupt request or an unmasked maskable interrupt request p. 279 addition of 9.1.6 (4) [output waveform width with respect to set value] (d) when bfcmnx = 0000h is set while dtmnx = 000h or tm0cedn bit = 1 p. 281 addition of 9.1.6 (4) [output waveform width with respect to set value] (e) when bfcmnx = cm0n3 = a is set p. 297 addition of caution to 9.2.3 (1) timer 10 (tm10) p. 305 modification of de scription in table in 9.2.4 (6) (b) udc mode (cmd bit of tum0 register = 1) p. 313 modification of description in table 9-8 list of count operations in udc mode
appendix d revision history 685 user's manual u15195ej5v0ud (2/2) page description p. 337 addition of 9.3.4 (6) (a) caution for pwm output change timing p. 410 addition of remark to figure 10-2 asynchronous serial interface 0 block diagram p. 414 deletion of a part of description and addition of caution to 10.2.3 (2) asynchronous serial interface status register 0 (asis0) p. 438 addition of description to 10.2.6 (5) transfer rate during continuous transmission p. 438 addition of description to 10.2.7 cautions (2) p. 459 modification of figure 10-20 asynchronous serial interface reception completion interrupt timing p. 583 addition of caution to 12.5.2 (1) timer 10 noise elimination time selection register (nrc10) p. 584 addition of caution to 12.5.2 (2) timer 3 noise elimination time selection register (nrc3) p. 586 addition of caution to 12.5.3 (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) p. 611 addition of 15.6 programming method p. 614 addition of 15.7 flash memory programming by self-programming p. 635 addition of 15.8 how to distinguish flash memory and mask rom versions p. 663 addition of (3) and (4) to table 18-1 surface mounting type soldering conditions p. 626 in previous edition deletion of appendix a notes
appendix d revision history 686 user's manual u15195ej5v0ud d.2 revision history up to previous edition the following table shows the revision history up to the pr evious edition. the ?applied to:? column indicates the chapters of each edition in which the revision was applied. (1/7) edition major revision up to previous edition applied to: change of description on memory space in 1.2 features change of description on regulator in 1.2 features deletion of note in 1.4 ordering information chapter 1 introduction change of astb (pct6) pin status in 2.2 pin status change of i/o circuit type from 5-k to 5-ac in 2.4 types of pin i/o circuits and connection of unused pins change of i/o circuit type from 5-k to 5-ac in 2.5 pin i/o circuits chapter 2 pin functions modification of figure 3-3 memory map addition and deletion of description in 3.4.5 (2) internal ram area modification of description in 3.4.5 (4) external memory area deletion of description in 3.4.7 (1) program space deletion of part of description in example of wrap-around application in 3.4.7 (2) data space modification of figure 3-5 recommended memory map addition and modification of description in 3.4.8 peripheral i/o registers addition and modification of description in 3.4.10 system wait control register (vswc) chapter 3 cpu function addition and modification of description in 4.2.1 pin status during internal rom, internal ram, and peripheral i/o access addition and modification of description in 4.3 memory block function addition of 4.3.1 chip select control function addition of description in 4.4.1 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) addition of indication of note in 4.5.1 number of access clocks addition of 4.5.2 bus sizing function addition of description in 4.6.1 (1) data wait control registers 0, 1 (dwc0, dwc1) addition of description in 4.6.1 (2) address wait control register (awc) change of timing in figure 4-2 example of wait insertion addition of description in 4.7 (1) bus cycle control register (bcc) chapter 4 bus control function addition of description in 6.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) change of description when ds1, ds0 bits = 1, 0 in 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) addition of cautions in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) change of description on bit that can be manipulated in 6.3.6 dma disable status register (ddis) change of description on bit that can be manipulated in 6.3.7 dma restart register (drst) addition of description in 6.5.1 single transfer mode addition of description in 6.5.2 single-step transfer mode change of transfer status when transfer target is in internal ram in table 6-1 relationship between transfer type and transfer target addition of caution in 6.8 dma channel priorities 2nd addition of 6.14 (5) dma start factors chapter 6 dma functions (dma controller)
appendix d revision history 687 user's manual u15195ej5v0ud (2/7) edition major revision up to previous edition applied to: addition of generating source of cc10ic1 register in table 7-1 interrupt/exception source list change of description in figure 7-2 acknowledging non-maskable interrupt request addition of caution and change of description in 7.3.8 (2) signal edge selection register 10 (sesa10) addition of caution in 7.3.8 (3) valid edge selection register (sesc) addition and change of description in 7.3.8 (4) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) modification of description in 7.8 periods in which interrupts are not acknowledged chapter 7 interrupt/ exception processing function change of description on bits that can be m anipulated and data setting sequences to ckc in 8.3.4 clock control register (ckc) modification of note in figure 8-1 power save mode state transition diagram modification of operation status of astb in table 8-4 operation status in idle mode addition and modification of description in 8.5.4 (2) release of idle mode change of operation status of astb in table 8-6 operation status in software stop mode addition and modification of description in 8.5.5 (2) release of software stop mode addition and modification of descripti on and change of timing chart in 8.6.1 (1) securing the time using an on-chip time base counter modification of timing chart in 8.6.1 (2) securing the time according to the signal level width (reset pin input) chapter 8 clock generation function addition of a table in 9.1.2 function overview (timer 0) addition of caution in table 9-2 operation modes of timer 0 addition and modification of description in 9.1.5 (3) timer unit control registers 00, 01 (tuc00, tuc01) modification of description in 9.1.5 (4) timer output mode registers 0, 1 (tomr0, tomr1) addition and modification of description in 9.1.5 (6) pwm software timing output registers 0, 1 (psto0, psto1) and addition of figures 9-9 to 9-14 addition of remark in 9.1.6 operation addition of remark in 9.1.6 (2) pwm mode 0: triangular wave modulation (right-left symmetric waveform control) [output waveform width in respect to set value] addition of remark in 9.1.6 (3) pwm mode 1: triangular wave modulation (right-left asymmetric waveform control) [output waveform width in respect to set value] addition of remark in 9.1.6 (4) pwm mode 2: sawtooth wave modulation [output waveform width in respect to set value] addition of remark in figure 9-30 tm0cen bit write and tm0n timer operation timing change of description in 9.2.2 function overview (timer 1) change of description in table 9-5 timer 1 configuration list modification of figure 9-45 block diagram of timer 1 modification of description in 9.2.4 (1) timer 1/timer 2 clock selection register (prm02) addition of description in 9.2.4 (3) timer control register 10 (tmc10) modification of description in 9.2.4 (5) signal edge selection register 10 (sesa10) change of description in figure 9-46 tm10 block diagram (during pwm output operation) change of description in 9.3.2 function overview (timer 2) change of description in table 9-9 timer 2 configuration list addition of table 9-10 capture/compare operation sources addition of table 9-11 output level sources during timer output 2nd change of description in figure 9-62 block diagram of timer 2 chapter 9 timer/counter function (real- time pulse unit)
appendix d revision history 688 user's manual u15195ej5v0ud (3/7) edition major revision up to previous edition applied to: modification of description in 9.3.4 (1) timer 1/timer 2 clock selection register (prm02) modification of description in 9.3.4 (2) timer 2 clock stop register 0 (stopte0) addition of caution and modification in 9.3.4 (5) timer 2 time base control register 0 (tcre0) addition of note and deletion of caution in figure 9-95 cycle measurement operation timing example modification of description in figure 9-97 example of timing during tm4 operation chapter 9 timer/counter function (real- time pulse unit) modification of caution in 10.2.3 (1) asynchronous serial interface mode register 0 (asim0) change of description on bits that can be manipulated in 10.2.3 (2) asynchronous serial interface status register 0 (asis0) addition of caution and modifi cation of description in 10.2.3 (3) asynchronous serial interface transmission status register 0 (asif0) change of description on bits that can be manipulated in 10.2.3 (4) receive buffer register (rxb0) change of description on bits that can be manipulated in 10.2.3 (5) transmit buffer register 0 (txb0) addition and modification of description in 10.2.5 (3) continuous transmission operation addition of figure 10-5 continuous transmission processing flow addition of note and change of description in table in figure 10-6 continuous transmission starting procedure change of description of table in figure 10-7 continuous transmission end procedure addition of cautions in figure 10-8 asynchronous serial interface reception completion interrupt timing change of description on bits that can be manipulated and addition of caution in 10.2.6 (2) (a) clock select register 0 (cksr0) change of description on bits that can be manipulated in 10.2.6 (2) (b) baud rate generator control register 0 (brgc0) addition of (2) in 10.2.7 cautions change of description on bits that can be manipulated in 10.3.3 (4) 2-frame continuous reception buffer register 1 (rxb1)/receive buffer register l1 (rxbl1) addition of caution in 10.3.4 (1) reception completion interrupt (intsr1) addition of 10.3.5 (3) continuous transmission of 3 or more frames change of description on bits that can be manipulated in 10.3.7 (2) (c) prescaler compare register 1 (prscm1) addition of 10.3.7 (3) allowable baud rate range during reception addition of 10.3.7 (4) transfer rate in 2-frame continuous reception change of description on bits that can be manipulated in 10.4.3 (4) clocked serial interface receive buffer registers l0, l1 (sirbl0, sirbl1) change of description on bits that can be manipulated in 10.4.3 (6) clocked serial interface read-only receive buffer registers l0, l1 (sirbel0, sirbel1) change of description on bits that can be manipulated in 10.4.3 (8) clocked serial interface transmit buffer registers l0, l1 (sotbl0, sotbl1) change of description on bits that can be manipulated in 10.4.3 (10) clocked serial interface initial transmit buffer registers l0, l1 (sotbfl0, sotbfl1) change of description on bits that can be manipulated in 10.4.3 (12) serial i/o shift registers l0, l1 (siol0, siol1) modification of caution description in 10.4.6 (2) (b) prescaler mode register 3 (prsm3) 2nd change of description on bits that can be manipulated and caution in 10.4.6 (2) (c) prescaler compare register 3 (prscm3) chapter 10 serial interface function
appendix d revision history 689 user's manual u15195ej5v0ud (4/7) edition major revision up to previous edition applied to: addition of caution in 11.4 (1) a/d scan mode registers 00 and 10 (adscm00, asdscm10) change of description on bits that can be mani pulated and change of explanation of fr2 to fr0 bits in 11.4 (2) a/d scan mode registers 01 and 11 (adscm01, adscm11) addition of 11.11.6 timing that makes the a/d conversion result undefined addition of 11.12 how to read a/d converter characteristics table chapter 11 a/d converter modification of description in 12.2 (1) functions of each port modification of figure 12-4 type d block diagram modification of figure 12-7 type g block diagram modification of figure 12-8 type h block diagram modification of figure 12-13 type m block diagram addition of figure 12-14 type n block diagram change of description in 12.3.6 (1) operation in control mode modification of figure 12-15 example of noise elimination timing addition of caution and change of description in 12.4.3 (1) timer 2 input filter mode registers 0 to 5 (fem0 to fem5) chapter 12 port functions addition of 13.2 (2) <1> reset circuit and <2> reset timing addition of item and change of description in table 13-2 initial values of cpu, internal ram, and on-chip peripheral i/o after reset chapter 13 reset function modification of description in 14.1 features addition and modification of description in 14.2 functional outline modification of figure 14-1 example of connection when using n-ch transistor addition of figure 14-2 mount pad dimensions when mounted on 2sd1950 (vl standard product) (glass epoxy board) (unit: mm) addition of figure 14-3 connection when using external regulator addition and modification of description in caution in 14.4 (1) regulator control register (regc) chapter 14 regulator addition of caution in 15.2 writing using flash programmer addition of description in 15.2 (2) off-board programming modification of description in 15.3 programming environment change of description in 15.4 (1) uart0 change of description in 15.4 (2) csi0 change of description in 15.4 (3) handshake-supported csi communication modification of description in 15.5.8 power supply chapter 15 flash memory ( pd70f3114) 2nd change of description in b.2 instruction set (alphabetical order) appendix b instruction set list addition of 100-pin plastic qfp (14 20) package throughout addition of table 1-2 differences between v850e/ia1 and v850e/ia2 register setting values chapter 1 introduction modification of description in 4.2.1 pin status during internal rom, internal ram, and on- chip peripheral i/o access addition of caution to 4.3.1 (1) chip area select control registers 0, 1 (csc0, csc1) modification and deleti on of description in 4.9.1 program space chapter 4 bus control function addition of description to 6.3.1 (1) dma source address registers 0h to 3h (dsa0h to dsa3h) 3rd addition of description to 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) chapter 6 dma functions (dma controller)
appendix d revision history 690 user's manual u15195ej5v0ud (5/7) edition major revision up to previous edition applied to: addition of description and caution to 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) addition of description and caution to and modification of bit description in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) addition of description to 6.3.6 dma disable status register (ddis) addition of description to 6.3.7 dma restart register (drst) addition of caution to 6.6.1 two-cycle transfer addition of description to remark in 6.13 forcible termination modification of description in 6.14 (3) times related to dma transfer chapter 6 dma functions (dma controller) addition of caution to 7.3.4 interrupt control register (xxicn) addition of caution to 7.3.6 in-service priority register (ispr) modification of description in figure 7-14 pipeline operation at interrupt request acknowledgment (outline) chapter 7 interrupt/ exception processing function modification of description in table 9-2 operation modes of timer 0 modification of description in table 9-4 operation modes of timer 0 (tm0n) modification of description in remark in 9.1.6 (2) pwm mode 0: triangular wave modulation (right-left symmetric waveform control) modification of figures 9-15 , 9-17 to 9-20 , 9-22 to 9-30 , and 9-32 to 9-35 chapter 9 timer/counter function (real- time pulse unit) modification of maximum transfer rate in 10.2.1 features addition of description to table 10-3 baud rate generator setting data chapter 10 serial interface function addition of caution to 12.2 (1) functions of each port chapter 12 port functions addition of description to 15.2 (2) off-board programming chapter 15 flash memory ( pd70f3114) addition of chapter 16 electrical specifications chapter 16 electrical specifications addition of chapter 17 package drawings chapter 17 package drawings addition of chapter 18 recommended soldering conditions chapter 18 recommended soldering conditions addition of appendix a notes on target system design appendix a notes on target system design modification of description in c.2 instruction set (alphabetical order) appendix c instruction set list addition of appendix d index appendix d index 3rd addition of appendix e revision history appendix e revision history
appendix d revision history 691 user's manual u15195ej5v0ud (6/7) edition major revision up to previous edition applied to: ? addition of the following products pd703114gc(a)- -8eu, 70f3114gc(a)-8eu throughout addition of note 2 to 1.5 pin configuration (top view) chapter 1 introduction addition of description to 6.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) addition of caution 2 to 6.3.1 dma source address registers 0h to 3h (dsa0h to dsa3h) addition of description to 6.3.2 dma destination address registers 0 to 3 (dda0 to dda3) addition of caution 2 to 6.3.2 (1) dma destination address registers 0h to 3h (dda0h to dda3h) addition of description and cautions 1 and 2 to 6.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) addition of caution 2 to 6.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) modification/addition of description of caution in 6.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) modification of description in 6.3.7 dma restart register (drst) addition of description to 6.3.8 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) addition of description to remark in 6.7.1 transfer type and transfer target deletion of note from table 6-2 external bus cycles during dma transfer (two-cycle transfer) modification of description in 6.9 next address setting function addition of cautions 1 and 2 to 6.10 dma transfer start factors modification of description in 6.11 forcible suspension addition of 6.13.1 restrictions on forcible termination of dma transfer modification of description in 6.14 time required for dma transfer addition of 6.15 (5) restrictions related to automatic clearing of tcn bit of dchcn register and (6) read values of dsan and ddan registers chapter 6 dma functions (dma controller) modification of description in chapter 7 interrupt/exception processing function chapter 7 interrupt/ exception processing function addition of caution 2 to 9.1.6 (2) pwm mode 0: triangular wave modulation (right-left symmetric waveform control) addition of note to 9.3.4 (3) timer 2 count clock/control edge selection register 0 (cse0) addition of 9.3.6 pwm output operation in timer 2 compare mode modification of description in figure 9-91 tm3 compare operation example (set/reset output mode) chapter 9 timer/counter function (real- time pulse unit) addition of caution 2 to 10.2.3 (1) asynchronous serial interface mode register 0 (asim0) addition of caution to 10.2.5 (3) continuous transmission operation addition of description of transfer rate to 10.3.1 features addition of cautions 1 and 2 to 10.3.3 (1) asynchronous serial interface mode register 10 (asim10) addition of caution 3 to 10.3.7 (2) (c) prescaler compare register 1 (prscm1) 4th modification of description in table 10-8 baud rate generator setting data (brg = f xx /2) chapter 10 serial interface function
appendix d revision history 692 user's manual u15195ej5v0ud (7/7) edition major revision up to previous edition applied to: addition of caution to 12.3.2 (1) operation in control mode addition of caution to 12.3.3 (1) operation in control mode addition of caution to 12.3.4 (1) operation in control mode modification of descripti on of bits 7 to 5 in 12.3.4 (2) (a) port 3 mode register (pm3) addition of caution to 12.3.5 (1) operation in control mode addition of note to 12.3.9 (1) operation in control mode addition of 12.4 operation of port function addition of 12.6 cautions chapter 12 port functions addition of description to caution 2 in 13.2 (2) <3> description chapter 13 reset function addition of caution to data retention characteristics in 16.1 normal operation mode addition of (b) to ac test input test points in 16.1 normal operation mode change of description of stabilization capacitance in the conditions column in 16.1 (3) regulator output stabilization time modification of description of t hstwt1 in 16.1 (5) (a) clkout asynchronous addition of caution to 16.1 (5) (c) read cycle (clkout synchronous/asynchronous, 1 wait) addition of caution to 16.1 (5) (d) write cycle (clkout synchronous/asynchronous, 1 wait) addition of remark to 16.1 (8) timer operating frequency addition of description of tx d1 output delay time to 16.1 (11) (a) clocked master mode modification of descriptions in v pp supply voltage (v ppl ) row of basic characteristics in 16.2 flash memory programming mode chapter 16 electrical specifications addition of appendix a notes appendix a notes addition of note 22 to mul and mulu in d.2 instruction set (alphabetical order) in appendix d appendix c instruction set list 4th modification of description in appendix e revision history appendix e revision history

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